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soloist_hu |
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Release 10.1 Trace (nt)
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Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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C:\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise
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X:/Display_Controller/Display_Controller.ise -intstyle ise -e 3 -s 4 -xml
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Display_Controller Display_Controller.ncd -o Display_Controller.twr
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Display_Controller.pcf -ucf vga_pins.ucf
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Design file: Display_Controller.ncd
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Physical constraint file: Display_Controller.pcf
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Device,package,speed: xc3s1000,ft256,-4 (PRODUCTION 1.39 2008-01-09)
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Report level: error report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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Data Sheet report:
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-----------------
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All values displayed in nanoseconds (ns)
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Clock to Setup on destination clock clk
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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clk | 4.229| | | |
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---------------+---------+---------+---------+---------+
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Analysis completed Sun Nov 23 21:13:53 2008
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--------------------------------------------------------------------------------
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Trace Settings:
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-------------------------
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Trace Settings
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Peak Memory Usage: 91 MB
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