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[/] [bu_pacman/] [tags/] [arelease/] [Sources/] [ps2/] [ps2_decode.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 soloist_hu 
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: BU PACMAN TEAM
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// Engineer: Huaxin Dai
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//
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// Create Date:    21:02:09 11/14/2008
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// Design Name:          PS/2 Interface
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// Module Name:    ps2_decode
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// Project Name:   BU PACMAN
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// Target Devices: XC3S1000
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// Tool versions:  ISE 10.1
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// Description:    PS/2 interface, key decode part.
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//
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// Dependencies:   ps2_receive.v
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ps2_decode(
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         input in_clk,
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    input in_reset,
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    input [7:0]in_data,
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    output reg [6:0]out_data
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    );
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always @(posedge in_clk)
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if(in_reset)
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        begin
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        out_data <= 7'b0000001;
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        end
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else
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        begin
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                case(in_data)
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                        8'h1C:begin//left, A
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                                                out_data <= 7'b0010000;
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                                        end
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                        8'h1B:begin//down, S
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                                                out_data <= 7'b0100000;
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                                        end
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                        8'h23:begin//right, D
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                                                out_data <= 7'b0001000;
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                                        end
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                        8'h1D:begin//up, W
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                                                out_data <= 7'b1000000;
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                                        end
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                        8'h2D:begin//reset, R
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                                                out_data <= 7'b0000100;
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                                        end
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                        8'h4D:begin//pause, P
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                                                out_data <= 7'b0000010;
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                                        end
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                default: begin//stop
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                                                out_data <= 7'b0000001;
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                                        end
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                endcase
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        end
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endmodule

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