No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med".
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CLK Net:clk3/div_clk may have excessive skew because
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0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
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N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.
