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[/] [bu_pacman/] [tags/] [arelease/] [blk_mem_gen_v2_7_readme.txt] - Blame information for rev 6
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The following files were generated for 'blk_mem_gen_v2_7' in directory
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X:\My Documents\mem40\:
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blk_mem_gen_v2_7.mif:
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Memory Initialization File which is automatically generated by the
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CORE Generator System for some modules when a simulation flow is
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specified. A MIF data file is used to support HDL functional
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simulation of modules which use arrays of values.
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blk_mem_gen_v2_7.ngc:
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Binary Xilinx implementation netlist file containing the information
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required to implement the module in a Xilinx (R) FPGA.
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blk_mem_gen_v2_7.v:
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Verilog wrapper file provided to support functional simulation.
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This file contains simulation model customization data that is
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passed to a parameterized simulation model for the core.
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blk_mem_gen_v2_7.veo:
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VEO template file containing code that can be used as a model for
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instantiating a CORE Generator module in a Verilog design.
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blk_mem_gen_v2_7.xco:
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CORE Generator input file containing the parameters used to
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regenerate a core.
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blk_mem_gen_v2_7_blk_mem_gen_v2_7_xst_1.ngc_xst.xrpt:
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Please see the core data sheet.
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blk_mem_gen_v2_7_flist.txt:
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Text file listing all of the output files produced when a customized
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core was generated in the CORE Generator.
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blk_mem_gen_v2_7_readme.txt:
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Text file indicating the files generated and how they are used.
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blk_mem_gen_v2_7_xmdf.tcl:
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ISE Project Navigator interface file. ISE uses this file to determine
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how the files output by CORE Generator for the core can be integrated
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into your ISE project.
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Please see the Xilinx CORE Generator online help for further details on
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generated files and how to use them.
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