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[/] [bu_pacman/] [tags/] [arelease/] [mem40_16.cgp] - Blame information for rev 6

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Line No. Rev Author Line
1 3 soloist_hu 
# Date: Fri Nov 21 01:26:23 2008
2 
SET addpads = False
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SET asysymbol = False
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = Verilog
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SET device = xc3s200
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SET devicefamily = spartan3
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SET flowvendor = Other
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = ft256
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SET removerpms = False
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SET simulationfiles = Behavioral
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SET speedgrade = -4
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SET verilogsim = True
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SET vhdlsim = False
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SET workingdirectory = "X:\My Documents\mem40\tmp"
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