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[/] [bu_pacman/] [tags/] [arelease/] [templates/] [coregen.xml] - Blame information for rev 6

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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
blk_mem_gen_v2_7 YourInstanceName (
    .clka(clka),
    .dina(dina), // Bus [15 : 0]
    .addra(addra), // Bus [15 : 0]
    .ena(ena),
    .wea(wea), // Bus [0 : 0]
    .douta(douta), // Bus [15 : 0]
    .clkb(clkb),
    .dinb(dinb), // Bus [15 : 0]
    .addrb(addrb), // Bus [15 : 0]
    .enb(enb),
    .web(web), // Bus [0 : 0]
    .doutb(doutb)); // Bus [15 : 0]
 
 
                
                
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
fifo_generator_v4_3 YourInstanceName (
    .din(din), // Bus [15 : 0]
    .rd_clk(rd_clk),
    .rd_en(rd_en),
    .rst(rst),
    .wr_clk(wr_clk),
    .wr_en(wr_en),
    .dout(dout), // Bus [15 : 0]
    .empty(empty),
    .full(full));
 
 
                
        
        
                
                
                
                
        




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7			`// The following must be inserted into your Verilog file for this`
8			`// core to be instantiated. Change the instance name and port connections`
9			`// (in parentheses) to your own signal names.`
10
11			`blk_mem_gen_v2_7 YourInstanceName (`
12			`.clka(clka),`
13			`.dina(dina), // Bus [15 : 0]`
14			`.addra(addra), // Bus [15 : 0]`
15			`.ena(ena),`
16			`.wea(wea), // Bus [0 : 0]`
17			`.douta(douta), // Bus [15 : 0]`
18			`.clkb(clkb),`
19			`.dinb(dinb), // Bus [15 : 0]`
20			`.addrb(addrb), // Bus [15 : 0]`
21			`.enb(enb),`
22			`.web(web), // Bus [0 : 0]`
23			`.doutb(doutb)); // Bus [15 : 0]`
24
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30			`// The following must be inserted into your Verilog file for this`
31			`// core to be instantiated. Change the instance name and port connections`
32			`// (in parentheses) to your own signal names.`
33
34			`fifo_generator_v4_3 YourInstanceName (`
35			`.din(din), // Bus [15 : 0]`
36			`.rd_clk(rd_clk),`
37			`.rd_en(rd_en),`
38			`.rst(rst),`
39			`.wr_clk(wr_clk),`
40			`.wr_en(wr_en),`
41			`.dout(dout), // Bus [15 : 0]`
42			`.empty(empty),`
43			`.full(full));`
44
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[/] [bu_pacman/] [tags/] [arelease/] [templates/] [coregen.xml] - Blame information for rev 6