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[/] [bu_pacman/] [tags/] [arelease/] [test_memory.syr] - Blame information for rev 6

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Release 10.1 - xst K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to X:/Display_Controller/xst/projnav.tmp
 
 
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
 
--> Parameter xsthdpdir set to X:/Display_Controller/xst
 
 
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
 
--> Reading design: test_memory.prj
 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT
 
 
=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "test_memory.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
 
---- Target Parameters
Output File Name                   : "test_memory"
Output Format                      : NGC
Target Device                      : xc3s200-4-ft256
 
---- Source Options
Top Module Name                    : test_memory
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : auto
Automatic Register Balancing       : No
 
---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES
 
---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : test_memory.lso
Keep Hierarchy                     : NO
Netlist Hierarchy                  : as_optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5
 
=========================================================================
 
 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "generate_add.v" in library work
Compiling verilog file "clock_divider.v" in library work
Module  compiled
Compiling verilog file "blk_mem_gen_v2_7.v" in library work
Module  compiled
Compiling verilog file "test_memory.v" in library work
Module  compiled
Module  compiled
No errors in compilation
Analysis of file <"test_memory.prj"> succeeded.
 
 
=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module  in library .
 
Analyzing hierarchy for module  in library  with parameters.
        NBIT = "00000000000000000000000000010110"
        NDIV = "00000010111110101111000010000000"
 
Analyzing hierarchy for module  in library .
 
 
=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module .
WARNING:Xst:2211 - "blk_mem_gen_v2_7.v" line 33: Instantiating black box module .
Module  is correct for synthesis.
 
Analyzing module  in library .
        NBIT = 32'sb00000000000000000000000000010110
        NDIV = 32'sb00000010111110101111000010000000
Module  is correct for synthesis.
 
Analyzing module  in library .
Module  is correct for synthesis.
 
 
=========================================================================
*                           HDL Synthesis                               *
=========================================================================
 
Performing bidirectional port resolution...
 
Synthesizing Unit .
    Related source file is "clock_divider.v".
    Found 22-bit up counter for signal .
    Summary:
        inferred   1 Counter(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is "generate_add.v".
    Found 16-bit up counter for signal .
    Summary:
        inferred   1 Counter(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is "test_memory.v".
WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal  is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit  synthesized.
 
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# Counters                                             : 1
 16-bit up counter                                     : 1
 
=========================================================================
 
=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
 
Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx\10.1\ISE.
Reading core .
Loading core  for timing and area information for instance .
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# Counters                                             : 1
 16-bit up counter                                     : 1
 
=========================================================================
 
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
 
Optimizing unit  ...
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block test_memory, actual ratio is 7.
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Found no macro
=========================================================================
 
=========================================================================
*                           Partition Report                             *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : test_memory.ngr
Top Level Output File Name         : test_memory
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO
 
Design Statistics
# IOs                              : 10
 
Cell Usage :
# BELS                             : 439
#      GND                         : 2
#      LUT3                        : 214
#      LUT4                        : 64
#      MUXF5                       : 104
#      MUXF6                       : 36
#      MUXF7                       : 18
#      VCC                         : 1
# FlipFlops/Latches                : 10
#      FDE                         : 10
# RAMS                             : 38
#      RAMB16_S1_S1                : 15
#      RAMB16_S2_S2                : 3
#      RAMB16_S9_S9                : 20
# IO Buffers                       : 8
#      OBUF                        : 8
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 3s200ft256-4
 
 Number of Slices:                      144  out of   1920     7%
 Number of Slice Flip Flops:             10  out of   3840     0%
 Number of 4 input LUTs:                278  out of   3840     7%
 Number of IOs:                          10
 Number of bonded IOBs:                   8  out of    173     4%
 Number of BRAMs:                        38  out of     12   316% (*)
 
WARNING:Xst:1336 -  (*) More than 100% of Device resources are used
 
---------------------------
Partition Resource Summary:
---------------------------
 
  No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+----------------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                                | Load  |
-----------------------------------+----------------------------------------------------------------------+-------+
N0                                 | NONE(mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0)| 30    |
-----------------------------------+----------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
 
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
 
Timing Summary:
---------------
Speed Grade: -4
 
   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 12.611ns
   Maximum combinational path delay: No path found
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'N0'
  Total number of paths / destination ports: 336 / 8
-------------------------------------------------------------------------
Offset:              12.611ns (Levels of Logic = 7)
  Source:            mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      N0 rising
 
  Data Path: mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             81   0.720   2.473  U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<0>)
     LUT3:I0->O            1   0.551   0.000  U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_8 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_8)
     MUXF5:I1->O           1   0.360   0.000  U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_7_f5 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_7_f5)
     MUXF6:I1->O           1   0.342   0.000  U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_6_f6 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_6_f6)
     MUXF7:I1->O           1   0.342   0.827  U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_5_f7 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_5_f7)
     LUT4:I3->O            1   0.551   0.801  U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<4> (douta(10))
     end scope: 'BU2'
     end scope: 'mem1'
     OBUF:I->O                 5.644          dataout_2_OBUF (dataout<2>)
    ----------------------------------------
    Total                     12.611ns (8.510ns logic, 4.101ns route)
                                       (67.5% logic, 32.5% route)
 
=========================================================================
 
 
Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 13.72 secs
 
-->
 
Total memory usage is 130992 kilobytes
 
Number of errors   :    0 (   0 filtered)
Number of warnings :   26 (   0 filtered)
Number of infos    :    1 (   0 filtered)
 

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Subversion Repositories bu_pacman

[/] [bu_pacman/] [tags/] [arelease/] [test_memory.syr] - Blame information for rev 6

Line No.	Rev	Author	Line
1	3	soloist_hu	`Release 10.1 - xst K.31 (nt)`
2			`Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.`
3			`--> Parameter TMPDIR set to X:/Display_Controller/xst/projnav.tmp`
4
5
6			`Total REAL time to Xst completion: 1.00 secs`
7			`Total CPU time to Xst completion: 0.16 secs`
8
9			`--> Parameter xsthdpdir set to X:/Display_Controller/xst`
10
11
12			`Total REAL time to Xst completion: 1.00 secs`
13			`Total CPU time to Xst completion: 0.16 secs`
14
15			`--> Reading design: test_memory.prj`
16
17			`TABLE OF CONTENTS`
18			`1) Synthesis Options Summary`
19			`2) HDL Compilation`
20			`3) Design Hierarchy Analysis`
21			`4) HDL Analysis`
22			`5) HDL Synthesis`
23			`5.1) HDL Synthesis Report`
24			`6) Advanced HDL Synthesis`
25			`6.1) Advanced HDL Synthesis Report`
26			`7) Low Level Synthesis`
27			`8) Partition Report`
28			`9) Final Report`
29			`9.1) Device utilization summary`
30			`9.2) Partition Resource Summary`
31			`9.3) TIMING REPORT`
32
33
34			`=========================================================================`
35			`* Synthesis Options Summary *`
36			`=========================================================================`
37			`---- Source Parameters`
38			`Input File Name : "test_memory.prj"`
39			`Input Format : mixed`
40			`Ignore Synthesis Constraint File : NO`
41
42			`---- Target Parameters`
43			`Output File Name : "test_memory"`
44			`Output Format : NGC`
45			`Target Device : xc3s200-4-ft256`
46
47			`---- Source Options`
48			`Top Module Name : test_memory`
49			`Automatic FSM Extraction : YES`
50			`FSM Encoding Algorithm : Auto`
51			`Safe Implementation : No`
52			`FSM Style : lut`
53			`RAM Extraction : Yes`
54			`RAM Style : Auto`
55			`ROM Extraction : Yes`
56			`Mux Style : Auto`
57			`Decoder Extraction : YES`
58			`Priority Encoder Extraction : YES`
59			`Shift Register Extraction : YES`
60			`Logical Shifter Extraction : YES`
61			`XOR Collapsing : YES`
62			`ROM Style : Auto`
63			`Mux Extraction : YES`
64			`Resource Sharing : YES`
65			`Asynchronous To Synchronous : NO`
66			`Multiplier Style : auto`
67			`Automatic Register Balancing : No`
68
69			`---- Target Options`
70			`Add IO Buffers : YES`
71			`Global Maximum Fanout : 500`
72			`Add Generic Clock Buffer(BUFG) : 8`
73			`Register Duplication : YES`
74			`Slice Packing : YES`
75			`Optimize Instantiated Primitives : NO`
76			`Use Clock Enable : Yes`
77			`Use Synchronous Set : Yes`
78			`Use Synchronous Reset : Yes`
79			`Pack IO Registers into IOBs : auto`
80			`Equivalent register Removal : YES`
81
82			`---- General Options`
83			`Optimization Goal : Speed`
84			`Optimization Effort : 1`
85			`Library Search Order : test_memory.lso`
86			`Keep Hierarchy : NO`
87			`Netlist Hierarchy : as_optimized`
88			`RTL Output : Yes`
89			`Global Optimization : AllClockNets`
90			`Read Cores : YES`
91			`Write Timing Constraints : NO`
92			`Cross Clock Analysis : NO`
93			`Hierarchy Separator : /`
94			`Bus Delimiter : <>`
95			`Case Specifier : maintain`
96			`Slice Utilization Ratio : 100`
97			`BRAM Utilization Ratio : 100`
98			`Verilog 2001 : YES`
99			`Auto BRAM Packing : NO`
100			`Slice Utilization Ratio Delta : 5`
101
102			`=========================================================================`
103
104
105			`=========================================================================`
106			`* HDL Compilation *`
107			`=========================================================================`
108			`Compiling verilog file "generate_add.v" in library work`
109			`Compiling verilog file "clock_divider.v" in library work`
110			`Module compiled`
111			`Compiling verilog file "blk_mem_gen_v2_7.v" in library work`
112			`Module compiled`
113			`Compiling verilog file "test_memory.v" in library work`
114			`Module compiled`
115			`Module compiled`
116			`No errors in compilation`
117			`Analysis of file <"test_memory.prj"> succeeded.`
118
119
120			`=========================================================================`
121			`* Design Hierarchy Analysis *`
122			`=========================================================================`
123			`Analyzing hierarchy for module in library .`
124
125			`Analyzing hierarchy for module in library with parameters.`
126			`NBIT = "00000000000000000000000000010110"`
127			`NDIV = "00000010111110101111000010000000"`
128
129			`Analyzing hierarchy for module in library .`
130
131
132			`=========================================================================`
133			`* HDL Analysis *`
134			`=========================================================================`
135			`Analyzing top module .`
136			`WARNING:Xst:2211 - "blk_mem_gen_v2_7.v" line 33: Instantiating black box module .`
137			`Module is correct for synthesis.`
138
139			`Analyzing module in library .`
140			`NBIT = 32'sb00000000000000000000000000010110`
141			`NDIV = 32'sb00000010111110101111000010000000`
142			`Module is correct for synthesis.`
143
144			`Analyzing module in library .`
145			`Module is correct for synthesis.`
146
147
148			`=========================================================================`
149			`* HDL Synthesis *`
150			`=========================================================================`
151
152			`Performing bidirectional port resolution...`
153
154			`Synthesizing Unit .`
155			`Related source file is "clock_divider.v".`
156			`Found 22-bit up counter for signal .`
157			`Summary:`
158			`inferred 1 Counter(s).`
159			`Unit synthesized.`
160
161
162			`Synthesizing Unit .`
163			`Related source file is "generate_add.v".`
164			`Found 16-bit up counter for signal .`
165			`Summary:`
166			`inferred 1 Counter(s).`
167			`Unit synthesized.`
168
169
170			`Synthesizing Unit .`
171			`Related source file is "test_memory.v".`
172			`WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.`
173			`WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.`
174			`Unit synthesized.`
175
176
177			`=========================================================================`
178			`HDL Synthesis Report`
179
180			`Macro Statistics`
181			`# Counters : 1`
182			`16-bit up counter : 1`
183
184			`=========================================================================`
185
186			`=========================================================================`
187			`* Advanced HDL Synthesis *`
188			`=========================================================================`
189
190			`Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx\10.1\ISE.`
191			`Reading core .`
192			`Loading core for timing and area information for instance .`
193
194			`=========================================================================`
195			`Advanced HDL Synthesis Report`
196
197			`Macro Statistics`
198			`# Counters : 1`
199			`16-bit up counter : 1`
200
201			`=========================================================================`
202
203			`=========================================================================`
204			`* Low Level Synthesis *`
205			`=========================================================================`
206			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
207			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
208			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
209			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
210			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
211			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
212			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
213			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
214			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
215			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
216			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
217			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
218			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
219			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
220			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
221			`WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.`
222
223			`Optimizing unit ...`
224
225			`Mapping all equations...`
226			`Building and optimizing final netlist ...`
227			`Found area constraint ratio of 100 (+ 5) on block test_memory, actual ratio is 7.`
228
229			`Final Macro Processing ...`
230
231			`=========================================================================`
232			`Final Register Report`
233
234			`Found no macro`
235			`=========================================================================`
236
237			`=========================================================================`
238			`* Partition Report *`
239			`=========================================================================`
240
241			`Partition Implementation Status`
242			`-------------------------------`
243
244			`No Partitions were found in this design.`
245
246			`-------------------------------`
247
248			`=========================================================================`
249			`* Final Report *`
250			`=========================================================================`
251			`Final Results`
252			`RTL Top Level Output File Name : test_memory.ngr`
253			`Top Level Output File Name : test_memory`
254			`Output Format : NGC`
255			`Optimization Goal : Speed`
256			`Keep Hierarchy : NO`
257
258			`Design Statistics`
259			`# IOs : 10`
260
261			`Cell Usage :`
262			`# BELS : 439`
263			`# GND : 2`
264			`# LUT3 : 214`
265			`# LUT4 : 64`
266			`# MUXF5 : 104`
267			`# MUXF6 : 36`
268			`# MUXF7 : 18`
269			`# VCC : 1`
270			`# FlipFlops/Latches : 10`
271			`# FDE : 10`
272			`# RAMS : 38`
273			`# RAMB16_S1_S1 : 15`
274			`# RAMB16_S2_S2 : 3`
275			`# RAMB16_S9_S9 : 20`
276			`# IO Buffers : 8`
277			`# OBUF : 8`
278			`=========================================================================`
279
280			`Device utilization summary:`
281			`---------------------------`
282
283			`Selected Device : 3s200ft256-4`
284
285			`Number of Slices: 144 out of 1920 7%`
286			`Number of Slice Flip Flops: 10 out of 3840 0%`
287			`Number of 4 input LUTs: 278 out of 3840 7%`
288			`Number of IOs: 10`
289			`Number of bonded IOBs: 8 out of 173 4%`
290			`Number of BRAMs: 38 out of 12 316% (*)`
291
292			`WARNING:Xst:1336 - (*) More than 100% of Device resources are used`
293
294			`---------------------------`
295			`Partition Resource Summary:`
296			`---------------------------`
297
298			`No Partitions were found in this design.`
299
300			`---------------------------`
301
302
303			`=========================================================================`
304			`TIMING REPORT`
305
306			`NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.`
307			`FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT`
308			`GENERATED AFTER PLACE-and-ROUTE.`
309
310			`Clock Information:`
311			`------------------`
312			`-----------------------------------+----------------------------------------------------------------------+-------+`
313			`Clock Signal \| Clock buffer(FF name) \| Load \|`
314			`-----------------------------------+----------------------------------------------------------------------+-------+`
315			`N0 \| NONE(mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0)\| 30 \|`
316			`-----------------------------------+----------------------------------------------------------------------+-------+`
317			`INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.`
318
319			`Asynchronous Control Signals Information:`
320			`----------------------------------------`
321			`No asynchronous control signals found in this design`
322
323			`Timing Summary:`
324			`---------------`
325			`Speed Grade: -4`
326
327			`Minimum period: No path found`
328			`Minimum input arrival time before clock: No path found`
329			`Maximum output required time after clock: 12.611ns`
330			`Maximum combinational path delay: No path found`
331
332			`Timing Detail:`
333			`--------------`
334			`All values displayed in nanoseconds (ns)`
335
336			`=========================================================================`
337			`Timing constraint: Default OFFSET OUT AFTER for Clock 'N0'`
338			`Total number of paths / destination ports: 336 / 8`
339			`-------------------------------------------------------------------------`
340			`Offset: 12.611ns (Levels of Logic = 7)`
341			`Source: mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 (FF)`
342			`Destination: dataout<7> (PAD)`
343			`Source Clock: N0 rising`
344
345			`Data Path: mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 to dataout<7>`
346			`Gate Net`
347			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
348			`---------------------------------------- ------------`
349			`FDE:C->Q 81 0.720 2.473 U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<0>)`
350			`LUT3:I0->O 1 0.551 0.000 U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_8 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_8)`
351			`MUXF5:I1->O 1 0.360 0.000 U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_7_f5 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_7_f5)`
352			`MUXF6:I1->O 1 0.342 0.000 U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_6_f6 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_6_f6)`
353			`MUXF7:I1->O 1 0.342 0.827 U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_5_f7 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_5_f7)`
354			`LUT4:I3->O 1 0.551 0.801 U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<4> (douta(10))`
355			`end scope: 'BU2'`
356			`end scope: 'mem1'`
357			`OBUF:I->O 5.644 dataout_2_OBUF (dataout<2>)`
358			`----------------------------------------`
359			`Total 12.611ns (8.510ns logic, 4.101ns route)`
360			`(67.5% logic, 32.5% route)`
361
362			`=========================================================================`
363
364
365			`Total REAL time to Xst completion: 14.00 secs`
366			`Total CPU time to Xst completion: 13.72 secs`
367
368			`-->`
369
370			`Total memory usage is 130992 kilobytes`
371
372			`Number of errors : 0 ( 0 filtered)`
373			`Number of warnings : 26 ( 0 filtered)`
374			`Number of infos : 1 ( 0 filtered)`
375