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soloist_hu |
Release 10.1 - xst K.31 (nt)
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Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to X:/Display_Controller/xst/projnav.tmp
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.16 secs
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--> Parameter xsthdpdir set to X:/Display_Controller/xst
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.16 secs
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--> Reading design: test_memory.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "test_memory.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "test_memory"
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Output Format : NGC
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Target Device : xc3s200-4-ft256
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---- Source Options
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Top Module Name : test_memory
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Library Search Order : test_memory.lso
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Keep Hierarchy : NO
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Netlist Hierarchy : as_optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "generate_add.v" in library work
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Compiling verilog file "clock_divider.v" in library work
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Module compiled
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Compiling verilog file "blk_mem_gen_v2_7.v" in library work
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Module compiled
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Compiling verilog file "test_memory.v" in library work
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Module compiled
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Module compiled
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No errors in compilation
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Analysis of file <"test_memory.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library with parameters.
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NBIT = "00000000000000000000000000010110"
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NDIV = "00000010111110101111000010000000"
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Analyzing hierarchy for module in library .
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module .
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WARNING:Xst:2211 - "blk_mem_gen_v2_7.v" line 33: Instantiating black box module .
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Module is correct for synthesis.
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Analyzing module in library .
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NBIT = 32'sb00000000000000000000000000010110
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NDIV = 32'sb00000010111110101111000010000000
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "clock_divider.v".
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Found 22-bit up counter for signal .
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Summary:
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inferred 1 Counter(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "generate_add.v".
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Found 16-bit up counter for signal .
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Summary:
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inferred 1 Counter(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "test_memory.v".
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WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Unit synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Counters : 1
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16-bit up counter : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx\10.1\ISE.
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Reading core .
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Loading core for timing and area information for instance .
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Counters : 1
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16-bit up counter : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
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Optimizing unit ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block test_memory, actual ratio is 7.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Found no macro
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : test_memory.ngr
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Top Level Output File Name : test_memory
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : NO
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Design Statistics
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# IOs : 10
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Cell Usage :
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# BELS : 439
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# GND : 2
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# LUT3 : 214
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# LUT4 : 64
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# MUXF5 : 104
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# MUXF6 : 36
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# MUXF7 : 18
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# VCC : 1
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# FlipFlops/Latches : 10
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# FDE : 10
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# RAMS : 38
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# RAMB16_S1_S1 : 15
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# RAMB16_S2_S2 : 3
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# RAMB16_S9_S9 : 20
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# IO Buffers : 8
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# OBUF : 8
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : 3s200ft256-4
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Number of Slices: 144 out of 1920 7%
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Number of Slice Flip Flops: 10 out of 3840 0%
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Number of 4 input LUTs: 278 out of 3840 7%
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Number of IOs: 10
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Number of bonded IOBs: 8 out of 173 4%
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Number of BRAMs: 38 out of 12 316% (*)
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WARNING:Xst:1336 - (*) More than 100% of Device resources are used
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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-----------------------------------+----------------------------------------------------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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-----------------------------------+----------------------------------------------------------------------+-------+
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N0 | NONE(mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0)| 30 |
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-----------------------------------+----------------------------------------------------------------------+-------+
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INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
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Asynchronous Control Signals Information:
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----------------------------------------
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No asynchronous control signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -4
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Minimum period: No path found
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Minimum input arrival time before clock: No path found
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Maximum output required time after clock: 12.611ns
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Maximum combinational path delay: No path found
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default OFFSET OUT AFTER for Clock 'N0'
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Total number of paths / destination ports: 336 / 8
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-------------------------------------------------------------------------
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Offset: 12.611ns (Levels of Logic = 7)
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Source: mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 (FF)
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Destination: dataout<7> (PAD)
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Source Clock: N0 rising
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Data Path: mem1/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 to dataout<7>
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDE:C->Q 81 0.720 2.473 U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<0>)
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LUT3:I0->O 1 0.551 0.000 U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_8 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_8)
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MUXF5:I1->O 1 0.360 0.000 U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_7_f5 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_7_f5)
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MUXF6:I1->O 1 0.342 0.000 U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_6_f6 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_6_f6)
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MUXF7:I1->O 1 0.342 0.827 U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_5_f7 (U0/blk_mem_generator/valid.cstr/has_mux_a.A/Mmux_dout_mux_5_f7)
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|
LUT4:I3->O 1 0.551 0.801 U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<4> (douta(10))
|
355 |
|
|
end scope: 'BU2'
|
356 |
|
|
end scope: 'mem1'
|
357 |
|
|
OBUF:I->O 5.644 dataout_2_OBUF (dataout<2>)
|
358 |
|
|
----------------------------------------
|
359 |
|
|
Total 12.611ns (8.510ns logic, 4.101ns route)
|
360 |
|
|
(67.5% logic, 32.5% route)
|
361 |
|
|
|
362 |
|
|
=========================================================================
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
Total REAL time to Xst completion: 14.00 secs
|
366 |
|
|
Total CPU time to Xst completion: 13.72 secs
|
367 |
|
|
|
368 |
|
|
-->
|
369 |
|
|
|
370 |
|
|
Total memory usage is 130992 kilobytes
|
371 |
|
|
|
372 |
|
|
Number of errors : 0 ( 0 filtered)
|
373 |
|
|
Number of warnings : 26 ( 0 filtered)
|
374 |
|
|
Number of infos : 1 ( 0 filtered)
|
375 |
|
|
|