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soloist_hu |
Release 10.1 Map K.31 (nt)
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Xilinx Map Application Log File for Design 'test_memory'
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Design Information
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------------------
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Command Line : map -ise X:/Display_Controller/Display_Controller.ise -intstyle
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ise -p xc3s200-ft256-4 -cm area -pr off -k 4 -c 100 -o test_memory_map.ncd
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test_memory.ngd test_memory.pcf
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Target Device : xc3s200
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Target Package : ft256
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Target Speed : -4
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Mapper Version : spartan3 -- $Revision: 1.1.1.1 $
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Mapped Date : Thu Nov 20 21:07:08 2008
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Mapping design into LUTs...
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Running directed packing...
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Running delay-based LUT packing...
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Running related packing...
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Design Summary
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--------------
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Design Summary:
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Number of errors: 0
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Number of warnings: 4
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Logic Utilization:
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Logic Distribution:
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Number of Slices containing only related logic: 0 out of 0 0%
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Number of Slices containing unrelated logic: 0 out of 0 0%
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*See NOTES below for an explanation of the effects of unrelated logic.
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Number of bonded IOBs: 10 out of 173 5%
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Number of RAMB16s: 1 out of 12 8%
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Peak Memory Usage: 125 MB
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Total REAL time to MAP completion: 7 secs
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Total CPU time to MAP completion: 1 secs
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NOTES:
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Related logic is defined as being logic that shares connectivity - e.g. two
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LUTs are "related" if they share common inputs. When assembling slices,
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Map gives priority to combine logic that is related. Doing so results in
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the best timing performance.
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Unrelated logic shares no connectivity. Map will only begin packing
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unrelated logic into a slice once 99% of the slices are occupied through
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related logic packing.
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Note that once logic distribution reaches the 99% level through related
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logic packing, this does not mean the device is completely utilized.
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Unrelated logic packing will then begin, continuing until all usable LUTs
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and FFs are occupied. Depending on your timing budget, increased levels of
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unrelated logic packing may adversely affect the overall timing performance
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of your design.
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Mapping completed.
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See MAP report file "test_memory_map.mrp" for details.
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