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[/] [bubblesortmodule/] [trunk/] [rtl/] [verilog/] [rungenerator.v] - Blame information for rev 4

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1 4 avramionut
//////////////////////////////////////////////////////////////////////
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////
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//// Copyright (C) 2014 avram ionut, avramionut@opencores.org
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////
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//// This source file may be used and distributed without
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//// restriction provided that this copyright statement is not
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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////
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//// This source file is free software; you can redistribute it
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//// and/or modify it under the terms of the GNU Lesser General
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//// Public License as published by the Free Software Foundation;
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//// either version 2.1 of the License, or (at your option) any
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//// later version.
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////
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//// This source is distributed in the hope that it will be
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// details.
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////
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//// You should have received a copy of the GNU Lesser General
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//// Public License along with this source; if not, download it
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//// from http://www.opencores.org/lgpl.shtml
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////
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//
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// Revisions: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//                     
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//
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//////////////////////////////////////////////////////////////////////////////////
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module rungenerator #(parameter N_BITS=8)
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    (
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    input   clk,
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    input   rst,
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    input   start_i,
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    input   all_sorted_i,
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    output  run_o
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    );
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    reg [N_BITS+4-1:0]  r_count;
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    reg     r_job_done;
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    wire    w_ready_to_stop;
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    wire    w_next_bit;
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    always @(posedge clk)
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        begin
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            if (rst) begin
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                r_count <= {{N_BITS{1'd0}},4'b0000};             end
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            else if(start_i) begin
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                r_count <= {{N_BITS{1'd1}},4'b0000};             end
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            else  begin
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                r_count <= {r_count[N_BITS+4-2:0],w_next_bit};   end
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        end
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    always @(posedge clk)
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        begin
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            if (rst) begin
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                r_job_done <= 1'b1;          end
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            else if (all_sorted_i) begin
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                r_job_done <= 1'b1;          end
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            else if (start_i) begin
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                r_job_done <= 1'b0;          end
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        end
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    assign w_ready_to_stop = ~r_count[0];
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    assign w_next_bit = (r_job_done & w_ready_to_stop) ? 1'b0 : r_count[N_BITS+4-1];
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    assign run_o = r_count[0];
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endmodule

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