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[/] [bustap-jtag/] [tags/] [v1p0/] [rtl/] [up_monitor.vhd] - Blame information for rev 22

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Line No. Rev Author Line
1 2 ash_riple 
library ieee;
2 
use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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6 
entity up_monitor is
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port (
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        up_clk          : in std_logic;
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        up_wbe          : in std_logic;
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        up_csn          : in std_logic;
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        up_addr         : in std_logic_vector(15 downto 2);
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        up_data_io              : in std_logic_vector(31 downto 0)
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);
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end up_monitor;
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architecture synth of up_monitor is
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component virtual_jtag_adda_fifo is
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        generic(
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                data_width      : integer;
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                fifo_depth      : integer;
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                addr_width      : integer;
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                al_full_val     : integer;
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                al_empt_val     : integer
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        );
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        port(
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                clk             : in std_logic;
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                wr_en   : in std_logic;
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                data_in : in std_logic_vector(data_width-1 downto 0)
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        );
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end component virtual_jtag_adda_fifo;
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signal up_csn_d1, up_csn_d2, up_csn_d3, up_csn_d4       : std_logic;
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signal up_csn_neg_pulse         : std_logic;
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signal up_bus_content           : std_logic_vector(47 downto 0);
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type addr_array is array (15 downto 0) of std_logic_vector (31 downto 0);
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component virtual_jtag_addr_mask is
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        generic(
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                addr_width      : integer;
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                mask_index      : integer;
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                mask_num        : integer
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        );
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        port(
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                mask_out0       : out std_logic_vector (31 downto 0);
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                mask_out1       : out std_logic_vector (31 downto 0);
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                mask_out2       : out std_logic_vector (31 downto 0);
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                mask_out3       : out std_logic_vector (31 downto 0);
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                mask_out4       : out std_logic_vector (31 downto 0);
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                mask_out5       : out std_logic_vector (31 downto 0);
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                mask_out6       : out std_logic_vector (31 downto 0);
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                mask_out7       : out std_logic_vector (31 downto 0);
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                mask_out8       : out std_logic_vector (31 downto 0);
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                mask_out9       : out std_logic_vector (31 downto 0);
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                mask_out10      : out std_logic_vector (31 downto 0);
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                mask_out11      : out std_logic_vector (31 downto 0);
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                mask_out12      : out std_logic_vector (31 downto 0);
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                mask_out13      : out std_logic_vector (31 downto 0);
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                mask_out14      : out std_logic_vector (31 downto 0);
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                mask_out15      : out std_logic_vector (31 downto 0)
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        );
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end component virtual_jtag_addr_mask;
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signal addr_mask : addr_array;
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signal addr_mask_ok : std_logic;
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component virtual_jtag_adda_trig is
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        generic(
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                trig_width      : integer
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        );
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        port(
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                trig_out        : out std_logic_vector(trig_width-1 downto 0)
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        );
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end component virtual_jtag_adda_trig;
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signal trig_condition   : std_logic_vector(49 downto 0);
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alias  trig_en          : std_logic is trig_condition(49);
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alias  trig_set         : std_logic is trig_condition(48);
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alias  trig_addr        : std_logic_vector(15 downto 0) is trig_condition(47 downto 32);
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alias  trig_data        : std_logic_vector(31 downto 0) is trig_condition(31 downto 0);
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signal trig_condition_ok : std_logic;
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84 
begin
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process (up_clk)
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begin
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        if (up_clk'event and up_clk='1') then
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                up_csn_d1 <= up_csn or up_wbe;
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                up_csn_d2 <= up_csn_d1;
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                up_csn_d3 <= up_csn_d2;
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                up_csn_d4 <= up_csn_d3;
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        end if;
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end process;
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96 
 
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process (up_clk)
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begin
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        if (up_clk'event and up_clk='1') then
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                if ((   (up_addr(15 downto 2)<=addr_mask(0)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(0)(15 downto 2)) or
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                        (up_addr(15 downto 2)<=addr_mask(1)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(1)(15 downto 2)) or
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                        (up_addr(15 downto 2)<=addr_mask(2)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(2)(15 downto 2)) or
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                        (up_addr(15 downto 2)<=addr_mask(3)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(3)(15 downto 2)) or
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                        (up_addr(15 downto 2)<=addr_mask(4)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(4)(15 downto 2)) or
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                        (up_addr(15 downto 2)<=addr_mask(5)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(5)(15 downto 2)) or
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                        (up_addr(15 downto 2)<=addr_mask(6)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(6)(15 downto 2)) or
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                        (up_addr(15 downto 2)<=addr_mask(7)(31 downto 18) and up_addr(15 downto 2)>=addr_mask(7)(15 downto 2))
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                    ) --inclusive address set
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                    and
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                    (   (up_addr(15 downto 2)>addr_mask(8) (31 downto 18) or up_addr(15 downto 2)<addr_mask(8) (15 downto 2)) and
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                        (up_addr(15 downto 2)>addr_mask(9) (31 downto 18) or up_addr(15 downto 2)<addr_mask(9) (15 downto 2)) and
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                        (up_addr(15 downto 2)>addr_mask(10)(31 downto 18) or up_addr(15 downto 2)<addr_mask(10)(15 downto 2)) and
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                        (up_addr(15 downto 2)>addr_mask(11)(31 downto 18) or up_addr(15 downto 2)<addr_mask(11)(15 downto 2)) and
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                        (up_addr(15 downto 2)>addr_mask(12)(31 downto 18) or up_addr(15 downto 2)<addr_mask(12)(15 downto 2)) and
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                        (up_addr(15 downto 2)>addr_mask(13)(31 downto 18) or up_addr(15 downto 2)<addr_mask(13)(15 downto 2)) and
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                        (up_addr(15 downto 2)>addr_mask(14)(31 downto 18) or up_addr(15 downto 2)<addr_mask(14)(15 downto 2)) and
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                        (up_addr(15 downto 2)>addr_mask(15)(31 downto 18) or up_addr(15 downto 2)<addr_mask(15)(15 downto 2))
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                    ) --exclusive address set
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                   ) then
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                        addr_mask_ok <= '1';
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                else
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                        addr_mask_ok <= '0';
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                end if;
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        end if;
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end process;
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127 
process (up_clk)
128 
begin
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        if (up_clk'event and up_clk='1') then
130 
                if (trig_en='0') then
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                        trig_condition_ok <= '1';
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                elsif (trig_set='0') then
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                        trig_condition_ok <= '0';
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                elsif (up_csn_d1='0' and up_csn_d2='1') then
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                        if (trig_addr(15 downto 2)=up_addr(15 downto 2) and trig_data=up_data_io) then
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                                trig_condition_ok <= '1';
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                        end if;
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                end if;
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        end if;
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end process;
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up_csn_neg_pulse <= (not up_csn_d3) and up_csn_d4 and addr_mask_ok and trig_condition_ok;
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up_bus_content <= up_addr(15 downto 2) & "00" & up_data_io(31 downto 0);
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u_virtual_jtag_adda_fifo : virtual_jtag_adda_fifo
146 
generic map
147 
        (
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        data_width      => 48,
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        fifo_depth      => 512,
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        addr_width      => 9,
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        al_full_val     => 511,
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        al_empt_val     => 0
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        )
154 
port map
155 
        (
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        clk             => up_clk,
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        wr_en   => up_csn_neg_pulse,
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        data_in => up_bus_content
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        );
160 
 
161 
u_virtual_jtag_addr_mask : virtual_jtag_addr_mask
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generic map
163 
        (
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        addr_width      => 32,
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        mask_index      => 4,
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        mask_num        => 16
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        )
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port map
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        (
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        mask_out0       => addr_mask(0),
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        mask_out1       => addr_mask(1),
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        mask_out2       => addr_mask(2),
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        mask_out3       => addr_mask(3),
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        mask_out4       => addr_mask(4),
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        mask_out5       => addr_mask(5),
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        mask_out6       => addr_mask(6),
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        mask_out7       => addr_mask(7),
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        mask_out8       => addr_mask(8),
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        mask_out9       => addr_mask(9),
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        mask_out10      => addr_mask(10),
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        mask_out11      => addr_mask(11),
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        mask_out12      => addr_mask(12),
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        mask_out13      => addr_mask(13),
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        mask_out14      => addr_mask(14),
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        mask_out15      => addr_mask(15)
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        );
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188 
u_virtual_jtag_adda_trig : virtual_jtag_adda_trig
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generic map
190 
        (
191 
        trig_width      => 50
192 
        )
193 
port map
194 
        (
195 
        trig_out        => trig_condition
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        );
197 
 
198 
end synth;

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