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#-- DISCLAIMER OF LIABILITY
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#--
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#-- This file contains proprietary and confidential information of
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#-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
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#-- from Xilinx, and may be used, copied and/or disclosed only
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#-- pursuant to the terms of a valid license agreement with Xilinx.
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#--
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#-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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#-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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#-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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#-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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#-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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#-- does not warrant that functions included in the Materials will
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#-- meet the requirements of Licensee, or that the operation of the
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#-- Materials will be uninterrupted or error-free, or that defects
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#-- in the Materials will be corrected. Furthermore, Xilinx does
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#-- results of the use, of the Materials in terms of correctness,
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#-- accuracy, reliability or otherwise.
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#--
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#-- Xilinx products are not designed or intended to be fail-safe,
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#-- or for use in any application requiring fail-safe performance,
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#-- such as life-support or safety devices or systems, Class III
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#-- medical devices, nuclear facilities, applications related to
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#-- the deployment of airbags, or any other applications that could
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#-- lead to death, personal injury or severe property or
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#-- environmental damage (individually and collectively, "critical
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#-- applications"). Customer assumes the sole risk and liability
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#-- of any use of Xilinx products in critical applications,
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#-- subject only to applicable laws and regulations governing
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#-- limitations on product liability.
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#--
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#-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
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#--
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#-- This disclaimer and copyright notice must be retained as part
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#-- of this file at all times.
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#--
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###################################################################
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##
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## Name : bustap_jtag
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## Desc : Microprocessor Peripheral Description
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## : Automatically generated by PsfUtility
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##
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###################################################################
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BEGIN bustap_jtag
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## Peripheral Options
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OPTION IPTYPE = PERIPHERAL
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OPTION IMP_NETLIST = TRUE
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OPTION STYLE = MIX
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OPTION DESC = AXI BUS TAP
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OPTION LONG_DESC = AXI BUS TAP JTAG
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OPTION HDL = MIXED
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OPTION RUN_NGCBUILD = TRUE
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## MON_AXI Bus Interfaces
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BUS_INTERFACE BUS = MON_AXI, BUS_STD = AXI, BUS_TYPE = MONITOR
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## MON_AXI Generics for VHDL or Parameters for Verilog
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PARAMETER C_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = MON_AXI
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PARAMETER C_DATA_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = MON_AXI
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PARAMETER C_PROTOCOL = AXI4Lite, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = MON_AXI
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## MON_AXI Ports
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PORT ACLK = "", BUS = MON_AXI, DIR = I, SIGIS = CLK
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PORT ARESETN = ARESETN, BUS = MON_AXI, DIR = I, SIGIS = RST
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PORT AWADDR = AWADDR, BUS = MON_AXI, DIR = I, VEC = [(C_ADDR_WIDTH-1):0]
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PORT AWPROT = AWPROT, BUS = MON_AXI, DIR = I, VEC = [2:0]
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PORT AWVALID = AWVALID, BUS = MON_AXI, DIR = I
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PORT AWREADY = AWREADY, BUS = MON_AXI, DIR = I
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PORT WDATA = WDATA, BUS = MON_AXI, DIR = I, VEC = [(C_DATA_WIDTH-1):0]
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PORT WSTRB = WSTRB, BUS = MON_AXI, DIR = I, VEC = [((C_DATA_WIDTH/8) -1):0]
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PORT WVALID = WVALID, BUS = MON_AXI, DIR = I
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PORT WREADY = WREADY, BUS = MON_AXI, DIR = I
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PORT BRESP = BRESP, BUS = MON_AXI, DIR = I, VEC = [1:0]
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PORT BVALID = BVALID, BUS = MON_AXI, DIR = I
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PORT BREADY = BREADY, BUS = MON_AXI, DIR = I
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PORT ARADDR = ARADDR, BUS = MON_AXI, DIR = I, VEC = [(C_ADDR_WIDTH-1):0
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PORT ARPROT = ARPROT, BUS = MON_AXI, DIR = I, VEC = [2:0]
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PORT ARVALID = ARVALID, BUS = MON_AXI, DIR = I
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PORT ARREADY = ARREADY, BUS = MON_AXI, DIR = I
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PORT RDATA = RDATA, BUS = MON_AXI, DIR = I, VEC = [(C_DATA_WIDTH-1):0]
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PORT RRESP = RRESP, BUS = MON_AXI, DIR = I, VEC = [1:0]
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PORT RVALID = RVALID, BUS = MON_AXI, DIR = I
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PORT RREADY = RREADY, BUS = MON_AXI, DIR = I
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## CHIPSCOPE ICON Ports
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PORT CHIPSCOPE_ICON_CONTROL0 = "", DIR = I, VEC = [35:0], ASSIGNMENT = OPTIONAL
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PORT CHIPSCOPE_ICON_CONTROL1 = "", DIR = I, VEC = [35:0], ASSIGNMENT = OPTIONAL
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PORT CHIPSCOPE_ICON_CONTROL2 = "", DIR = I, VEC = [35:0], ASSIGNMENT = OPTIONAL
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END
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