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ash_riple |
//**************************************************************
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// Module : bustap_jtag_v1_0.v
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// Platform : Ubuntu 14.04
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// Simulator : Modelsim 6.5b
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// Synthesizer : Vivado 2014.2
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// Place and Route : Vivado 2014.2
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// Targets device : Zynq 7000
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Revision : 2.4
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// Date : 2014/09/22
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// Description : axi interface to pipelined access
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// interface converter. axi pass through
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// @Note: AXI-Lite is supported.
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//**************************************************************
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`timescale 1ns/1ns
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module bustap_jtag_v1_0 #
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(
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parameter integer C_S00_AXI_DATA_WIDTH = 32,
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parameter integer C_S00_AXI_ADDR_WIDTH = 32,
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parameter integer C_M00_AXI_DATA_WIDTH = 32,
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parameter integer C_M00_AXI_ADDR_WIDTH = 32
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)
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(
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// AXI Slave Interface
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input wire s00_axi_aclk,
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input wire s00_axi_aresetn,
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input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
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input wire [2 : 0] s00_axi_awprot,
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input wire s00_axi_awvalid,
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output wire s00_axi_awready,
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input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
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input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
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input wire s00_axi_wvalid,
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output wire s00_axi_wready,
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output wire [1 : 0] s00_axi_bresp,
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output wire s00_axi_bvalid,
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input wire s00_axi_bready,
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input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
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input wire [2 : 0] s00_axi_arprot,
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input wire s00_axi_arvalid,
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output wire s00_axi_arready,
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output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
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output wire [1 : 0] s00_axi_rresp,
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output wire s00_axi_rvalid,
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input wire s00_axi_rready,
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// AXI Master Interface
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input wire m00_axi_aclk,
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input wire m00_axi_aresetn,
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output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
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output wire [2 : 0] m00_axi_awprot,
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output wire m00_axi_awvalid,
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input wire m00_axi_awready,
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output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
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output wire [(C_M00_AXI_DATA_WIDTH/8)-1 : 0] m00_axi_wstrb,
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output wire m00_axi_wvalid,
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input wire m00_axi_wready,
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input wire [1 : 0] m00_axi_bresp,
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input wire m00_axi_bvalid,
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output wire m00_axi_bready,
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output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
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output wire [2 : 0] m00_axi_arprot,
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output wire m00_axi_arvalid,
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input wire m00_axi_arready,
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input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
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input wire [1 : 0] m00_axi_rresp,
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input wire m00_axi_rvalid,
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output wire m00_axi_rready
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);
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// Pass Through
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assign m00_axi_awaddr = s00_axi_awaddr;
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assign m00_axi_awprot = s00_axi_awprot;
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assign m00_axi_awvalid = s00_axi_awvalid;
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assign s00_axi_awready = m00_axi_awready;
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assign m00_axi_wdata = s00_axi_wdata;
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assign m00_axi_wstrb = s00_axi_wstrb;
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assign m00_axi_wvalid = s00_axi_wvalid;
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assign s00_axi_wready = m00_axi_wready;
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assign s00_axi_bresp = m00_axi_bresp;
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assign s00_axi_bvalid = m00_axi_bvalid;
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assign m00_axi_bready = s00_axi_bready;
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assign m00_axi_araddr = s00_axi_araddr;
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assign m00_axi_arprot = s00_axi_arprot;
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assign m00_axi_arvalid = s00_axi_arvalid;
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assign s00_axi_arready = m00_axi_arready;
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assign s00_axi_rdata = m00_axi_rdata;
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assign s00_axi_rresp = m00_axi_rresp;
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assign s00_axi_rvalid = m00_axi_rvalid;
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assign m00_axi_rready = s00_axi_rready;
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// latch address and data, does not support simultaneous read and write
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reg [C_S00_AXI_ADDR_WIDTH-1:0] addr_latch;
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always @(posedge s00_axi_aclk) begin
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if (s00_axi_awvalid && s00_axi_awready)
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addr_latch <= s00_axi_awaddr;
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else if (s00_axi_arvalid && s00_axi_arready)
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addr_latch <= s00_axi_araddr;
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else
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addr_latch <= addr_latch;
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end
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reg [C_S00_AXI_DATA_WIDTH-1:0] data_latch;
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always @(posedge s00_axi_aclk) begin
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if (s00_axi_wvalid && s00_axi_wready)
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data_latch <= s00_axi_wdata;
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else if (s00_axi_rvalid && s00_axi_rready)
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data_latch <= s00_axi_rdata;
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else
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data_latch <= data_latch;
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end
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// generate wr/rd pulse
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reg wr_pulse;
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always @(posedge s00_axi_aclk or negedge s00_axi_aresetn) begin
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if (!s00_axi_aresetn)
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wr_pulse <= 1'b0;
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else if (s00_axi_wvalid && s00_axi_wready)
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wr_pulse <= 1'b1;
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else
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wr_pulse <= 1'b0;
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end
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reg rd_pulse;
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always @(posedge s00_axi_aclk or negedge s00_axi_aresetn) begin
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if (!s00_axi_aresetn)
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rd_pulse <= 1'b0;
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else if (s00_axi_rvalid && s00_axi_rready)
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rd_pulse <= 1'b1;
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else
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rd_pulse <= 1'b0;
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end
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// map to pipelined access interface
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wire clk = s00_axi_aclk;
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wire wr_en = wr_pulse;
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wire rd_en = rd_pulse;
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wire [31:0] addr_in = addr_latch[31:0];
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wire [31:0] data_in = data_latch;
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up_monitor inst (
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.clk(clk),
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.wr_en(wr_en),
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.rd_en(rd_en),
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.addr_in(addr_in),
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.data_in(data_in)
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);
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endmodule
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