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// Copyright (C) 1991-2011 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// Quartus II 10.1 Build 197 11/29/2010
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// VIRTUAL JTAG MODULE CONSTANTS
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// the default bit length for time and value
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`define DEFAULT_BIT_LENGTH 32
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// the bit length for type
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`define TYPE_BIT_LENGTH 4
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// the bit length for delay time
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`define TIME_BIT_LENGTH 64
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// the number of selection bits + width of hub instructions(3)
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`define NUM_SELECTION_BITS 4
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// the states for the parser state machine
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`define STARTSTATE 3'b000
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`define LENGTHSTATE 3'b001
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`define VALUESTATE 3'b011
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`define TYPESTATE 3'b111
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`define TIMESTATE 3'b101
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`define V_DR_SCAN_TYPE 4'b0010
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`define V_IR_SCAN_TYPE 4'b0001
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// specify time scale, allowing JTAG to run at 1GHz against actual 10MHz
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`define CLK_PERIOD 1000
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`define DELAY_RESOLUTION 100
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// the states for the tap controller state machine
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`define TLR_ST 5'b00000
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`define RTI_ST 5'b00001
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`define DRS_ST 5'b00011
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`define CDR_ST 5'b00111
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`define SDR_ST 5'b01111
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`define E1DR_ST 5'b01011
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`define PDR_ST 5'b01101
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`define E2DR_ST 5'b01000
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`define UDR_ST 5'b01001
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`define IRS_ST 5'b01100
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`define CIR_ST 5'b01010
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`define SIR_ST 5'b00101
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`define E1IR_ST 5'b00100
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`define PIR_ST 5'b00010
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`define E2IR_ST 5'b00110
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`define UIR_ST 5'b01110
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`define INIT_ST 5'b10000
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// usr1 instruction for tap controller
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`define JTAG_USR1_INSTR 10'b0000001110
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//START_MODULE_NAME------------------------------------------------------------
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// Module Name : signal_gen
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//
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// Description : Simulates customizable actions on a JTAG input
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//
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// Limitation : Zero is not a valid length and causes simulation to halt with
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// an error message.
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// Values with more bits than specified length will be truncated.
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// Length for IR scans are ignored. They however should be factored in when
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// calculating SLD_NODE_TOTAl_LENGTH.
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//
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// Results expected :
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//
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//
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//END_MODULE_NAME--------------------------------------------------------------
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// BEGINNING OF MODULE
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`timescale 1 ps / 1 ps
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// MODULE DECLARATION
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module signal_gen (tck,tms,tdi,jtag_usr1,tdo);
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// GLOBAL PARAMETER DECLARATION
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parameter sld_node_ir_width = 1;
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parameter sld_node_n_scan = 0;
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parameter sld_node_total_length = 0;
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parameter sld_node_sim_action = "()";
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// INPUT PORTS
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input jtag_usr1;
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input tdo;
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// OUTPUT PORTS
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output tck;
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output tms;
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output tdi;
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// CONSTANT DECLARATIONS
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`define DECODED_SCANS_LENGTH (sld_node_total_length + ((sld_node_n_scan * `DEFAULT_BIT_LENGTH) * 2) + (sld_node_n_scan * `TYPE_BIT_LENGTH) - 1)
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`define DEFAULT_SCAN_LENGTH (sld_node_n_scan * `DEFAULT_BIT_LENGTH)
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`define TYPE_SCAN_LENGTH (sld_node_n_scan * `TYPE_BIT_LENGTH) - 1
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// INTEGER DECLARATION
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integer char_idx; // character_loop index
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integer value_idx; // decoding value index
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integer value_idx_old; // previous decoding value index
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integer value_idx_cur; // reading/outputing value index
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integer length_idx; // decoding length index
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integer length_idx_old; // previous decoding length index
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integer length_idx_cur; // reading/outputing length index
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integer last_length_idx;// decoding previous length index
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integer type_idx; // decoding type index
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integer type_idx_old; // previous decoding type index
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integer type_idx_cur; // reading/outputing type index
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integer time_idx; // decoding time index
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integer time_idx_old; // previous decoding time index
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integer time_idx_cur; // reading/outputing time index
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// REGISTERS
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reg [ `DEFAULT_SCAN_LENGTH - 1 : 0 ] scan_length;
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// register for the 32-bit length values
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reg [ sld_node_total_length - 1 : 0 ] scan_values;
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// register for values
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reg [ `TYPE_SCAN_LENGTH : 0 ] scan_type;
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// register for 4-bit type
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reg [ `DEFAULT_SCAN_LENGTH - 1 : 0 ] scan_time;
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// register to hold time values
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reg [15 : 0] two_character;
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// two ascii characters. Used in decoding
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reg [2 : 0] c_state;
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// the current state register
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reg [3 : 0] hex_value;
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// temporary value to hold hex value of ascii character
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reg [31 : 0] last_length;
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// register to hold the previous length value read
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reg tms_reg;
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// register to hold tms value before its clocked
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reg tdi_reg;
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// register to hold tdi vale before its clocked
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// OUTPUT REGISTERS
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reg tms;
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reg tck;
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reg tdi;
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// input registers
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// LOCAL TIME DECLARATION
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// FUNCTION DECLARATION
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// hexToBits - takes in a hexadecimal character and
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// returns the 4-bit value of the character.
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// Returns 0 if character is not a hexadeciaml character
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function [3 : 0] hexToBits;
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input [7 : 0] character;
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begin
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case ( character )
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"0" : hexToBits = 4'b0000;
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"1" : hexToBits = 4'b0001;
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"2" : hexToBits = 4'b0010;
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"3" : hexToBits = 4'b0011;
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"4" : hexToBits = 4'b0100;
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"5" : hexToBits = 4'b0101;
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"6" : hexToBits = 4'b0110;
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"7" : hexToBits = 4'b0111;
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"8" : hexToBits = 4'b1000;
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"9" : hexToBits = 4'b1001;
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"A" : hexToBits = 4'b1010;
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"a" : hexToBits = 4'b1010;
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"B" : hexToBits = 4'b1011;
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"b" : hexToBits = 4'b1011;
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"C" : hexToBits = 4'b1100;
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"c" : hexToBits = 4'b1100;
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"D" : hexToBits = 4'b1101;
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"d" : hexToBits = 4'b1101;
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"E" : hexToBits = 4'b1110;
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"e" : hexToBits = 4'b1110;
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"F" : hexToBits = 4'b1111;
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"f" : hexToBits = 4'b1111;
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default :
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begin
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hexToBits = 4'b0000;
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$display("%s is not a hexadecimal value",character);
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end
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endcase
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end
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endfunction
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// TASK DECLARATIONS
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// clocks tck
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task clock_tck;
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input in_tms;
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input in_tdi;
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begin : clock_tck_tsk
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#(`CLK_PERIOD/2) tck <= ~tck;
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tms <= in_tms;
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tdi <= in_tdi;
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#(`CLK_PERIOD/2) tck <= ~tck;
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end // clock_tck_tsk
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endtask // clock_tck
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// move tap controller from dr/ir shift state to ir/dr update state
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task goto_update_state;
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begin : goto_update_state_tsk
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// get into e1(i/d)r state
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tms_reg = 1'b1;
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clock_tck(tms_reg,tdi_reg);
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// get into u(i/d)r state
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tms_reg = 1'b1;
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clock_tck(tms_reg,tdi_reg);
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end // goto_update_state_tsk
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endtask // goto_update_state
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// resets the jtag TAP controller by holding tms high
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// for 6 tck cycles
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task reset_jtag;
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integer idx;
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begin
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for (idx = 0; idx < 6; idx= idx + 1)
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begin
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tms_reg = 1'b1;
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clock_tck(tms_reg,tdi_reg);
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end
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// get into rti state
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
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jtag_ir_usr1;
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end
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endtask // reset_jtag
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// sends a jtag_usr0 intsruction
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task jtag_ir_usr0;
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integer i;
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begin : jtag_ir_usr0_tsk
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// get into drs state
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tms_reg = 1'b1;
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clock_tck(tms_reg,tdi_reg);
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// get into irs state
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tms_reg = 1'b1;
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clock_tck(tms_reg,tdi_reg);
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// get into cir state
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
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// get into sir state
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
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// shift in data i.e usr0 instruction
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// usr1 = 0x0E = 0b00 0000 1100
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for ( i = 0; i < 2; i = i + 1)
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begin :ir_usr0_loop1
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tdi_reg = 1'b0;
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
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end // ir_usr0_loop1
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for ( i = 0; i < 2; i = i + 1)
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begin :ir_usr0_loop2
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tdi_reg = 1'b1;
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
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end // ir_usr0_loop2
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// done with 1100
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for ( i = 0; i < 6; i = i + 1)
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begin :ir_usr0_loop3
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tdi_reg = 1'b0;
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
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end // ir_usr0_loop3
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// done with 00 0000
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// get into e1ir state
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tms_reg = 1'b1;
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clock_tck(tms_reg,tdi_reg);
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// get into uir state
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tms_reg = 1'b1;
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clock_tck(tms_reg,tdi_reg);
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end // jtag_ir_usr0_tsk
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endtask // jtag_ir_usr0
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// sends a jtag_usr1 intsruction
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task jtag_ir_usr1;
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integer i;
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begin : jtag_ir_usr1_tsk
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// get into drs state
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tms_reg = 1'b1;
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clock_tck(tms_reg,tdi_reg);
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// get into irs state
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tms_reg = 1'b1;
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clock_tck(tms_reg,tdi_reg);
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// get into cir state
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
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// get into sir state
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
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// shift in data i.e usr1 instruction
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// usr1 = 0x0E = 0b00 0000 1110
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tdi_reg = 1'b0;
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
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for ( i = 0; i < 3; i = i + 1)
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begin :ir_usr1_loop1
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tdi_reg = 1'b1;
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
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end // ir_usr1_loop1
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// done with 1110
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for ( i = 0; i < 5; i = i + 1)
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begin :ir_usr1_loop2
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tdi_reg = 1'b0;
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
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end // ir_sur1_loop2
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tdi_reg = 1'b0;
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tms_reg = 1'b1;
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clock_tck(tms_reg,tdi_reg);
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// done with 00 0000
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// now in e1ir state
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// get into uir state
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tms_reg = 1'b1;
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clock_tck(tms_reg,tdi_reg);
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end // jtag_ir_usr1_tsk
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endtask // jtag_ir_usr1
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// sends a force_ir_capture instruction to the node
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task send_force_ir_capture;
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integer i;
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begin : send_force_ir_capture_tsk
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goto_dr_shift_state;
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// start shifting in the instruction
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tdi_reg = 1'b1;
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tms_reg = 1'b0;
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clock_tck(tms_reg,tdi_reg);
|
343 |
|
|
tdi_reg = 1'b1;
|
344 |
|
|
tms_reg = 1'b0;
|
345 |
|
|
clock_tck(tms_reg,tdi_reg);
|
346 |
|
|
tdi_reg = 1'b0;
|
347 |
|
|
tms_reg = 1'b0;
|
348 |
|
|
clock_tck(tms_reg,tdi_reg);
|
349 |
|
|
// done with 011
|
350 |
|
|
tdi_reg = 1'b0;
|
351 |
|
|
tms_reg = 1'b0;
|
352 |
|
|
clock_tck(tms_reg,tdi_reg);
|
353 |
|
|
// done with select bit
|
354 |
|
|
// fill up with zeros up to ir_width
|
355 |
|
|
for ( i = 0; i < sld_node_ir_width - 4; i = i + 1 )
|
356 |
|
|
begin
|
357 |
|
|
tdi_reg = 1'b0;
|
358 |
|
|
tms_reg = 1'b0;
|
359 |
|
|
clock_tck(tms_reg,tdi_reg);
|
360 |
|
|
end
|
361 |
|
|
goto_update_state;
|
362 |
|
|
end // send_force_ir_capture_tsk
|
363 |
|
|
endtask // send_forse_ir_capture
|
364 |
|
|
|
365 |
|
|
// puts the JTAG tap controller in DR shift state
|
366 |
|
|
task goto_dr_shift_state;
|
367 |
|
|
begin : goto_dr_shift_state_tsk
|
368 |
|
|
// get into drs state
|
369 |
|
|
tms_reg = 1'b1;
|
370 |
|
|
clock_tck(tms_reg,tdi_reg);
|
371 |
|
|
// get into cdr state
|
372 |
|
|
tms_reg = 1'b0;
|
373 |
|
|
clock_tck(tms_reg,tdi_reg);
|
374 |
|
|
// get into sdr state
|
375 |
|
|
tms_reg = 1'b0;
|
376 |
|
|
clock_tck(tms_reg,tdi_reg);
|
377 |
|
|
end // goto_dr_shift_state_tsk
|
378 |
|
|
endtask // goto_dr_shift_state
|
379 |
|
|
|
380 |
|
|
// performs a virtual_ir_scan
|
381 |
|
|
task v_ir_scan;
|
382 |
|
|
input [`DEFAULT_BIT_LENGTH - 1 : 0] length;
|
383 |
|
|
integer i;
|
384 |
|
|
begin : v_ir_scan_tsk
|
385 |
|
|
// if we are not in usr1 then go to usr1 state
|
386 |
|
|
if (jtag_usr1 == 1'b0)
|
387 |
|
|
begin
|
388 |
|
|
jtag_ir_usr1;
|
389 |
|
|
end
|
390 |
|
|
// send force_ir_capture
|
391 |
|
|
send_force_ir_capture;
|
392 |
|
|
// shift in the ir value
|
393 |
|
|
goto_dr_shift_state;
|
394 |
|
|
value_idx_cur = value_idx_cur - length;
|
395 |
|
|
for ( i = 0; i < length; i = i + 1)
|
396 |
|
|
begin
|
397 |
|
|
tms_reg = 1'b0;
|
398 |
|
|
tdi_reg = scan_values[value_idx_cur + i];
|
399 |
|
|
clock_tck(tms_reg,tdi_reg);
|
400 |
|
|
end
|
401 |
|
|
// pad with zeros if necessary
|
402 |
|
|
for(i = length; i < sld_node_ir_width; i = i + 1)
|
403 |
|
|
begin : zero_padding
|
404 |
|
|
tdi_reg = 1'b0;
|
405 |
|
|
tms_reg = 1'b0;
|
406 |
|
|
clock_tck(tms_reg,tdi_reg);
|
407 |
|
|
end //zero_padding
|
408 |
|
|
tdi_reg = 1'b1;
|
409 |
|
|
goto_update_state;
|
410 |
|
|
end // v_ir_scan_tsk
|
411 |
|
|
endtask // v_ir_scan
|
412 |
|
|
|
413 |
|
|
// performs a virtual dr scan
|
414 |
|
|
task v_dr_scan;
|
415 |
|
|
input [`DEFAULT_BIT_LENGTH - 1 : 0] length;
|
416 |
|
|
integer i;
|
417 |
|
|
begin : v_dr_scan_tsk
|
418 |
|
|
// if we are in usr1 then go to usr0 state
|
419 |
|
|
if (jtag_usr1 == 1'b1)
|
420 |
|
|
begin
|
421 |
|
|
jtag_ir_usr0;
|
422 |
|
|
end
|
423 |
|
|
// shift in the dr value
|
424 |
|
|
goto_dr_shift_state;
|
425 |
|
|
value_idx_cur = value_idx_cur - length;
|
426 |
|
|
for ( i = 0; i < length - 1; i = i + 1)
|
427 |
|
|
begin
|
428 |
|
|
tms_reg = 1'b0;
|
429 |
|
|
tdi_reg = scan_values[value_idx_cur + i];
|
430 |
|
|
clock_tck(tms_reg,tdi_reg);
|
431 |
|
|
end
|
432 |
|
|
// last bit is clocked together with state transition
|
433 |
|
|
tdi_reg = scan_values[value_idx_cur + i];
|
434 |
|
|
goto_update_state;
|
435 |
|
|
end // v_dr_scan_tsk
|
436 |
|
|
endtask // v_dr_scan
|
437 |
|
|
|
438 |
|
|
reg vj_sim_done;
|
439 |
|
|
initial
|
440 |
|
|
begin : sim_model
|
441 |
|
|
vj_sim_done = 0;
|
442 |
|
|
// initialize output registers
|
443 |
|
|
tck = 1'b1;
|
444 |
|
|
tms = 1'b0;
|
445 |
|
|
tdi = 1'b0;
|
446 |
|
|
// initialize variables
|
447 |
|
|
tms_reg = 1'b0;
|
448 |
|
|
tdi_reg = 1'b0;
|
449 |
|
|
two_character = 'b0;
|
450 |
|
|
last_length_idx = 0;
|
451 |
|
|
value_idx = 0;
|
452 |
|
|
value_idx_old = 0;
|
453 |
|
|
length_idx = 0;
|
454 |
|
|
length_idx_old = 0;
|
455 |
|
|
type_idx = 0;
|
456 |
|
|
type_idx_old = 0;
|
457 |
|
|
time_idx = 0;
|
458 |
|
|
time_idx_old = 0;
|
459 |
|
|
scan_length = 'b0;
|
460 |
|
|
scan_values = 'b0;
|
461 |
|
|
scan_type = 'b0;
|
462 |
|
|
scan_time = 'b0;
|
463 |
|
|
last_length = 'b0;
|
464 |
|
|
hex_value = 'b0;
|
465 |
|
|
c_state = `STARTSTATE;
|
466 |
|
|
// initialize current indices
|
467 |
|
|
value_idx_cur = sld_node_total_length;
|
468 |
|
|
type_idx_cur = `TYPE_SCAN_LENGTH;
|
469 |
|
|
time_idx_cur = `DEFAULT_SCAN_LENGTH;
|
470 |
|
|
length_idx_cur = `DEFAULT_SCAN_LENGTH;
|
471 |
|
|
for(char_idx = 0;two_character != "((";char_idx = char_idx + 8)
|
472 |
|
|
begin : character_loop
|
473 |
|
|
// convert two characters to equivalent 16-bit value
|
474 |
|
|
two_character[0] = sld_node_sim_action[char_idx];
|
475 |
|
|
two_character[1] = sld_node_sim_action[char_idx+1];
|
476 |
|
|
two_character[2] = sld_node_sim_action[char_idx+2];
|
477 |
|
|
two_character[3] = sld_node_sim_action[char_idx+3];
|
478 |
|
|
two_character[4] = sld_node_sim_action[char_idx+4];
|
479 |
|
|
two_character[5] = sld_node_sim_action[char_idx+5];
|
480 |
|
|
two_character[6] = sld_node_sim_action[char_idx+6];
|
481 |
|
|
two_character[7] = sld_node_sim_action[char_idx+7];
|
482 |
|
|
two_character[8] = sld_node_sim_action[char_idx+8];
|
483 |
|
|
two_character[9] = sld_node_sim_action[char_idx+9];
|
484 |
|
|
two_character[10] = sld_node_sim_action[char_idx+10];
|
485 |
|
|
two_character[11] = sld_node_sim_action[char_idx+11];
|
486 |
|
|
two_character[12] = sld_node_sim_action[char_idx+12];
|
487 |
|
|
two_character[13] = sld_node_sim_action[char_idx+13];
|
488 |
|
|
two_character[14] = sld_node_sim_action[char_idx+14];
|
489 |
|
|
two_character[15] = sld_node_sim_action[char_idx+15];
|
490 |
|
|
// use state machine to decode
|
491 |
|
|
case (c_state)
|
492 |
|
|
`STARTSTATE :
|
493 |
|
|
begin
|
494 |
|
|
if (two_character[15 : 8] != ")")
|
495 |
|
|
begin
|
496 |
|
|
c_state = `LENGTHSTATE;
|
497 |
|
|
end
|
498 |
|
|
end
|
499 |
|
|
`LENGTHSTATE :
|
500 |
|
|
begin
|
501 |
|
|
if (two_character[7 : 0] == ",")
|
502 |
|
|
begin
|
503 |
|
|
length_idx = length_idx_old + 32;
|
504 |
|
|
length_idx_old = length_idx;
|
505 |
|
|
c_state = `VALUESTATE;
|
506 |
|
|
end
|
507 |
|
|
else
|
508 |
|
|
begin
|
509 |
|
|
hex_value = hexToBits(two_character[7:0]);
|
510 |
|
|
scan_length [ length_idx] = hex_value[0];
|
511 |
|
|
scan_length [ length_idx + 1] = hex_value[1];
|
512 |
|
|
scan_length [ length_idx + 2] = hex_value[2];
|
513 |
|
|
scan_length [ length_idx + 3] = hex_value[3];
|
514 |
|
|
last_length [ last_length_idx] = hex_value[0];
|
515 |
|
|
last_length [ last_length_idx + 1] = hex_value[1];
|
516 |
|
|
last_length [ last_length_idx + 2] = hex_value[2];
|
517 |
|
|
last_length [ last_length_idx + 3] = hex_value[3];
|
518 |
|
|
length_idx = length_idx + 4;
|
519 |
|
|
last_length_idx = last_length_idx + 4;
|
520 |
|
|
end
|
521 |
|
|
end
|
522 |
|
|
`VALUESTATE :
|
523 |
|
|
begin
|
524 |
|
|
if (two_character[7 : 0] == ",")
|
525 |
|
|
begin
|
526 |
|
|
value_idx = value_idx_old + last_length;
|
527 |
|
|
value_idx_old = value_idx;
|
528 |
|
|
last_length = 'b0; // reset the last length value
|
529 |
|
|
last_length_idx = 0; // reset index for length
|
530 |
|
|
c_state = `TYPESTATE;
|
531 |
|
|
end
|
532 |
|
|
else
|
533 |
|
|
begin
|
534 |
|
|
hex_value = hexToBits(two_character[7:0]);
|
535 |
|
|
scan_values [ value_idx] = hex_value[0];
|
536 |
|
|
scan_values [ value_idx + 1] = hex_value[1];
|
537 |
|
|
scan_values [ value_idx + 2] = hex_value[2];
|
538 |
|
|
scan_values [ value_idx + 3] = hex_value[3];
|
539 |
|
|
value_idx = value_idx + 4;
|
540 |
|
|
end
|
541 |
|
|
end
|
542 |
|
|
`TYPESTATE :
|
543 |
|
|
begin
|
544 |
|
|
if (two_character[7 : 0] == ",")
|
545 |
|
|
begin
|
546 |
|
|
type_idx = type_idx + 4;
|
547 |
|
|
c_state = `TIMESTATE;
|
548 |
|
|
end
|
549 |
|
|
else
|
550 |
|
|
begin
|
551 |
|
|
hex_value = hexToBits(two_character[7:0]);
|
552 |
|
|
scan_type [ type_idx] = hex_value[0];
|
553 |
|
|
scan_type [ type_idx + 1] = hex_value[1];
|
554 |
|
|
scan_type [ type_idx + 2] = hex_value[2];
|
555 |
|
|
scan_type [ type_idx + 3] = hex_value[3];
|
556 |
|
|
end
|
557 |
|
|
end
|
558 |
|
|
`TIMESTATE :
|
559 |
|
|
begin
|
560 |
|
|
if (two_character[7 : 0] == "(")
|
561 |
|
|
begin
|
562 |
|
|
time_idx = time_idx_old + 32;
|
563 |
|
|
time_idx_old = time_idx;
|
564 |
|
|
c_state = `STARTSTATE;
|
565 |
|
|
end
|
566 |
|
|
else
|
567 |
|
|
begin
|
568 |
|
|
hex_value = hexToBits(two_character[7:0]);
|
569 |
|
|
scan_time [ time_idx] = hex_value[0];
|
570 |
|
|
scan_time [ time_idx + 1] = hex_value[1];
|
571 |
|
|
scan_time [ time_idx + 2] = hex_value[2];
|
572 |
|
|
scan_time [ time_idx + 3] = hex_value[3];
|
573 |
|
|
time_idx = time_idx + 4;
|
574 |
|
|
end
|
575 |
|
|
end
|
576 |
|
|
default :
|
577 |
|
|
c_state = `STARTSTATE;
|
578 |
|
|
endcase
|
579 |
|
|
end // block: character_loop
|
580 |
|
|
# (`CLK_PERIOD/2);
|
581 |
|
|
begin : execute
|
582 |
|
|
integer write_scan_idx;
|
583 |
|
|
integer tempLength_idx;
|
584 |
|
|
reg [`TYPE_BIT_LENGTH - 1 : 0] tempType;
|
585 |
|
|
reg [`DEFAULT_BIT_LENGTH - 1 : 0 ] tempLength;
|
586 |
|
|
reg [`DEFAULT_BIT_LENGTH - 1 : 0 ] tempTime;
|
587 |
|
|
reg [`TIME_BIT_LENGTH - 1 : 0 ] delayTime;
|
588 |
|
|
reset_jtag;
|
589 |
|
|
for (write_scan_idx = 0; write_scan_idx < sld_node_n_scan; write_scan_idx = write_scan_idx + 1)
|
590 |
|
|
begin : all_scans_loop
|
591 |
|
|
tempType[3] = scan_type[type_idx_cur];
|
592 |
|
|
tempType[2] = scan_type[type_idx_cur - 1];
|
593 |
|
|
tempType[1] = scan_type[type_idx_cur - 2];
|
594 |
|
|
tempType[0] = scan_type[type_idx_cur - 3];
|
595 |
|
|
time_idx_cur = time_idx_cur - `DEFAULT_BIT_LENGTH;
|
596 |
|
|
length_idx_cur = length_idx_cur - `DEFAULT_BIT_LENGTH;
|
597 |
|
|
for (tempLength_idx = 0; tempLength_idx < `DEFAULT_BIT_LENGTH; tempLength_idx = tempLength_idx + 1)
|
598 |
|
|
begin : get_scan_time
|
599 |
|
|
tempTime[tempLength_idx] = scan_time[time_idx_cur + tempLength_idx];
|
600 |
|
|
end // get_scan_time
|
601 |
|
|
delayTime =(`DELAY_RESOLUTION * `CLK_PERIOD * tempTime);
|
602 |
|
|
# delayTime;
|
603 |
|
|
if (tempType == `V_IR_SCAN_TYPE)
|
604 |
|
|
begin
|
605 |
|
|
for (tempLength_idx = 0; tempLength_idx < `DEFAULT_BIT_LENGTH; tempLength_idx = tempLength_idx + 1)
|
606 |
|
|
begin : ir_get_length
|
607 |
|
|
tempLength[tempLength_idx] = scan_length[length_idx_cur + tempLength_idx];
|
608 |
|
|
end // ir_get_length
|
609 |
|
|
v_ir_scan(tempLength);
|
610 |
|
|
end
|
611 |
|
|
else
|
612 |
|
|
begin
|
613 |
|
|
if (tempType == `V_DR_SCAN_TYPE)
|
614 |
|
|
begin
|
615 |
|
|
for (tempLength_idx = 0; tempLength_idx < `DEFAULT_BIT_LENGTH; tempLength_idx = tempLength_idx + 1)
|
616 |
|
|
begin : dr_get_length
|
617 |
|
|
tempLength[tempLength_idx] = scan_length[length_idx_cur + tempLength_idx];
|
618 |
|
|
end // dr_get_length
|
619 |
|
|
v_dr_scan(tempLength);
|
620 |
|
|
end
|
621 |
|
|
else
|
622 |
|
|
begin
|
623 |
|
|
$display("Invalid scan type");
|
624 |
|
|
end
|
625 |
|
|
end
|
626 |
|
|
type_idx_cur = type_idx_cur - 4;
|
627 |
|
|
end // all_scans_loop
|
628 |
|
|
//get into tlr state
|
629 |
|
|
for (tempLength_idx = 0; tempLength_idx < 6; tempLength_idx= tempLength_idx + 1)
|
630 |
|
|
begin
|
631 |
|
|
tms_reg = 1'b1;
|
632 |
|
|
clock_tck(tms_reg,tdi_reg);
|
633 |
|
|
end
|
634 |
|
|
end //execute
|
635 |
|
|
vj_sim_done = 1;
|
636 |
|
|
end // block: sim_model
|
637 |
|
|
endmodule // signal_gen
|
638 |
|
|
|
639 |
|
|
// END OF MODULE
|
640 |
|
|
|
641 |
|
|
|
642 |
|
|
|
643 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
644 |
|
|
// Module Name : jtag_tap_controller
|
645 |
|
|
//
|
646 |
|
|
// Description : Behavioral model of JTAG tap controller with state signals
|
647 |
|
|
//
|
648 |
|
|
// Limitation : Can only decode USER1 and USER0 instructions
|
649 |
|
|
//
|
650 |
|
|
// Results expected :
|
651 |
|
|
//
|
652 |
|
|
//
|
653 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
654 |
|
|
|
655 |
|
|
// BEGINNING OF MODULE
|
656 |
|
|
`timescale 1 ps / 1 ps
|
657 |
|
|
|
658 |
|
|
// MODULE DECLARATION
|
659 |
|
|
module jtag_tap_controller (tck,tms,tdi,jtag_tdo,tdo,jtag_tck,jtag_tms,jtag_tdi,
|
660 |
|
|
jtag_state_tlr,jtag_state_rti,jtag_state_drs,jtag_state_cdr,
|
661 |
|
|
jtag_state_sdr,jtag_state_e1dr,jtag_state_pdr,jtag_state_e2dr,
|
662 |
|
|
jtag_state_udr,jtag_state_irs,jtag_state_cir,jtag_state_sir,
|
663 |
|
|
jtag_state_e1ir,jtag_state_pir,jtag_state_e2ir,jtag_state_uir,
|
664 |
|
|
jtag_usr1);
|
665 |
|
|
|
666 |
|
|
|
667 |
|
|
// GLOBAL PARAMETER DECLARATION
|
668 |
|
|
parameter ir_register_width = 16;
|
669 |
|
|
|
670 |
|
|
// INPUT PORTS
|
671 |
|
|
input tck; // tck signal from signal_gen
|
672 |
|
|
input tms; // tms signal from signal_gen
|
673 |
|
|
input tdi; // tdi signal from signal_gen
|
674 |
|
|
input jtag_tdo; // tdo signal from hub
|
675 |
|
|
|
676 |
|
|
// OUTPUT PORTS
|
677 |
|
|
output tdo; // tdo signal to signal_gen
|
678 |
|
|
output jtag_tck; // tck signal from jtag
|
679 |
|
|
output jtag_tms; // tms signal from jtag
|
680 |
|
|
output jtag_tdi; // tdi signal from jtag
|
681 |
|
|
output jtag_state_tlr; // tlr state
|
682 |
|
|
output jtag_state_rti; // rti state
|
683 |
|
|
output jtag_state_drs; // select dr scan state
|
684 |
|
|
output jtag_state_cdr; // capture dr state
|
685 |
|
|
output jtag_state_sdr; // shift dr state
|
686 |
|
|
output jtag_state_e1dr; // exit1 dr state
|
687 |
|
|
output jtag_state_pdr; // pause dr state
|
688 |
|
|
output jtag_state_e2dr; // exit2 dr state
|
689 |
|
|
output jtag_state_udr; // update dr state
|
690 |
|
|
output jtag_state_irs; // select ir scan state
|
691 |
|
|
output jtag_state_cir; // capture ir state
|
692 |
|
|
output jtag_state_sir; // shift ir state
|
693 |
|
|
output jtag_state_e1ir; // exit1 ir state
|
694 |
|
|
output jtag_state_pir; // pause ir state
|
695 |
|
|
output jtag_state_e2ir; // exit2 ir state
|
696 |
|
|
output jtag_state_uir; // update ir state
|
697 |
|
|
output jtag_usr1; // jtag has usr1 instruction
|
698 |
|
|
|
699 |
|
|
// INTERNAL REGISTERS
|
700 |
|
|
|
701 |
|
|
reg tdo_reg;
|
702 |
|
|
// temporary tdo output register
|
703 |
|
|
reg tdo_rom_reg;
|
704 |
|
|
// temporary register used to generate 0101... during SIR_ST
|
705 |
|
|
reg jtag_usr1_reg;
|
706 |
|
|
// temporary jtag_usr1 register
|
707 |
|
|
reg jtag_reset_i;
|
708 |
|
|
// internal reset
|
709 |
|
|
reg [ 4 : 0 ] cState;
|
710 |
|
|
// register for current state
|
711 |
|
|
reg [ 4 : 0 ] nState;
|
712 |
|
|
// register for the next state signal
|
713 |
|
|
reg [ ir_register_width - 1 : 0] ir_srl;
|
714 |
|
|
// the ir shift register
|
715 |
|
|
reg [ ir_register_width - 1 : 0] ir_srl_hold;
|
716 |
|
|
// the ir shift register
|
717 |
|
|
|
718 |
|
|
// INTERNAL WIRES
|
719 |
|
|
wire [ 4 : 0 ] cState_tmp;
|
720 |
|
|
wire [ ir_register_width - 1 : 0] ir_srl_tmp;
|
721 |
|
|
|
722 |
|
|
|
723 |
|
|
// OUTPUT REGISTERS
|
724 |
|
|
reg jtag_state_tlr; // tlr state
|
725 |
|
|
reg jtag_state_rti; // rti state
|
726 |
|
|
reg jtag_state_drs; // select dr scan state
|
727 |
|
|
reg jtag_state_cdr; // capture dr state
|
728 |
|
|
reg jtag_state_sdr; // shift dr state
|
729 |
|
|
reg jtag_state_e1dr; // exit1 dr state
|
730 |
|
|
reg jtag_state_pdr; // pause dr state
|
731 |
|
|
reg jtag_state_e2dr; // exit2 dr state
|
732 |
|
|
reg jtag_state_udr; // update dr state
|
733 |
|
|
reg jtag_state_irs; // select ir scan state
|
734 |
|
|
reg jtag_state_cir; // capture ir state
|
735 |
|
|
reg jtag_state_sir; // shift ir state
|
736 |
|
|
reg jtag_state_e1ir; // exit1 ir state
|
737 |
|
|
reg jtag_state_pir; // pause ir state
|
738 |
|
|
reg jtag_state_e2ir; // exit2 ir state
|
739 |
|
|
reg jtag_state_uir; // update ir state
|
740 |
|
|
|
741 |
|
|
|
742 |
|
|
// INITIAL STATEMENTS
|
743 |
|
|
initial
|
744 |
|
|
begin
|
745 |
|
|
// initialize state registers
|
746 |
|
|
cState = `INIT_ST;
|
747 |
|
|
nState = `TLR_ST;
|
748 |
|
|
end
|
749 |
|
|
|
750 |
|
|
// State Register block
|
751 |
|
|
always @ (posedge tck or posedge jtag_reset_i)
|
752 |
|
|
begin : stateReg
|
753 |
|
|
if (jtag_reset_i)
|
754 |
|
|
begin
|
755 |
|
|
cState <= `TLR_ST;
|
756 |
|
|
ir_srl <= 'b0;
|
757 |
|
|
tdo_reg <= 1'b0;
|
758 |
|
|
tdo_rom_reg <= 1'b0;
|
759 |
|
|
jtag_usr1_reg <= 1'b0;
|
760 |
|
|
end
|
761 |
|
|
else
|
762 |
|
|
begin
|
763 |
|
|
// in capture ir, set-up tdo_rom_reg
|
764 |
|
|
// to generate 010101...
|
765 |
|
|
if(cState_tmp == `CIR_ST)
|
766 |
|
|
begin
|
767 |
|
|
tdo_rom_reg <= 1'b0;
|
768 |
|
|
end
|
769 |
|
|
else
|
770 |
|
|
begin
|
771 |
|
|
// write to shift register else pipe
|
772 |
|
|
if (cState_tmp == `SIR_ST)
|
773 |
|
|
begin
|
774 |
|
|
tdo_rom_reg <= ~tdo_rom_reg;
|
775 |
|
|
tdo_reg <= tdo_rom_reg;
|
776 |
|
|
ir_srl <= ir_srl_tmp >> 1;
|
777 |
|
|
ir_srl[ir_register_width - 1] <= tdi;
|
778 |
|
|
end
|
779 |
|
|
else
|
780 |
|
|
begin
|
781 |
|
|
tdo_reg <= jtag_tdo;
|
782 |
|
|
end
|
783 |
|
|
end
|
784 |
|
|
// check if in usr1 state
|
785 |
|
|
if (cState_tmp == `UIR_ST)
|
786 |
|
|
begin
|
787 |
|
|
if (ir_srl_hold == `JTAG_USR1_INSTR)
|
788 |
|
|
begin
|
789 |
|
|
jtag_usr1_reg <= 1'b1;
|
790 |
|
|
end
|
791 |
|
|
else
|
792 |
|
|
begin
|
793 |
|
|
jtag_usr1_reg <= 1'b0;
|
794 |
|
|
end
|
795 |
|
|
end
|
796 |
|
|
cState <= nState;
|
797 |
|
|
end
|
798 |
|
|
end // stateReg
|
799 |
|
|
|
800 |
|
|
// hold register
|
801 |
|
|
always @ (negedge tck or posedge jtag_reset_i)
|
802 |
|
|
begin : holdReg
|
803 |
|
|
if (jtag_reset_i)
|
804 |
|
|
begin
|
805 |
|
|
ir_srl_hold <= 'b0;
|
806 |
|
|
end
|
807 |
|
|
else
|
808 |
|
|
begin
|
809 |
|
|
if (cState == `E1IR_ST)
|
810 |
|
|
begin
|
811 |
|
|
ir_srl_hold <= ir_srl;
|
812 |
|
|
end
|
813 |
|
|
end
|
814 |
|
|
end // holdReg
|
815 |
|
|
|
816 |
|
|
// next state logic
|
817 |
|
|
always @(cState or tms)
|
818 |
|
|
begin : stateTrans
|
819 |
|
|
nState = cState;
|
820 |
|
|
case (cState)
|
821 |
|
|
`TLR_ST :
|
822 |
|
|
begin
|
823 |
|
|
if (tms == 1'b0)
|
824 |
|
|
begin
|
825 |
|
|
nState = `RTI_ST;
|
826 |
|
|
jtag_reset_i = 1'b0;
|
827 |
|
|
end
|
828 |
|
|
else
|
829 |
|
|
begin
|
830 |
|
|
jtag_reset_i = 1'b1;
|
831 |
|
|
end
|
832 |
|
|
end
|
833 |
|
|
`RTI_ST :
|
834 |
|
|
begin
|
835 |
|
|
if (tms)
|
836 |
|
|
begin
|
837 |
|
|
nState = `DRS_ST;
|
838 |
|
|
end
|
839 |
|
|
end
|
840 |
|
|
`DRS_ST :
|
841 |
|
|
begin
|
842 |
|
|
if (tms)
|
843 |
|
|
begin
|
844 |
|
|
nState = `IRS_ST;
|
845 |
|
|
end
|
846 |
|
|
else
|
847 |
|
|
begin
|
848 |
|
|
nState = `CDR_ST;
|
849 |
|
|
end
|
850 |
|
|
end
|
851 |
|
|
`CDR_ST :
|
852 |
|
|
begin
|
853 |
|
|
if (tms)
|
854 |
|
|
begin
|
855 |
|
|
nState = `E1DR_ST;
|
856 |
|
|
end
|
857 |
|
|
else
|
858 |
|
|
begin
|
859 |
|
|
nState = `SDR_ST;
|
860 |
|
|
end
|
861 |
|
|
end
|
862 |
|
|
`SDR_ST :
|
863 |
|
|
begin
|
864 |
|
|
if (tms)
|
865 |
|
|
begin
|
866 |
|
|
nState = `E1DR_ST;
|
867 |
|
|
end
|
868 |
|
|
end
|
869 |
|
|
`E1DR_ST :
|
870 |
|
|
begin
|
871 |
|
|
if (tms)
|
872 |
|
|
begin
|
873 |
|
|
nState = `UDR_ST;
|
874 |
|
|
end
|
875 |
|
|
else
|
876 |
|
|
begin
|
877 |
|
|
nState = `PDR_ST;
|
878 |
|
|
end
|
879 |
|
|
end
|
880 |
|
|
`PDR_ST :
|
881 |
|
|
begin
|
882 |
|
|
if (tms)
|
883 |
|
|
begin
|
884 |
|
|
nState = `E2DR_ST;
|
885 |
|
|
end
|
886 |
|
|
end
|
887 |
|
|
`E2DR_ST :
|
888 |
|
|
begin
|
889 |
|
|
if (tms)
|
890 |
|
|
begin
|
891 |
|
|
nState = `UDR_ST;
|
892 |
|
|
end
|
893 |
|
|
else
|
894 |
|
|
begin
|
895 |
|
|
nState = `SDR_ST;
|
896 |
|
|
end
|
897 |
|
|
end
|
898 |
|
|
`UDR_ST :
|
899 |
|
|
begin
|
900 |
|
|
if (tms)
|
901 |
|
|
begin
|
902 |
|
|
nState = `DRS_ST;
|
903 |
|
|
end
|
904 |
|
|
else
|
905 |
|
|
begin
|
906 |
|
|
nState = `RTI_ST;
|
907 |
|
|
end
|
908 |
|
|
end
|
909 |
|
|
`IRS_ST :
|
910 |
|
|
begin
|
911 |
|
|
if (tms)
|
912 |
|
|
begin
|
913 |
|
|
nState = `TLR_ST;
|
914 |
|
|
end
|
915 |
|
|
else
|
916 |
|
|
begin
|
917 |
|
|
nState = `CIR_ST;
|
918 |
|
|
end
|
919 |
|
|
end
|
920 |
|
|
`CIR_ST :
|
921 |
|
|
begin
|
922 |
|
|
if (tms)
|
923 |
|
|
begin
|
924 |
|
|
nState = `E1IR_ST;
|
925 |
|
|
end
|
926 |
|
|
else
|
927 |
|
|
begin
|
928 |
|
|
nState = `SIR_ST;
|
929 |
|
|
end
|
930 |
|
|
end
|
931 |
|
|
`SIR_ST :
|
932 |
|
|
begin
|
933 |
|
|
if (tms)
|
934 |
|
|
begin
|
935 |
|
|
nState = `E1IR_ST;
|
936 |
|
|
end
|
937 |
|
|
end
|
938 |
|
|
`E1IR_ST :
|
939 |
|
|
begin
|
940 |
|
|
if (tms)
|
941 |
|
|
begin
|
942 |
|
|
nState = `UIR_ST;
|
943 |
|
|
end
|
944 |
|
|
else
|
945 |
|
|
begin
|
946 |
|
|
nState = `PIR_ST;
|
947 |
|
|
end
|
948 |
|
|
end
|
949 |
|
|
`PIR_ST :
|
950 |
|
|
begin
|
951 |
|
|
if (tms)
|
952 |
|
|
begin
|
953 |
|
|
nState = `E2IR_ST;
|
954 |
|
|
end
|
955 |
|
|
end
|
956 |
|
|
`E2IR_ST :
|
957 |
|
|
begin
|
958 |
|
|
if (tms)
|
959 |
|
|
begin
|
960 |
|
|
nState = `UIR_ST;
|
961 |
|
|
end
|
962 |
|
|
else
|
963 |
|
|
begin
|
964 |
|
|
nState = `SIR_ST;
|
965 |
|
|
end
|
966 |
|
|
end
|
967 |
|
|
`UIR_ST :
|
968 |
|
|
begin
|
969 |
|
|
if (tms)
|
970 |
|
|
begin
|
971 |
|
|
nState = `DRS_ST;
|
972 |
|
|
end
|
973 |
|
|
else
|
974 |
|
|
begin
|
975 |
|
|
nState = `RTI_ST;
|
976 |
|
|
end
|
977 |
|
|
end
|
978 |
|
|
`INIT_ST :
|
979 |
|
|
begin
|
980 |
|
|
nState = `TLR_ST;
|
981 |
|
|
end
|
982 |
|
|
default :
|
983 |
|
|
begin
|
984 |
|
|
$display("Tap Controller State machine error");
|
985 |
|
|
$display ("Time: %0t Instance: %m", $time);
|
986 |
|
|
nState = `TLR_ST;
|
987 |
|
|
end
|
988 |
|
|
endcase
|
989 |
|
|
end // stateTrans
|
990 |
|
|
|
991 |
|
|
// Output logic
|
992 |
|
|
always @ (cState)
|
993 |
|
|
begin : output_logic
|
994 |
|
|
jtag_state_tlr <= 1'b0;
|
995 |
|
|
jtag_state_rti <= 1'b0;
|
996 |
|
|
jtag_state_drs <= 1'b0;
|
997 |
|
|
jtag_state_cdr <= 1'b0;
|
998 |
|
|
jtag_state_sdr <= 1'b0;
|
999 |
|
|
jtag_state_e1dr <= 1'b0;
|
1000 |
|
|
jtag_state_pdr <= 1'b0;
|
1001 |
|
|
jtag_state_e2dr <= 1'b0;
|
1002 |
|
|
jtag_state_udr <= 1'b0;
|
1003 |
|
|
jtag_state_irs <= 1'b0;
|
1004 |
|
|
jtag_state_cir <= 1'b0;
|
1005 |
|
|
jtag_state_sir <= 1'b0;
|
1006 |
|
|
jtag_state_e1ir <= 1'b0;
|
1007 |
|
|
jtag_state_pir <= 1'b0;
|
1008 |
|
|
jtag_state_e2ir <= 1'b0;
|
1009 |
|
|
jtag_state_uir <= 1'b0;
|
1010 |
|
|
case (cState)
|
1011 |
|
|
`TLR_ST :
|
1012 |
|
|
begin
|
1013 |
|
|
jtag_state_tlr <= 1'b1;
|
1014 |
|
|
end
|
1015 |
|
|
`RTI_ST :
|
1016 |
|
|
begin
|
1017 |
|
|
jtag_state_rti <= 1'b1;
|
1018 |
|
|
end
|
1019 |
|
|
`DRS_ST :
|
1020 |
|
|
begin
|
1021 |
|
|
jtag_state_drs <= 1'b1;
|
1022 |
|
|
end
|
1023 |
|
|
`CDR_ST :
|
1024 |
|
|
begin
|
1025 |
|
|
jtag_state_cdr <= 1'b1;
|
1026 |
|
|
end
|
1027 |
|
|
`SDR_ST :
|
1028 |
|
|
begin
|
1029 |
|
|
jtag_state_sdr <= 1'b1;
|
1030 |
|
|
end
|
1031 |
|
|
`E1DR_ST :
|
1032 |
|
|
begin
|
1033 |
|
|
jtag_state_e1dr <= 1'b1;
|
1034 |
|
|
end
|
1035 |
|
|
`PDR_ST :
|
1036 |
|
|
begin
|
1037 |
|
|
jtag_state_pdr <= 1'b1;
|
1038 |
|
|
end
|
1039 |
|
|
`E2DR_ST :
|
1040 |
|
|
begin
|
1041 |
|
|
jtag_state_e2dr <= 1'b1;
|
1042 |
|
|
end
|
1043 |
|
|
`UDR_ST :
|
1044 |
|
|
begin
|
1045 |
|
|
jtag_state_udr <= 1'b1;
|
1046 |
|
|
end
|
1047 |
|
|
`IRS_ST :
|
1048 |
|
|
begin
|
1049 |
|
|
jtag_state_irs <= 1'b1;
|
1050 |
|
|
end
|
1051 |
|
|
`CIR_ST :
|
1052 |
|
|
begin
|
1053 |
|
|
jtag_state_cir <= 1'b1;
|
1054 |
|
|
end
|
1055 |
|
|
`SIR_ST :
|
1056 |
|
|
begin
|
1057 |
|
|
jtag_state_sir <= 1'b1;
|
1058 |
|
|
end
|
1059 |
|
|
`E1IR_ST :
|
1060 |
|
|
begin
|
1061 |
|
|
jtag_state_e1ir <= 1'b1;
|
1062 |
|
|
end
|
1063 |
|
|
`PIR_ST :
|
1064 |
|
|
begin
|
1065 |
|
|
jtag_state_pir <= 1'b1;
|
1066 |
|
|
end
|
1067 |
|
|
`E2IR_ST :
|
1068 |
|
|
begin
|
1069 |
|
|
jtag_state_e2ir <= 1'b1;
|
1070 |
|
|
end
|
1071 |
|
|
`UIR_ST :
|
1072 |
|
|
begin
|
1073 |
|
|
jtag_state_uir <= 1'b1;
|
1074 |
|
|
end
|
1075 |
|
|
default :
|
1076 |
|
|
begin
|
1077 |
|
|
$display("Tap Controller State machine output error");
|
1078 |
|
|
$display ("Time: %0t Instance: %m", $time);
|
1079 |
|
|
end
|
1080 |
|
|
endcase
|
1081 |
|
|
end // output_logic
|
1082 |
|
|
// temporary values
|
1083 |
|
|
assign ir_srl_tmp = ir_srl;
|
1084 |
|
|
assign cState_tmp = cState;
|
1085 |
|
|
|
1086 |
|
|
// Pipe through signals
|
1087 |
|
|
assign tdo = tdo_reg;
|
1088 |
|
|
assign jtag_tck = tck;
|
1089 |
|
|
assign jtag_tdi = tdi;
|
1090 |
|
|
assign jtag_tms = tms;
|
1091 |
|
|
assign jtag_usr1 = jtag_usr1_reg;
|
1092 |
|
|
|
1093 |
|
|
endmodule
|
1094 |
|
|
// END OF MODULE
|
1095 |
|
|
|
1096 |
|
|
|
1097 |
|
|
|
1098 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
1099 |
|
|
// Module Name : dummy_hub
|
1100 |
|
|
//
|
1101 |
|
|
// Description : Acts as node and mux between the tap controller and
|
1102 |
|
|
// user design. Generates hub signals
|
1103 |
|
|
//
|
1104 |
|
|
// Limitation : Assumes only one node. Ignores user input on tdo and ir_out.
|
1105 |
|
|
//
|
1106 |
|
|
// Results expected :
|
1107 |
|
|
//
|
1108 |
|
|
//
|
1109 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
1110 |
|
|
|
1111 |
|
|
// BEGINNING OF MODULE
|
1112 |
|
|
`timescale 1 ps / 1 ps
|
1113 |
|
|
|
1114 |
|
|
// MODULE DECLARATION
|
1115 |
|
|
|
1116 |
|
|
module dummy_hub (jtag_tck,jtag_tdi,jtag_tms,jtag_usr1,jtag_state_tlr,jtag_state_rti,
|
1117 |
|
|
jtag_state_drs,jtag_state_cdr,jtag_state_sdr,jtag_state_e1dr,
|
1118 |
|
|
jtag_state_pdr,jtag_state_e2dr,jtag_state_udr,jtag_state_irs,
|
1119 |
|
|
jtag_state_cir,jtag_state_sir,jtag_state_e1ir,jtag_state_pir,
|
1120 |
|
|
jtag_state_e2ir,jtag_state_uir,dummy_tdo,virtual_ir_out,
|
1121 |
|
|
jtag_tdo,dummy_tck,dummy_tdi,dummy_tms,dummy_state_tlr,
|
1122 |
|
|
dummy_state_rti,dummy_state_drs,dummy_state_cdr,dummy_state_sdr,
|
1123 |
|
|
dummy_state_e1dr,dummy_state_pdr,dummy_state_e2dr,dummy_state_udr,
|
1124 |
|
|
dummy_state_irs,dummy_state_cir,dummy_state_sir,dummy_state_e1ir,
|
1125 |
|
|
dummy_state_pir,dummy_state_e2ir,dummy_state_uir,virtual_state_cdr,
|
1126 |
|
|
virtual_state_sdr,virtual_state_e1dr,virtual_state_pdr,virtual_state_e2dr,
|
1127 |
|
|
virtual_state_udr,virtual_state_cir,virtual_state_uir,virtual_ir_in);
|
1128 |
|
|
|
1129 |
|
|
|
1130 |
|
|
// GLOBAL PARAMETER DECLARATION
|
1131 |
|
|
parameter sld_node_ir_width = 16;
|
1132 |
|
|
|
1133 |
|
|
// INPUT PORTS
|
1134 |
|
|
|
1135 |
|
|
input jtag_tck; // tck signal from tap controller
|
1136 |
|
|
input jtag_tdi; // tdi signal from tap controller
|
1137 |
|
|
input jtag_tms; // tms signal from tap controller
|
1138 |
|
|
input jtag_usr1; // usr1 signal from tap controller
|
1139 |
|
|
input jtag_state_tlr; // tlr state signal from tap controller
|
1140 |
|
|
input jtag_state_rti; // rti state signal from tap controller
|
1141 |
|
|
input jtag_state_drs; // drs state signal from tap controller
|
1142 |
|
|
input jtag_state_cdr; // cdr state signal from tap controller
|
1143 |
|
|
input jtag_state_sdr; // sdr state signal from tap controller
|
1144 |
|
|
input jtag_state_e1dr;// e1dr state signal from tap controller
|
1145 |
|
|
input jtag_state_pdr; // pdr state signal from tap controller
|
1146 |
|
|
input jtag_state_e2dr;// esdr state signal from tap controller
|
1147 |
|
|
input jtag_state_udr; // udr state signal from tap controller
|
1148 |
|
|
input jtag_state_irs; // irs state signal from tap controller
|
1149 |
|
|
input jtag_state_cir; // cir state signals from tap controller
|
1150 |
|
|
input jtag_state_sir; // sir state signal from tap controller
|
1151 |
|
|
input jtag_state_e1ir;// e1ir state signal from tap controller
|
1152 |
|
|
input jtag_state_pir; // pir state signals from tap controller
|
1153 |
|
|
input jtag_state_e2ir;// e2ir state signal from tap controller
|
1154 |
|
|
input jtag_state_uir; // uir state signal from tap controller
|
1155 |
|
|
input dummy_tdo; // tdo signal from world
|
1156 |
|
|
input [sld_node_ir_width - 1 : 0] virtual_ir_out; // captures parallel input from
|
1157 |
|
|
|
1158 |
|
|
// OUTPUT PORTS
|
1159 |
|
|
output jtag_tdo; // tdo signal to tap controller
|
1160 |
|
|
output dummy_tck; // tck signal to world
|
1161 |
|
|
output dummy_tdi; // tdi signal to world
|
1162 |
|
|
output dummy_tms; // tms signal to world
|
1163 |
|
|
output dummy_state_tlr; // tlr state signal to world
|
1164 |
|
|
output dummy_state_rti; // rti state signal to world
|
1165 |
|
|
output dummy_state_drs; // drs state signal to world
|
1166 |
|
|
output dummy_state_cdr; // cdr state signal to world
|
1167 |
|
|
output dummy_state_sdr; // sdr state signal to world
|
1168 |
|
|
output dummy_state_e1dr; // e1dr state signal to the world
|
1169 |
|
|
output dummy_state_pdr; // pdr state signal to world
|
1170 |
|
|
output dummy_state_e2dr; // e2dr state signal to world
|
1171 |
|
|
output dummy_state_udr; // udr state signal to world
|
1172 |
|
|
output dummy_state_irs; // irs state signal to world
|
1173 |
|
|
output dummy_state_cir; // cir state signal to world
|
1174 |
|
|
output dummy_state_sir; // sir state signal to world
|
1175 |
|
|
output dummy_state_e1ir; // e1ir state signal to world
|
1176 |
|
|
output dummy_state_pir; // pir state signal to world
|
1177 |
|
|
output dummy_state_e2ir; // e2ir state signal to world
|
1178 |
|
|
output dummy_state_uir; // uir state signal to world
|
1179 |
|
|
output virtual_state_cdr; // virtual cdr state signal
|
1180 |
|
|
output virtual_state_sdr; // virtual sdr state signal
|
1181 |
|
|
output virtual_state_e1dr; // virtual e1dr state signal
|
1182 |
|
|
output virtual_state_pdr; // virtula pdr state signal
|
1183 |
|
|
output virtual_state_e2dr; // virtual e2dr state signal
|
1184 |
|
|
output virtual_state_udr; // virtual udr state signal
|
1185 |
|
|
output virtual_state_cir; // virtual cir state signal
|
1186 |
|
|
output virtual_state_uir; // virtual uir state signal
|
1187 |
|
|
output [sld_node_ir_width - 1 : 0] virtual_ir_in; // parallel output to user design
|
1188 |
|
|
|
1189 |
|
|
|
1190 |
|
|
`define SLD_NODE_IR_WIDTH_I sld_node_ir_width + `NUM_SELECTION_BITS // internal ir width
|
1191 |
|
|
|
1192 |
|
|
// INTERNAL REGISTERS
|
1193 |
|
|
reg capture_ir; // signals force_ir_capture instruction
|
1194 |
|
|
reg jtag_tdo_reg; // register for jtag_tdo
|
1195 |
|
|
reg dummy_tdi_reg; // register for dummy_tdi
|
1196 |
|
|
reg dummy_tck_reg; // register for dummy_tck.
|
1197 |
|
|
reg [`SLD_NODE_IR_WIDTH_I - 1 : 0] ir_srl; // ir shift register
|
1198 |
|
|
wire [`SLD_NODE_IR_WIDTH_I - 1 : 0] ir_srl_tmp; // ir shift register
|
1199 |
|
|
reg [`SLD_NODE_IR_WIDTH_I - 1 : 0] ir_srl_hold; //hold register for ir shift register
|
1200 |
|
|
|
1201 |
|
|
// OUTPUT REGISTERS
|
1202 |
|
|
reg [sld_node_ir_width - 1 : 0] virtual_ir_in;
|
1203 |
|
|
|
1204 |
|
|
// INITIAL STATEMENTS
|
1205 |
|
|
always @ (posedge jtag_tck or posedge jtag_state_tlr)
|
1206 |
|
|
begin : simulation_logic
|
1207 |
|
|
if (jtag_state_tlr) // asynchronous active high reset
|
1208 |
|
|
begin : active_hi_async_reset
|
1209 |
|
|
ir_srl <= 'b0;
|
1210 |
|
|
jtag_tdo_reg <= 1'b0;
|
1211 |
|
|
dummy_tdi_reg <= 1'b0;
|
1212 |
|
|
end // active_hi_async_reset
|
1213 |
|
|
else
|
1214 |
|
|
begin : rising_edge_jtag_tck
|
1215 |
|
|
// logic for shifting in data and piping data through
|
1216 |
|
|
// logic for muxing inputs to outputs and otherwise
|
1217 |
|
|
if (jtag_usr1 && jtag_state_sdr)
|
1218 |
|
|
begin : shift_in_out_usr1
|
1219 |
|
|
jtag_tdo_reg <= ir_srl_tmp[0];
|
1220 |
|
|
ir_srl <= ir_srl_tmp >> 1;
|
1221 |
|
|
ir_srl[`SLD_NODE_IR_WIDTH_I - 1] <= jtag_tdi;
|
1222 |
|
|
end // shift_in_out_usr1
|
1223 |
|
|
else
|
1224 |
|
|
begin
|
1225 |
|
|
if (capture_ir && jtag_state_cdr)
|
1226 |
|
|
begin : capture_virtual_ir_out
|
1227 |
|
|
ir_srl[`SLD_NODE_IR_WIDTH_I - 2 : `NUM_SELECTION_BITS - 1] <= virtual_ir_out;
|
1228 |
|
|
end // capture_virtual_ir_out
|
1229 |
|
|
else
|
1230 |
|
|
begin
|
1231 |
|
|
if (capture_ir && jtag_state_sdr)
|
1232 |
|
|
begin : shift_in_out_usr0
|
1233 |
|
|
jtag_tdo_reg <= ir_srl_tmp[0];
|
1234 |
|
|
ir_srl <= ir_srl_tmp >> 1;
|
1235 |
|
|
ir_srl[`SLD_NODE_IR_WIDTH_I - 1] <= jtag_tdi;
|
1236 |
|
|
end // shift_in_out_usr0
|
1237 |
|
|
else
|
1238 |
|
|
begin
|
1239 |
|
|
if (jtag_state_sdr)
|
1240 |
|
|
begin : pipe_through
|
1241 |
|
|
dummy_tdi_reg <= jtag_tdi;
|
1242 |
|
|
jtag_tdo_reg <= dummy_tdo;
|
1243 |
|
|
end // pipe_through
|
1244 |
|
|
end
|
1245 |
|
|
end
|
1246 |
|
|
end
|
1247 |
|
|
end // rising_edge_jtag_tck
|
1248 |
|
|
end // simulation_logic
|
1249 |
|
|
|
1250 |
|
|
// always block for writing to capture_ir
|
1251 |
|
|
// stops nlint from complaining.
|
1252 |
|
|
always @ (posedge jtag_tck or posedge jtag_state_tlr)
|
1253 |
|
|
begin : capture_ir_logic
|
1254 |
|
|
if (jtag_state_tlr) // asynchronous active high reset
|
1255 |
|
|
begin : active_hi_async_reset
|
1256 |
|
|
capture_ir <= 1'b0;
|
1257 |
|
|
end // active_hi_async_reset
|
1258 |
|
|
else
|
1259 |
|
|
begin : rising_edge_jtag_tck
|
1260 |
|
|
// should check for 011 instruction
|
1261 |
|
|
// but we know that it is the only instruction ever sent to the
|
1262 |
|
|
// hub. So all we have to do is check the selection bit and udr
|
1263 |
|
|
// and usr1 state
|
1264 |
|
|
// logic for capture_ir signal
|
1265 |
|
|
if (jtag_state_udr && (ir_srl[`SLD_NODE_IR_WIDTH_I - 1] == 1'b0))
|
1266 |
|
|
begin
|
1267 |
|
|
capture_ir <= jtag_usr1;
|
1268 |
|
|
end
|
1269 |
|
|
else
|
1270 |
|
|
begin
|
1271 |
|
|
if (jtag_state_e1dr)
|
1272 |
|
|
begin
|
1273 |
|
|
capture_ir <= 1'b0;
|
1274 |
|
|
end
|
1275 |
|
|
end
|
1276 |
|
|
end // rising_edge_jtag_tck
|
1277 |
|
|
end // capture_ir_logic
|
1278 |
|
|
|
1279 |
|
|
// outputs - rising edge of clock
|
1280 |
|
|
always @ (posedge jtag_tck or posedge jtag_state_tlr)
|
1281 |
|
|
begin : parallel_ir_out
|
1282 |
|
|
if (jtag_state_tlr)
|
1283 |
|
|
begin : active_hi_async_reset
|
1284 |
|
|
virtual_ir_in <= 'b0;
|
1285 |
|
|
end
|
1286 |
|
|
else
|
1287 |
|
|
begin : rising_edge_jtag_tck
|
1288 |
|
|
virtual_ir_in <= ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 2 : `NUM_SELECTION_BITS - 1];
|
1289 |
|
|
end
|
1290 |
|
|
end
|
1291 |
|
|
|
1292 |
|
|
// outputs - falling edge of clock, separated for clarity
|
1293 |
|
|
always @ (negedge jtag_tck or posedge jtag_state_tlr)
|
1294 |
|
|
begin : shift_reg_hold
|
1295 |
|
|
if (jtag_state_tlr)
|
1296 |
|
|
begin : active_hi_async_reset
|
1297 |
|
|
ir_srl_hold <= 'b0;
|
1298 |
|
|
end
|
1299 |
|
|
else
|
1300 |
|
|
begin
|
1301 |
|
|
if (ir_srl[`SLD_NODE_IR_WIDTH_I - 1] && jtag_state_e1dr)
|
1302 |
|
|
begin
|
1303 |
|
|
ir_srl_hold <= ir_srl;
|
1304 |
|
|
end
|
1305 |
|
|
end
|
1306 |
|
|
end // shift_reg_hold
|
1307 |
|
|
|
1308 |
|
|
// generate tck in sync with tdi
|
1309 |
|
|
always @ (posedge jtag_tck or negedge jtag_tck)
|
1310 |
|
|
begin : gen_tck
|
1311 |
|
|
dummy_tck_reg <= jtag_tck;
|
1312 |
|
|
end // gen_tck
|
1313 |
|
|
// temporary signals
|
1314 |
|
|
assign ir_srl_tmp = ir_srl;
|
1315 |
|
|
|
1316 |
|
|
// Pipe through signals
|
1317 |
|
|
assign dummy_state_tlr = jtag_state_tlr;
|
1318 |
|
|
assign dummy_state_rti = jtag_state_rti;
|
1319 |
|
|
assign dummy_state_drs = jtag_state_drs;
|
1320 |
|
|
assign dummy_state_cdr = jtag_state_cdr;
|
1321 |
|
|
assign dummy_state_sdr = jtag_state_sdr;
|
1322 |
|
|
assign dummy_state_e1dr = jtag_state_e1dr;
|
1323 |
|
|
assign dummy_state_pdr = jtag_state_pdr;
|
1324 |
|
|
assign dummy_state_e2dr = jtag_state_e2dr;
|
1325 |
|
|
assign dummy_state_udr = jtag_state_udr;
|
1326 |
|
|
assign dummy_state_irs = jtag_state_irs;
|
1327 |
|
|
assign dummy_state_cir = jtag_state_cir;
|
1328 |
|
|
assign dummy_state_sir = jtag_state_sir;
|
1329 |
|
|
assign dummy_state_e1ir = jtag_state_e1ir;
|
1330 |
|
|
assign dummy_state_pir = jtag_state_pir;
|
1331 |
|
|
assign dummy_state_e2ir = jtag_state_e2ir;
|
1332 |
|
|
assign dummy_state_uir = jtag_state_uir;
|
1333 |
|
|
assign dummy_tms = jtag_tms;
|
1334 |
|
|
|
1335 |
|
|
|
1336 |
|
|
// Virtual signals
|
1337 |
|
|
assign virtual_state_uir = jtag_usr1 && jtag_state_udr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
|
1338 |
|
|
assign virtual_state_cir = jtag_usr1 && jtag_state_cdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
|
1339 |
|
|
assign virtual_state_udr = (! jtag_usr1) && jtag_state_udr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
|
1340 |
|
|
assign virtual_state_e2dr = (! jtag_usr1) && jtag_state_e2dr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
|
1341 |
|
|
assign virtual_state_pdr = (! jtag_usr1) && jtag_state_pdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
|
1342 |
|
|
assign virtual_state_e1dr = (! jtag_usr1) && jtag_state_e1dr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
|
1343 |
|
|
assign virtual_state_sdr = (! jtag_usr1) && jtag_state_sdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
|
1344 |
|
|
assign virtual_state_cdr = (! jtag_usr1) && jtag_state_cdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
|
1345 |
|
|
|
1346 |
|
|
// registered output
|
1347 |
|
|
assign jtag_tdo = jtag_tdo_reg;
|
1348 |
|
|
assign dummy_tdi = dummy_tdi_reg;
|
1349 |
|
|
assign dummy_tck = dummy_tck_reg;
|
1350 |
|
|
|
1351 |
|
|
endmodule
|
1352 |
|
|
// END OF MODULE
|
1353 |
|
|
|
1354 |
|
|
|
1355 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
1356 |
|
|
// Module Name : sld_virtual_jtag
|
1357 |
|
|
//
|
1358 |
|
|
// Description : Simulation model for SLD_VIRTUAL_JTAG megafunction
|
1359 |
|
|
//
|
1360 |
|
|
// Limitation : None
|
1361 |
|
|
//
|
1362 |
|
|
// Results expected :
|
1363 |
|
|
//
|
1364 |
|
|
//
|
1365 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
1366 |
|
|
|
1367 |
|
|
// BEGINNING OF MODULE
|
1368 |
|
|
`timescale 1 ps / 1 ps
|
1369 |
|
|
`define IR_REGISTER_WIDTH 10;
|
1370 |
|
|
|
1371 |
|
|
|
1372 |
|
|
// MODULE DECLARATION
|
1373 |
|
|
module sld_virtual_jtag (tdo,ir_out,tck,tdi,ir_in,virtual_state_cdr,virtual_state_sdr,
|
1374 |
|
|
virtual_state_e1dr,virtual_state_pdr,virtual_state_e2dr,
|
1375 |
|
|
virtual_state_udr,virtual_state_cir,virtual_state_uir,
|
1376 |
|
|
jtag_state_tlr,jtag_state_rti,jtag_state_sdrs,jtag_state_cdr,
|
1377 |
|
|
jtag_state_sdr,jtag_state_e1dr,jtag_state_pdr,jtag_state_e2dr,
|
1378 |
|
|
jtag_state_udr,jtag_state_sirs,jtag_state_cir,jtag_state_sir,
|
1379 |
|
|
jtag_state_e1ir,jtag_state_pir,jtag_state_e2ir,jtag_state_uir,
|
1380 |
|
|
tms);
|
1381 |
|
|
|
1382 |
|
|
|
1383 |
|
|
// GLOBAL PARAMETER DECLARATION
|
1384 |
|
|
parameter lpm_type = "SLD_VIRTUAL_JTAG"; // required by coding standard
|
1385 |
|
|
parameter lpm_hint = "SLD_VIRTUAL_JTAG"; // required by coding standard
|
1386 |
|
|
parameter sld_auto_instance_index = "NO"; //Yes if auto index is desired and no otherwise
|
1387 |
|
|
parameter sld_instance_index = 0; // index to be used if SLD_AUTO_INDEX is no
|
1388 |
|
|
parameter sld_ir_width = 1; //the width of the IR register
|
1389 |
|
|
parameter sld_sim_n_scan = 0; // the number of scans in the simulatiom parameters
|
1390 |
|
|
parameter sld_sim_total_length = 0; // The total bit width of all scan values
|
1391 |
|
|
parameter sld_sim_action = ""; // the actions to be simulated
|
1392 |
|
|
|
1393 |
|
|
// local parameter declaration
|
1394 |
|
|
defparam user_input.sld_node_ir_width = sld_ir_width;
|
1395 |
|
|
defparam user_input.sld_node_n_scan = sld_sim_n_scan;
|
1396 |
|
|
defparam user_input.sld_node_total_length = sld_sim_total_length;
|
1397 |
|
|
defparam user_input.sld_node_sim_action = sld_sim_action;
|
1398 |
|
|
defparam jtag.ir_register_width = 10 ; // compilation fails if defined constant is used
|
1399 |
|
|
defparam hub.sld_node_ir_width = sld_ir_width;
|
1400 |
|
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|
1401 |
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|
1402 |
|
|
// INPUT PORTS DECLARATION
|
1403 |
|
|
input tdo; // tdo signal into megafunction
|
1404 |
|
|
input [sld_ir_width - 1 : 0] ir_out;// parallel ir data into megafunction
|
1405 |
|
|
|
1406 |
|
|
// OUTPUT PORTS DECLARATION
|
1407 |
|
|
output tck; // tck signal from megafunction
|
1408 |
|
|
output tdi; // tdi signal from megafunction
|
1409 |
|
|
output virtual_state_cdr; // cdr state signal of megafunction
|
1410 |
|
|
output virtual_state_sdr; // sdr state signal of megafunction
|
1411 |
|
|
output virtual_state_e1dr;// e1dr state signal of megafunction
|
1412 |
|
|
output virtual_state_pdr; // pdr state signal of megafunction
|
1413 |
|
|
output virtual_state_e2dr;// e2dr state signal of megafunction
|
1414 |
|
|
output virtual_state_udr; // udr state signal of megafunction
|
1415 |
|
|
output virtual_state_cir; // cir state signal of megafunction
|
1416 |
|
|
output virtual_state_uir; // uir state signal of megafunction
|
1417 |
|
|
output jtag_state_tlr; // Test, Logic, Reset state
|
1418 |
|
|
output jtag_state_rti; // Run, Test, Idle state
|
1419 |
|
|
output jtag_state_sdrs; // Select DR scan state
|
1420 |
|
|
output jtag_state_cdr; // capture DR state
|
1421 |
|
|
output jtag_state_sdr; // Shift DR state
|
1422 |
|
|
output jtag_state_e1dr; // exit 1 dr state
|
1423 |
|
|
output jtag_state_pdr; // pause dr state
|
1424 |
|
|
output jtag_state_e2dr; // exit 2 dr state
|
1425 |
|
|
output jtag_state_udr; // update dr state
|
1426 |
|
|
output jtag_state_sirs; // Select IR scan state
|
1427 |
|
|
output jtag_state_cir; // capture IR state
|
1428 |
|
|
output jtag_state_sir; // shift IR state
|
1429 |
|
|
output jtag_state_e1ir; // exit 1 IR state
|
1430 |
|
|
output jtag_state_pir; // pause IR state
|
1431 |
|
|
output jtag_state_e2ir; // exit 2 IR state
|
1432 |
|
|
output jtag_state_uir; // update IR state
|
1433 |
|
|
output tms; // tms signal
|
1434 |
|
|
output [sld_ir_width - 1 : 0] ir_in; // paraller ir data from megafunction
|
1435 |
|
|
|
1436 |
|
|
// connecting wires
|
1437 |
|
|
wire tck_i;
|
1438 |
|
|
wire tms_i;
|
1439 |
|
|
wire tdi_i;
|
1440 |
|
|
wire jtag_usr1_i;
|
1441 |
|
|
wire tdo_i;
|
1442 |
|
|
wire jtag_tdo_i;
|
1443 |
|
|
wire jtag_tck_i;
|
1444 |
|
|
wire jtag_tms_i;
|
1445 |
|
|
wire jtag_tdi_i;
|
1446 |
|
|
wire jtag_state_tlr_i;
|
1447 |
|
|
wire jtag_state_rti_i;
|
1448 |
|
|
wire jtag_state_drs_i;
|
1449 |
|
|
wire jtag_state_cdr_i;
|
1450 |
|
|
wire jtag_state_sdr_i;
|
1451 |
|
|
wire jtag_state_e1dr_i;
|
1452 |
|
|
wire jtag_state_pdr_i;
|
1453 |
|
|
wire jtag_state_e2dr_i;
|
1454 |
|
|
wire jtag_state_udr_i;
|
1455 |
|
|
wire jtag_state_irs_i;
|
1456 |
|
|
wire jtag_state_cir_i;
|
1457 |
|
|
wire jtag_state_sir_i;
|
1458 |
|
|
wire jtag_state_e1ir_i;
|
1459 |
|
|
wire jtag_state_pir_i;
|
1460 |
|
|
wire jtag_state_e2ir_i;
|
1461 |
|
|
wire jtag_state_uir_i;
|
1462 |
|
|
|
1463 |
|
|
|
1464 |
|
|
// COMPONENT INSTANTIATIONS
|
1465 |
|
|
// generates input to jtag controller
|
1466 |
|
|
signal_gen user_input (tck_i,tms_i,tdi_i,jtag_usr1_i,tdo_i);
|
1467 |
|
|
|
1468 |
|
|
// the JTAG TAP controller
|
1469 |
|
|
jtag_tap_controller jtag (tck_i,tms_i,tdi_i,jtag_tdo_i,
|
1470 |
|
|
tdo_i,jtag_tck_i,jtag_tms_i,jtag_tdi_i,
|
1471 |
|
|
jtag_state_tlr_i,jtag_state_rti_i,
|
1472 |
|
|
jtag_state_drs_i,jtag_state_cdr_i,
|
1473 |
|
|
jtag_state_sdr_i,jtag_state_e1dr_i,
|
1474 |
|
|
jtag_state_pdr_i,jtag_state_e2dr_i,
|
1475 |
|
|
jtag_state_udr_i,jtag_state_irs_i,
|
1476 |
|
|
jtag_state_cir_i,jtag_state_sir_i,
|
1477 |
|
|
jtag_state_e1ir_i,jtag_state_pir_i,
|
1478 |
|
|
jtag_state_e2ir_i,jtag_state_uir_i,
|
1479 |
|
|
jtag_usr1_i);
|
1480 |
|
|
|
1481 |
|
|
// the HUB
|
1482 |
|
|
dummy_hub hub (jtag_tck_i,jtag_tdi_i,jtag_tms_i,jtag_usr1_i,
|
1483 |
|
|
jtag_state_tlr_i,jtag_state_rti_i,jtag_state_drs_i,
|
1484 |
|
|
jtag_state_cdr_i,jtag_state_sdr_i,jtag_state_e1dr_i,
|
1485 |
|
|
jtag_state_pdr_i,jtag_state_e2dr_i,jtag_state_udr_i,
|
1486 |
|
|
jtag_state_irs_i,jtag_state_cir_i,jtag_state_sir_i,
|
1487 |
|
|
jtag_state_e1ir_i,jtag_state_pir_i,jtag_state_e2ir_i,
|
1488 |
|
|
jtag_state_uir_i,tdo,ir_out,jtag_tdo_i,tck,tdi,tms,
|
1489 |
|
|
jtag_state_tlr,jtag_state_rti,jtag_state_sdrs,jtag_state_cdr,
|
1490 |
|
|
jtag_state_sdr,jtag_state_e1dr,jtag_state_pdr,jtag_state_e2dr,
|
1491 |
|
|
jtag_state_udr,jtag_state_sirs,jtag_state_cir,jtag_state_sir,
|
1492 |
|
|
jtag_state_e1ir,jtag_state_pir,jtag_state_e2ir,jtag_state_uir,
|
1493 |
|
|
virtual_state_cdr,virtual_state_sdr,virtual_state_e1dr,
|
1494 |
|
|
virtual_state_pdr,virtual_state_e2dr,virtual_state_udr,
|
1495 |
|
|
virtual_state_cir,virtual_state_uir,ir_in);
|
1496 |
|
|
|
1497 |
|
|
endmodule
|
1498 |
|
|
// END OF MODULE
|
1499 |
|
|
|
1500 |
|
|
|
1501 |
|
|
|
1502 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
1503 |
|
|
//
|
1504 |
|
|
// Module Name : scfifo
|
1505 |
|
|
//
|
1506 |
|
|
// Description : Single Clock FIFO
|
1507 |
|
|
//
|
1508 |
|
|
// Limitation :
|
1509 |
|
|
//
|
1510 |
|
|
// Results expected:
|
1511 |
|
|
//
|
1512 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
1513 |
|
|
|
1514 |
|
|
// BEGINNING OF MODULE
|
1515 |
|
|
`timescale 1 ps / 1 ps
|
1516 |
|
|
|
1517 |
|
|
// MODULE DECLARATION
|
1518 |
|
|
module scfifo ( data,
|
1519 |
|
|
clock,
|
1520 |
|
|
wrreq,
|
1521 |
|
|
rdreq,
|
1522 |
|
|
aclr,
|
1523 |
|
|
sclr,
|
1524 |
|
|
q,
|
1525 |
|
|
usedw,
|
1526 |
|
|
full,
|
1527 |
|
|
empty,
|
1528 |
|
|
almost_full,
|
1529 |
|
|
almost_empty);
|
1530 |
|
|
|
1531 |
|
|
// GLOBAL PARAMETER DECLARATION
|
1532 |
|
|
parameter lpm_width = 1;
|
1533 |
|
|
parameter lpm_widthu = 1;
|
1534 |
|
|
parameter lpm_numwords = 2;
|
1535 |
|
|
parameter lpm_showahead = "OFF";
|
1536 |
|
|
parameter lpm_type = "scfifo";
|
1537 |
|
|
parameter lpm_hint = "USE_EAB=ON";
|
1538 |
|
|
parameter intended_device_family = "Stratix";
|
1539 |
|
|
parameter underflow_checking = "ON";
|
1540 |
|
|
parameter overflow_checking = "ON";
|
1541 |
|
|
parameter allow_rwcycle_when_full = "OFF";
|
1542 |
|
|
parameter use_eab = "ON";
|
1543 |
|
|
parameter add_ram_output_register = "OFF";
|
1544 |
|
|
parameter almost_full_value = 0;
|
1545 |
|
|
parameter almost_empty_value = 0;
|
1546 |
|
|
parameter maximum_depth = 0;
|
1547 |
|
|
|
1548 |
|
|
// LOCAL_PARAMETERS_BEGIN
|
1549 |
|
|
|
1550 |
|
|
parameter showahead_area = ((lpm_showahead == "ON") && (add_ram_output_register == "OFF"));
|
1551 |
|
|
parameter showahead_speed = ((lpm_showahead == "ON") && (add_ram_output_register == "ON"));
|
1552 |
|
|
parameter legacy_speed = ((lpm_showahead == "OFF") && (add_ram_output_register == "ON"));
|
1553 |
|
|
|
1554 |
|
|
// LOCAL_PARAMETERS_END
|
1555 |
|
|
|
1556 |
|
|
// INPUT PORT DECLARATION
|
1557 |
|
|
input [lpm_width-1:0] data;
|
1558 |
|
|
input clock;
|
1559 |
|
|
input wrreq;
|
1560 |
|
|
input rdreq;
|
1561 |
|
|
input aclr;
|
1562 |
|
|
input sclr;
|
1563 |
|
|
|
1564 |
|
|
// OUTPUT PORT DECLARATION
|
1565 |
|
|
output [lpm_width-1:0] q;
|
1566 |
|
|
output [lpm_widthu-1:0] usedw;
|
1567 |
|
|
output full;
|
1568 |
|
|
output empty;
|
1569 |
|
|
output almost_full;
|
1570 |
|
|
output almost_empty;
|
1571 |
|
|
|
1572 |
|
|
// INTERNAL REGISTERS DECLARATION
|
1573 |
|
|
reg [lpm_width-1:0] mem_data [(1<<lpm_widthu):0];
|
1574 |
|
|
reg [lpm_widthu-1:0] count_id;
|
1575 |
|
|
reg [lpm_widthu-1:0] read_id;
|
1576 |
|
|
reg [lpm_widthu-1:0] write_id;
|
1577 |
|
|
|
1578 |
|
|
wire valid_rreq;
|
1579 |
|
|
reg valid_wreq;
|
1580 |
|
|
reg write_flag;
|
1581 |
|
|
reg full_flag;
|
1582 |
|
|
reg empty_flag;
|
1583 |
|
|
reg almost_full_flag;
|
1584 |
|
|
reg almost_empty_flag;
|
1585 |
|
|
reg [lpm_width-1:0] tmp_q;
|
1586 |
|
|
reg stratix_family;
|
1587 |
|
|
reg set_q_to_x;
|
1588 |
|
|
reg set_q_to_x_by_empty;
|
1589 |
|
|
|
1590 |
|
|
reg [lpm_widthu-1:0] write_latency1;
|
1591 |
|
|
reg [lpm_widthu-1:0] write_latency2;
|
1592 |
|
|
reg [lpm_widthu-1:0] write_latency3;
|
1593 |
|
|
integer wrt_count;
|
1594 |
|
|
|
1595 |
|
|
reg empty_latency1;
|
1596 |
|
|
reg empty_latency2;
|
1597 |
|
|
|
1598 |
|
|
reg [(1<<lpm_widthu)-1:0] data_ready;
|
1599 |
|
|
reg [(1<<lpm_widthu)-1:0] data_shown;
|
1600 |
|
|
|
1601 |
|
|
// INTERNAL TRI DECLARATION
|
1602 |
|
|
tri0 aclr;
|
1603 |
|
|
|
1604 |
|
|
// LOCAL INTEGER DECLARATION
|
1605 |
|
|
integer i;
|
1606 |
|
|
|
1607 |
|
|
// COMPONENT INSTANTIATIONS
|
1608 |
|
|
ALTERA_DEVICE_FAMILIES dev ();
|
1609 |
|
|
|
1610 |
|
|
// INITIAL CONSTRUCT BLOCK
|
1611 |
|
|
initial
|
1612 |
|
|
begin
|
1613 |
|
|
|
1614 |
|
|
stratix_family = (dev.FEATURE_FAMILY_STRATIX(intended_device_family));
|
1615 |
|
|
if (lpm_width <= 0)
|
1616 |
|
|
begin
|
1617 |
|
|
$display ("Error! LPM_WIDTH must be greater than 0.");
|
1618 |
|
|
$display ("Time: %0t Instance: %m", $time);
|
1619 |
|
|
end
|
1620 |
|
|
if ((lpm_widthu !=1) && (lpm_numwords > (1 << lpm_widthu)))
|
1621 |
|
|
begin
|
1622 |
|
|
$display ("Error! LPM_NUMWORDS must equal to the ceiling of log2(LPM_WIDTHU).");
|
1623 |
|
|
$display ("Time: %0t Instance: %m", $time);
|
1624 |
|
|
end
|
1625 |
|
|
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
|
1626 |
|
|
begin
|
1627 |
|
|
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
|
1628 |
|
|
$display ("Time: %0t Instance: %m", $time);
|
1629 |
|
|
end
|
1630 |
|
|
if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF"))
|
1631 |
|
|
begin
|
1632 |
|
|
$display ("Error! add_ram_output_register must be ON or OFF.");
|
1633 |
|
|
$display ("Time: %0t Instance: %m", $time);
|
1634 |
|
|
end
|
1635 |
|
|
for (i = 0; i < (1<<lpm_widthu); i = i + 1)
|
1636 |
|
|
begin
|
1637 |
|
|
if (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family))
|
1638 |
|
|
mem_data[i] <= {lpm_width{1'b0}};
|
1639 |
|
|
else if (dev.FEATURE_FAMILY_STRATIX(intended_device_family))
|
1640 |
|
|
begin
|
1641 |
|
|
if ((add_ram_output_register == "ON") || (use_eab == "OFF"))
|
1642 |
|
|
mem_data[i] <= {lpm_width{1'b0}};
|
1643 |
|
|
else
|
1644 |
|
|
mem_data[i] <= {lpm_width{1'bx}};
|
1645 |
|
|
end
|
1646 |
|
|
else
|
1647 |
|
|
mem_data[i] <= {lpm_width{1'b0}};
|
1648 |
|
|
end
|
1649 |
|
|
|
1650 |
|
|
if (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family))
|
1651 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1652 |
|
|
else if (dev.FEATURE_FAMILY_STRATIX(intended_device_family))
|
1653 |
|
|
begin
|
1654 |
|
|
if ((add_ram_output_register == "ON") || (use_eab == "OFF"))
|
1655 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1656 |
|
|
else
|
1657 |
|
|
tmp_q <= {lpm_width{1'bx}};
|
1658 |
|
|
end
|
1659 |
|
|
else
|
1660 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1661 |
|
|
|
1662 |
|
|
write_flag <= 1'b0;
|
1663 |
|
|
count_id <= 0;
|
1664 |
|
|
read_id <= 0;
|
1665 |
|
|
write_id <= 0;
|
1666 |
|
|
full_flag <= 1'b0;
|
1667 |
|
|
empty_flag <= 1'b1;
|
1668 |
|
|
empty_latency1 <= 1'b1;
|
1669 |
|
|
empty_latency2 <= 1'b1;
|
1670 |
|
|
set_q_to_x <= 1'b0;
|
1671 |
|
|
set_q_to_x_by_empty <= 1'b0;
|
1672 |
|
|
wrt_count <= 0;
|
1673 |
|
|
|
1674 |
|
|
if (almost_full_value == 0)
|
1675 |
|
|
almost_full_flag <= 1'b1;
|
1676 |
|
|
else
|
1677 |
|
|
almost_full_flag <= 1'b0;
|
1678 |
|
|
|
1679 |
|
|
if (almost_empty_value == 0)
|
1680 |
|
|
almost_empty_flag <= 1'b0;
|
1681 |
|
|
else
|
1682 |
|
|
almost_empty_flag <= 1'b1;
|
1683 |
|
|
end
|
1684 |
|
|
|
1685 |
|
|
assign valid_rreq = (underflow_checking == "OFF")? rdreq : (rdreq && ~empty_flag);
|
1686 |
|
|
|
1687 |
|
|
always @(wrreq or rdreq or full_flag)
|
1688 |
|
|
begin
|
1689 |
|
|
if (overflow_checking == "OFF")
|
1690 |
|
|
valid_wreq = wrreq;
|
1691 |
|
|
else if (allow_rwcycle_when_full == "ON")
|
1692 |
|
|
valid_wreq = wrreq && (!full_flag || rdreq);
|
1693 |
|
|
else
|
1694 |
|
|
valid_wreq = wrreq && !full_flag;
|
1695 |
|
|
end
|
1696 |
|
|
|
1697 |
|
|
always @(posedge clock or posedge aclr)
|
1698 |
|
|
begin
|
1699 |
|
|
if (aclr)
|
1700 |
|
|
begin
|
1701 |
|
|
if (add_ram_output_register == "ON")
|
1702 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1703 |
|
|
else if ((lpm_showahead == "ON") && (use_eab == "ON"))
|
1704 |
|
|
begin
|
1705 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
1706 |
|
|
end
|
1707 |
|
|
else
|
1708 |
|
|
begin
|
1709 |
|
|
if (!stratix_family)
|
1710 |
|
|
begin
|
1711 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1712 |
|
|
end
|
1713 |
|
|
else
|
1714 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
1715 |
|
|
end
|
1716 |
|
|
|
1717 |
|
|
read_id <= 0;
|
1718 |
|
|
count_id <= 0;
|
1719 |
|
|
full_flag <= 1'b0;
|
1720 |
|
|
empty_flag <= 1'b1;
|
1721 |
|
|
empty_latency1 <= 1'b1;
|
1722 |
|
|
empty_latency2 <= 1'b1;
|
1723 |
|
|
set_q_to_x <= 1'b0;
|
1724 |
|
|
set_q_to_x_by_empty <= 1'b0;
|
1725 |
|
|
wrt_count <= 0;
|
1726 |
|
|
|
1727 |
|
|
if (almost_full_value > 0)
|
1728 |
|
|
almost_full_flag <= 1'b0;
|
1729 |
|
|
if (almost_empty_value > 0)
|
1730 |
|
|
almost_empty_flag <= 1'b1;
|
1731 |
|
|
|
1732 |
|
|
write_id <= 0;
|
1733 |
|
|
|
1734 |
|
|
if ((use_eab == "ON") && (stratix_family) && ((showahead_speed) || (showahead_area) || (legacy_speed)))
|
1735 |
|
|
begin
|
1736 |
|
|
write_latency1 <= 1'bx;
|
1737 |
|
|
write_latency2 <= 1'bx;
|
1738 |
|
|
data_shown <= {lpm_width{1'b0}};
|
1739 |
|
|
if (add_ram_output_register == "ON")
|
1740 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1741 |
|
|
else
|
1742 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
1743 |
|
|
end
|
1744 |
|
|
end
|
1745 |
|
|
else
|
1746 |
|
|
begin
|
1747 |
|
|
if (sclr)
|
1748 |
|
|
begin
|
1749 |
|
|
if (add_ram_output_register == "ON")
|
1750 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1751 |
|
|
else
|
1752 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
1753 |
|
|
|
1754 |
|
|
read_id <= 0;
|
1755 |
|
|
count_id <= 0;
|
1756 |
|
|
full_flag <= 1'b0;
|
1757 |
|
|
empty_flag <= 1'b1;
|
1758 |
|
|
empty_latency1 <= 1'b1;
|
1759 |
|
|
empty_latency2 <= 1'b1;
|
1760 |
|
|
set_q_to_x <= 1'b0;
|
1761 |
|
|
set_q_to_x_by_empty <= 1'b0;
|
1762 |
|
|
wrt_count <= 0;
|
1763 |
|
|
|
1764 |
|
|
if (almost_full_value > 0)
|
1765 |
|
|
almost_full_flag <= 1'b0;
|
1766 |
|
|
if (almost_empty_value > 0)
|
1767 |
|
|
almost_empty_flag <= 1'b1;
|
1768 |
|
|
|
1769 |
|
|
if (!stratix_family)
|
1770 |
|
|
begin
|
1771 |
|
|
if (valid_wreq)
|
1772 |
|
|
begin
|
1773 |
|
|
write_flag <= 1'b1;
|
1774 |
|
|
end
|
1775 |
|
|
else
|
1776 |
|
|
write_id <= 0;
|
1777 |
|
|
end
|
1778 |
|
|
else
|
1779 |
|
|
begin
|
1780 |
|
|
write_id <= 0;
|
1781 |
|
|
end
|
1782 |
|
|
|
1783 |
|
|
if ((use_eab == "ON") && (stratix_family) && ((showahead_speed) || (showahead_area) || (legacy_speed)))
|
1784 |
|
|
begin
|
1785 |
|
|
write_latency1 <= 1'bx;
|
1786 |
|
|
write_latency2 <= 1'bx;
|
1787 |
|
|
data_shown <= {lpm_width{1'b0}};
|
1788 |
|
|
if (add_ram_output_register == "ON")
|
1789 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1790 |
|
|
else
|
1791 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
1792 |
|
|
end
|
1793 |
|
|
end
|
1794 |
|
|
else
|
1795 |
|
|
begin
|
1796 |
|
|
//READ operation
|
1797 |
|
|
if (valid_rreq)
|
1798 |
|
|
begin
|
1799 |
|
|
if (!(set_q_to_x || set_q_to_x_by_empty))
|
1800 |
|
|
begin
|
1801 |
|
|
if (!valid_wreq)
|
1802 |
|
|
wrt_count <= wrt_count - 1;
|
1803 |
|
|
|
1804 |
|
|
if (!valid_wreq)
|
1805 |
|
|
begin
|
1806 |
|
|
full_flag <= 1'b0;
|
1807 |
|
|
|
1808 |
|
|
if (count_id <= 0)
|
1809 |
|
|
count_id <= {lpm_widthu{1'b1}};
|
1810 |
|
|
else
|
1811 |
|
|
count_id <= count_id - 1;
|
1812 |
|
|
end
|
1813 |
|
|
|
1814 |
|
|
if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area || legacy_speed))
|
1815 |
|
|
begin
|
1816 |
|
|
if ((wrt_count == 1 && valid_rreq && !valid_wreq) || ((wrt_count == 1 ) && valid_wreq && valid_rreq))
|
1817 |
|
|
begin
|
1818 |
|
|
empty_flag <= 1'b1;
|
1819 |
|
|
end
|
1820 |
|
|
else
|
1821 |
|
|
begin
|
1822 |
|
|
if (showahead_speed)
|
1823 |
|
|
begin
|
1824 |
|
|
if (data_shown[write_latency2] == 1'b0)
|
1825 |
|
|
begin
|
1826 |
|
|
empty_flag <= 1'b1;
|
1827 |
|
|
end
|
1828 |
|
|
end
|
1829 |
|
|
else if (showahead_area || legacy_speed)
|
1830 |
|
|
begin
|
1831 |
|
|
if (data_shown[write_latency1] == 1'b0)
|
1832 |
|
|
begin
|
1833 |
|
|
empty_flag <= 1'b1;
|
1834 |
|
|
end
|
1835 |
|
|
end
|
1836 |
|
|
end
|
1837 |
|
|
end
|
1838 |
|
|
else
|
1839 |
|
|
begin
|
1840 |
|
|
if (!valid_wreq)
|
1841 |
|
|
begin
|
1842 |
|
|
if ((count_id == 1) && !(full_flag))
|
1843 |
|
|
empty_flag <= 1'b1;
|
1844 |
|
|
end
|
1845 |
|
|
end
|
1846 |
|
|
|
1847 |
|
|
if (empty_flag)
|
1848 |
|
|
begin
|
1849 |
|
|
if (underflow_checking == "ON")
|
1850 |
|
|
begin
|
1851 |
|
|
if ((use_eab == "OFF") || (!stratix_family))
|
1852 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1853 |
|
|
end
|
1854 |
|
|
else
|
1855 |
|
|
begin
|
1856 |
|
|
set_q_to_x_by_empty <= 1'b1;
|
1857 |
|
|
$display ("Warning : Underflow occurred! Fifo output is unknown until the next reset is asserted.");
|
1858 |
|
|
$display ("Time: %0t Instance: %m", $time);
|
1859 |
|
|
end
|
1860 |
|
|
end
|
1861 |
|
|
else if (read_id >= ((1<<lpm_widthu) - 1))
|
1862 |
|
|
begin
|
1863 |
|
|
if (lpm_showahead == "ON")
|
1864 |
|
|
begin
|
1865 |
|
|
if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area))
|
1866 |
|
|
begin
|
1867 |
|
|
if (showahead_speed)
|
1868 |
|
|
begin
|
1869 |
|
|
if ((write_latency2 == 0) || (data_ready[0] == 1'b1))
|
1870 |
|
|
begin
|
1871 |
|
|
if (data_shown[0] == 1'b1)
|
1872 |
|
|
begin
|
1873 |
|
|
tmp_q <= mem_data[0];
|
1874 |
|
|
data_shown[0] <= 1'b0;
|
1875 |
|
|
data_ready[0] <= 1'b0;
|
1876 |
|
|
end
|
1877 |
|
|
end
|
1878 |
|
|
end
|
1879 |
|
|
else
|
1880 |
|
|
begin
|
1881 |
|
|
if ((count_id == 1) && !(full_flag))
|
1882 |
|
|
begin
|
1883 |
|
|
if (underflow_checking == "ON")
|
1884 |
|
|
begin
|
1885 |
|
|
if ((use_eab == "OFF") || (!stratix_family))
|
1886 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1887 |
|
|
end
|
1888 |
|
|
else
|
1889 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
1890 |
|
|
end
|
1891 |
|
|
else if ((write_latency1 == 0) || (data_ready[0] == 1'b1))
|
1892 |
|
|
begin
|
1893 |
|
|
if (data_shown[0] == 1'b1)
|
1894 |
|
|
begin
|
1895 |
|
|
tmp_q <= mem_data[0];
|
1896 |
|
|
data_shown[0] <= 1'b0;
|
1897 |
|
|
data_ready[0] <= 1'b0;
|
1898 |
|
|
end
|
1899 |
|
|
end
|
1900 |
|
|
end
|
1901 |
|
|
end
|
1902 |
|
|
else
|
1903 |
|
|
begin
|
1904 |
|
|
if ((count_id == 1) && !(full_flag))
|
1905 |
|
|
begin
|
1906 |
|
|
if (valid_wreq)
|
1907 |
|
|
tmp_q <= data;
|
1908 |
|
|
else
|
1909 |
|
|
if (underflow_checking == "ON")
|
1910 |
|
|
begin
|
1911 |
|
|
if ((use_eab == "OFF") || (!stratix_family))
|
1912 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1913 |
|
|
end
|
1914 |
|
|
else
|
1915 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
1916 |
|
|
end
|
1917 |
|
|
else
|
1918 |
|
|
tmp_q <= mem_data[0];
|
1919 |
|
|
end
|
1920 |
|
|
end
|
1921 |
|
|
else
|
1922 |
|
|
begin
|
1923 |
|
|
if ((use_eab == "ON") && stratix_family && legacy_speed)
|
1924 |
|
|
begin
|
1925 |
|
|
if ((write_latency1 == read_id) || (data_ready[read_id] == 1'b1))
|
1926 |
|
|
begin
|
1927 |
|
|
if (data_shown[read_id] == 1'b1)
|
1928 |
|
|
begin
|
1929 |
|
|
tmp_q <= mem_data[read_id];
|
1930 |
|
|
data_shown[read_id] <= 1'b0;
|
1931 |
|
|
data_ready[read_id] <= 1'b0;
|
1932 |
|
|
end
|
1933 |
|
|
end
|
1934 |
|
|
else
|
1935 |
|
|
begin
|
1936 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
1937 |
|
|
end
|
1938 |
|
|
end
|
1939 |
|
|
else
|
1940 |
|
|
tmp_q <= mem_data[read_id];
|
1941 |
|
|
end
|
1942 |
|
|
|
1943 |
|
|
read_id <= 0;
|
1944 |
|
|
end // end if (read_id >= ((1<<lpm_widthu) - 1))
|
1945 |
|
|
else
|
1946 |
|
|
begin
|
1947 |
|
|
if (lpm_showahead == "ON")
|
1948 |
|
|
begin
|
1949 |
|
|
if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area))
|
1950 |
|
|
begin
|
1951 |
|
|
if (showahead_speed)
|
1952 |
|
|
begin
|
1953 |
|
|
if ((write_latency2 == read_id+1) || (data_ready[read_id+1] == 1'b1))
|
1954 |
|
|
begin
|
1955 |
|
|
if (data_shown[read_id+1] == 1'b1)
|
1956 |
|
|
begin
|
1957 |
|
|
tmp_q <= mem_data[read_id + 1];
|
1958 |
|
|
data_shown[read_id+1] <= 1'b0;
|
1959 |
|
|
data_ready[read_id+1] <= 1'b0;
|
1960 |
|
|
end
|
1961 |
|
|
end
|
1962 |
|
|
end
|
1963 |
|
|
else
|
1964 |
|
|
begin
|
1965 |
|
|
if ((count_id == 1) && !(full_flag))
|
1966 |
|
|
begin
|
1967 |
|
|
if (underflow_checking == "ON")
|
1968 |
|
|
begin
|
1969 |
|
|
if ((use_eab == "OFF") || (!stratix_family))
|
1970 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
1971 |
|
|
end
|
1972 |
|
|
else
|
1973 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
1974 |
|
|
end
|
1975 |
|
|
else if ((write_latency1 == read_id+1) || (data_ready[read_id+1] == 1'b1))
|
1976 |
|
|
begin
|
1977 |
|
|
if (data_shown[read_id+1] == 1'b1)
|
1978 |
|
|
begin
|
1979 |
|
|
tmp_q <= mem_data[read_id + 1];
|
1980 |
|
|
data_shown[read_id+1] <= 1'b0;
|
1981 |
|
|
data_ready[read_id+1] <= 1'b0;
|
1982 |
|
|
end
|
1983 |
|
|
end
|
1984 |
|
|
end
|
1985 |
|
|
end
|
1986 |
|
|
else
|
1987 |
|
|
begin
|
1988 |
|
|
if ((count_id == 1) && !(full_flag))
|
1989 |
|
|
begin
|
1990 |
|
|
if ((use_eab == "OFF") && stratix_family)
|
1991 |
|
|
begin
|
1992 |
|
|
if (valid_wreq)
|
1993 |
|
|
begin
|
1994 |
|
|
tmp_q <= data;
|
1995 |
|
|
end
|
1996 |
|
|
else
|
1997 |
|
|
begin
|
1998 |
|
|
if (underflow_checking == "ON")
|
1999 |
|
|
begin
|
2000 |
|
|
if ((use_eab == "OFF") || (!stratix_family))
|
2001 |
|
|
tmp_q <= {lpm_width{1'b0}};
|
2002 |
|
|
end
|
2003 |
|
|
else
|
2004 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
2005 |
|
|
end
|
2006 |
|
|
end
|
2007 |
|
|
else
|
2008 |
|
|
begin
|
2009 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
2010 |
|
|
end
|
2011 |
|
|
end
|
2012 |
|
|
else
|
2013 |
|
|
tmp_q <= mem_data[read_id + 1];
|
2014 |
|
|
end
|
2015 |
|
|
end
|
2016 |
|
|
else
|
2017 |
|
|
begin
|
2018 |
|
|
if ((use_eab == "ON") && stratix_family && legacy_speed)
|
2019 |
|
|
begin
|
2020 |
|
|
if ((write_latency1 == read_id) || (data_ready[read_id] == 1'b1))
|
2021 |
|
|
begin
|
2022 |
|
|
if (data_shown[read_id] == 1'b1)
|
2023 |
|
|
begin
|
2024 |
|
|
tmp_q <= mem_data[read_id];
|
2025 |
|
|
data_shown[read_id] <= 1'b0;
|
2026 |
|
|
data_ready[read_id] <= 1'b0;
|
2027 |
|
|
end
|
2028 |
|
|
end
|
2029 |
|
|
else
|
2030 |
|
|
begin
|
2031 |
|
|
tmp_q <= {lpm_width{1'bX}};
|
2032 |
|
|
end
|
2033 |
|
|
end
|
2034 |
|
|
else
|
2035 |
|
|
tmp_q <= mem_data[read_id];
|
2036 |
|
|
end
|
2037 |
|
|
|
2038 |
|
|
read_id <= read_id + 1;
|
2039 |
|
|
end
|
2040 |
|
|
end
|
2041 |
|
|
end
|
2042 |
|
|
|
2043 |
|
|
// WRITE operation
|
2044 |
|
|
if (valid_wreq)
|
2045 |
|
|
begin
|
2046 |
|
|
if (!(set_q_to_x || set_q_to_x_by_empty))
|
2047 |
|
|
begin
|
2048 |
|
|
if (full_flag && (overflow_checking == "OFF"))
|
2049 |
|
|
begin
|
2050 |
|
|
set_q_to_x <= 1'b1;
|
2051 |
|
|
$display ("Warning : Overflow occurred! Fifo output is unknown until the next reset is asserted.");
|
2052 |
|
|
$display ("Time: %0t Instance: %m", $time);
|
2053 |
|
|
end
|
2054 |
|
|
else
|
2055 |
|
|
begin
|
2056 |
|
|
mem_data[write_id] <= data;
|
2057 |
|
|
write_flag <= 1'b1;
|
2058 |
|
|
|
2059 |
|
|
if (!((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area || legacy_speed)))
|
2060 |
|
|
begin
|
2061 |
|
|
empty_flag <= 1'b0;
|
2062 |
|
|
end
|
2063 |
|
|
else
|
2064 |
|
|
begin
|
2065 |
|
|
empty_latency1 <= 1'b0;
|
2066 |
|
|
end
|
2067 |
|
|
|
2068 |
|
|
if (!valid_rreq)
|
2069 |
|
|
wrt_count <= wrt_count + 1;
|
2070 |
|
|
|
2071 |
|
|
if (!valid_rreq)
|
2072 |
|
|
begin
|
2073 |
|
|
if (count_id >= (1 << lpm_widthu) - 1)
|
2074 |
|
|
count_id <= 0;
|
2075 |
|
|
else
|
2076 |
|
|
count_id <= count_id + 1;
|
2077 |
|
|
end
|
2078 |
|
|
else
|
2079 |
|
|
begin
|
2080 |
|
|
if (allow_rwcycle_when_full == "OFF")
|
2081 |
|
|
full_flag <= 1'b0;
|
2082 |
|
|
end
|
2083 |
|
|
|
2084 |
|
|
if (!(stratix_family) || (stratix_family && !(showahead_speed || showahead_area || legacy_speed)))
|
2085 |
|
|
begin
|
2086 |
|
|
if (!valid_rreq)
|
2087 |
|
|
if ((count_id == lpm_numwords - 1) && (empty_flag == 1'b0))
|
2088 |
|
|
full_flag <= 1'b1;
|
2089 |
|
|
end
|
2090 |
|
|
else
|
2091 |
|
|
begin
|
2092 |
|
|
if (!valid_rreq)
|
2093 |
|
|
if (count_id == lpm_numwords - 1)
|
2094 |
|
|
full_flag <= 1'b1;
|
2095 |
|
|
end
|
2096 |
|
|
|
2097 |
|
|
if (lpm_showahead == "ON")
|
2098 |
|
|
begin
|
2099 |
|
|
if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area))
|
2100 |
|
|
begin
|
2101 |
|
|
write_latency1 <= write_id;
|
2102 |
|
|
data_shown[write_id] <= 1'b1;
|
2103 |
|
|
data_ready[write_id] <= 1'bx;
|
2104 |
|
|
end
|
2105 |
|
|
else
|
2106 |
|
|
begin
|
2107 |
|
|
if ((use_eab == "OFF") && stratix_family && (count_id == 0) && (!full_flag))
|
2108 |
|
|
begin
|
2109 |
|
|
tmp_q <= data;
|
2110 |
|
|
end
|
2111 |
|
|
else
|
2112 |
|
|
begin
|
2113 |
|
|
if ((!empty_flag) && (!valid_rreq))
|
2114 |
|
|
begin
|
2115 |
|
|
tmp_q <= mem_data[read_id];
|
2116 |
|
|
end
|
2117 |
|
|
end
|
2118 |
|
|
end
|
2119 |
|
|
end
|
2120 |
|
|
else
|
2121 |
|
|
begin
|
2122 |
|
|
if ((use_eab == "ON") && stratix_family && legacy_speed)
|
2123 |
|
|
begin
|
2124 |
|
|
write_latency1 <= write_id;
|
2125 |
|
|
data_shown[write_id] <= 1'b1;
|
2126 |
|
|
data_ready[write_id] <= 1'bx;
|
2127 |
|
|
end
|
2128 |
|
|
end
|
2129 |
|
|
end
|
2130 |
|
|
end
|
2131 |
|
|
end
|
2132 |
|
|
|
2133 |
|
|
if (almost_full_value == 0)
|
2134 |
|
|
almost_full_flag <= 1'b1;
|
2135 |
|
|
else if (lpm_numwords > almost_full_value)
|
2136 |
|
|
begin
|
2137 |
|
|
if (almost_full_flag)
|
2138 |
|
|
begin
|
2139 |
|
|
if ((count_id == almost_full_value) && !wrreq && rdreq)
|
2140 |
|
|
almost_full_flag <= 1'b0;
|
2141 |
|
|
end
|
2142 |
|
|
else
|
2143 |
|
|
begin
|
2144 |
|
|
if ((almost_full_value == 1) && (count_id == 0) && wrreq)
|
2145 |
|
|
almost_full_flag <= 1'b1;
|
2146 |
|
|
else if ((almost_full_value > 1) && (count_id == almost_full_value - 1)
|
2147 |
|
|
&& wrreq && !rdreq)
|
2148 |
|
|
almost_full_flag <= 1'b1;
|
2149 |
|
|
end
|
2150 |
|
|
end
|
2151 |
|
|
|
2152 |
|
|
if (almost_empty_value == 0)
|
2153 |
|
|
almost_empty_flag <= 1'b0;
|
2154 |
|
|
else if (lpm_numwords > almost_empty_value)
|
2155 |
|
|
begin
|
2156 |
|
|
if (almost_empty_flag)
|
2157 |
|
|
begin
|
2158 |
|
|
if ((almost_empty_value == 1) && (count_id == 0) && wrreq)
|
2159 |
|
|
almost_empty_flag <= 1'b0;
|
2160 |
|
|
else if ((almost_empty_value > 1) && (count_id == almost_empty_value - 1)
|
2161 |
|
|
&& wrreq && !rdreq)
|
2162 |
|
|
almost_empty_flag <= 1'b0;
|
2163 |
|
|
end
|
2164 |
|
|
else
|
2165 |
|
|
begin
|
2166 |
|
|
if ((count_id == almost_empty_value) && !wrreq && rdreq)
|
2167 |
|
|
almost_empty_flag <= 1'b1;
|
2168 |
|
|
end
|
2169 |
|
|
end
|
2170 |
|
|
end
|
2171 |
|
|
|
2172 |
|
|
if ((use_eab == "ON") && stratix_family)
|
2173 |
|
|
begin
|
2174 |
|
|
if (showahead_speed)
|
2175 |
|
|
begin
|
2176 |
|
|
write_latency2 <= write_latency1;
|
2177 |
|
|
write_latency3 <= write_latency2;
|
2178 |
|
|
if (write_latency3 !== write_latency2)
|
2179 |
|
|
data_ready[write_latency2] <= 1'b1;
|
2180 |
|
|
|
2181 |
|
|
empty_latency2 <= empty_latency1;
|
2182 |
|
|
|
2183 |
|
|
if (data_shown[write_latency2]==1'b1)
|
2184 |
|
|
begin
|
2185 |
|
|
if ((read_id == write_latency2) || aclr || sclr)
|
2186 |
|
|
begin
|
2187 |
|
|
if (!(aclr === 1'b1) && !(sclr === 1'b1))
|
2188 |
|
|
begin
|
2189 |
|
|
if (write_latency2 !== 1'bx)
|
2190 |
|
|
begin
|
2191 |
|
|
tmp_q <= mem_data[write_latency2];
|
2192 |
|
|
data_shown[write_latency2] <= 1'b0;
|
2193 |
|
|
data_ready[write_latency2] <= 1'b0;
|
2194 |
|
|
|
2195 |
|
|
if (!valid_rreq)
|
2196 |
|
|
empty_flag <= empty_latency2;
|
2197 |
|
|
end
|
2198 |
|
|
end
|
2199 |
|
|
end
|
2200 |
|
|
end
|
2201 |
|
|
end
|
2202 |
|
|
else if (showahead_area)
|
2203 |
|
|
begin
|
2204 |
|
|
write_latency2 <= write_latency1;
|
2205 |
|
|
if (write_latency2 !== write_latency1)
|
2206 |
|
|
data_ready[write_latency1] <= 1'b1;
|
2207 |
|
|
|
2208 |
|
|
if (data_shown[write_latency1]==1'b1)
|
2209 |
|
|
begin
|
2210 |
|
|
if ((read_id == write_latency1) || aclr || sclr)
|
2211 |
|
|
begin
|
2212 |
|
|
if (!(aclr === 1'b1) && !(sclr === 1'b1))
|
2213 |
|
|
begin
|
2214 |
|
|
if (write_latency1 !== 1'bx)
|
2215 |
|
|
begin
|
2216 |
|
|
tmp_q <= mem_data[write_latency1];
|
2217 |
|
|
data_shown[write_latency1] <= 1'b0;
|
2218 |
|
|
data_ready[write_latency1] <= 1'b0;
|
2219 |
|
|
|
2220 |
|
|
if (!valid_rreq)
|
2221 |
|
|
begin
|
2222 |
|
|
empty_flag <= empty_latency1;
|
2223 |
|
|
end
|
2224 |
|
|
end
|
2225 |
|
|
end
|
2226 |
|
|
end
|
2227 |
|
|
end
|
2228 |
|
|
end
|
2229 |
|
|
else
|
2230 |
|
|
begin
|
2231 |
|
|
if (legacy_speed)
|
2232 |
|
|
begin
|
2233 |
|
|
write_latency2 <= write_latency1;
|
2234 |
|
|
if (write_latency2 !== write_latency1)
|
2235 |
|
|
data_ready[write_latency1] <= 1'b1;
|
2236 |
|
|
|
2237 |
|
|
empty_flag <= empty_latency1;
|
2238 |
|
|
|
2239 |
|
|
if ((wrt_count == 1 && !valid_wreq && valid_rreq) || aclr || sclr)
|
2240 |
|
|
begin
|
2241 |
|
|
empty_flag <= 1'b1;
|
2242 |
|
|
empty_latency1 <= 1'b1;
|
2243 |
|
|
end
|
2244 |
|
|
else
|
2245 |
|
|
begin
|
2246 |
|
|
if ((wrt_count == 1) && valid_wreq && valid_rreq)
|
2247 |
|
|
begin
|
2248 |
|
|
empty_flag <= 1'b1;
|
2249 |
|
|
end
|
2250 |
|
|
end
|
2251 |
|
|
end
|
2252 |
|
|
end
|
2253 |
|
|
end
|
2254 |
|
|
end
|
2255 |
|
|
end
|
2256 |
|
|
|
2257 |
|
|
always @(negedge clock)
|
2258 |
|
|
begin
|
2259 |
|
|
if (write_flag)
|
2260 |
|
|
begin
|
2261 |
|
|
write_flag <= 1'b0;
|
2262 |
|
|
|
2263 |
|
|
if (sclr || aclr || (write_id >= ((1 << lpm_widthu) - 1)))
|
2264 |
|
|
write_id <= 0;
|
2265 |
|
|
else
|
2266 |
|
|
write_id <= write_id + 1;
|
2267 |
|
|
end
|
2268 |
|
|
|
2269 |
|
|
if (!(stratix_family))
|
2270 |
|
|
begin
|
2271 |
|
|
if (!empty)
|
2272 |
|
|
begin
|
2273 |
|
|
if ((lpm_showahead == "ON") && ($time > 0))
|
2274 |
|
|
tmp_q <= mem_data[read_id];
|
2275 |
|
|
end
|
2276 |
|
|
end
|
2277 |
|
|
end
|
2278 |
|
|
|
2279 |
|
|
always @(full_flag)
|
2280 |
|
|
begin
|
2281 |
|
|
if (lpm_numwords == almost_full_value)
|
2282 |
|
|
if (full_flag)
|
2283 |
|
|
almost_full_flag = 1'b1;
|
2284 |
|
|
else
|
2285 |
|
|
almost_full_flag = 1'b0;
|
2286 |
|
|
|
2287 |
|
|
if (lpm_numwords == almost_empty_value)
|
2288 |
|
|
if (full_flag)
|
2289 |
|
|
almost_empty_flag = 1'b0;
|
2290 |
|
|
else
|
2291 |
|
|
almost_empty_flag = 1'b1;
|
2292 |
|
|
end
|
2293 |
|
|
|
2294 |
|
|
// CONTINOUS ASSIGNMENT
|
2295 |
|
|
assign q = (set_q_to_x || set_q_to_x_by_empty)? {lpm_width{1'bX}} : tmp_q;
|
2296 |
|
|
assign full = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : full_flag;
|
2297 |
|
|
assign empty = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : empty_flag;
|
2298 |
|
|
assign usedw = (set_q_to_x || set_q_to_x_by_empty)? {lpm_widthu{1'bX}} : count_id;
|
2299 |
|
|
assign almost_full = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : almost_full_flag;
|
2300 |
|
|
assign almost_empty = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : almost_empty_flag;
|
2301 |
|
|
|
2302 |
|
|
endmodule // scfifo
|
2303 |
|
|
// END OF MODULE
|
2304 |
|
|
|
2305 |
|
|
|
2306 |
|
|
|
2307 |
|
|
//START_MODULE_NAME------------------------------------------------------------
|
2308 |
|
|
//
|
2309 |
|
|
// Module Name : ALTERA_DEVICE_FAMILIES
|
2310 |
|
|
//
|
2311 |
|
|
// Description : Common Altera device families comparison
|
2312 |
|
|
//
|
2313 |
|
|
// Limitation :
|
2314 |
|
|
//
|
2315 |
|
|
// Results expected:
|
2316 |
|
|
//
|
2317 |
|
|
//END_MODULE_NAME--------------------------------------------------------------
|
2318 |
|
|
|
2319 |
|
|
// BEGINNING OF MODULE
|
2320 |
|
|
`timescale 1 ps / 1 ps
|
2321 |
|
|
|
2322 |
|
|
// MODULE DECLARATION
|
2323 |
|
|
module ALTERA_DEVICE_FAMILIES;
|
2324 |
|
|
|
2325 |
|
|
function IS_FAMILY_STRATIX;
|
2326 |
|
|
input[8*20:1] device;
|
2327 |
|
|
reg is_stratix;
|
2328 |
|
|
begin
|
2329 |
|
|
if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
|
2330 |
|
|
is_stratix = 1;
|
2331 |
|
|
else
|
2332 |
|
|
is_stratix = 0;
|
2333 |
|
|
|
2334 |
|
|
IS_FAMILY_STRATIX = is_stratix;
|
2335 |
|
|
end
|
2336 |
|
|
endfunction //IS_FAMILY_STRATIX
|
2337 |
|
|
|
2338 |
|
|
function IS_FAMILY_STRATIXGX;
|
2339 |
|
|
input[8*20:1] device;
|
2340 |
|
|
reg is_stratixgx;
|
2341 |
|
|
begin
|
2342 |
|
|
if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
|
2343 |
|
|
is_stratixgx = 1;
|
2344 |
|
|
else
|
2345 |
|
|
is_stratixgx = 0;
|
2346 |
|
|
|
2347 |
|
|
IS_FAMILY_STRATIXGX = is_stratixgx;
|
2348 |
|
|
end
|
2349 |
|
|
endfunction //IS_FAMILY_STRATIXGX
|
2350 |
|
|
|
2351 |
|
|
function IS_FAMILY_CYCLONE;
|
2352 |
|
|
input[8*20:1] device;
|
2353 |
|
|
reg is_cyclone;
|
2354 |
|
|
begin
|
2355 |
|
|
if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
|
2356 |
|
|
is_cyclone = 1;
|
2357 |
|
|
else
|
2358 |
|
|
is_cyclone = 0;
|
2359 |
|
|
|
2360 |
|
|
IS_FAMILY_CYCLONE = is_cyclone;
|
2361 |
|
|
end
|
2362 |
|
|
endfunction //IS_FAMILY_CYCLONE
|
2363 |
|
|
|
2364 |
|
|
function IS_FAMILY_MAXII;
|
2365 |
|
|
input[8*20:1] device;
|
2366 |
|
|
reg is_maxii;
|
2367 |
|
|
begin
|
2368 |
|
|
if ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
|
2369 |
|
|
is_maxii = 1;
|
2370 |
|
|
else
|
2371 |
|
|
is_maxii = 0;
|
2372 |
|
|
|
2373 |
|
|
IS_FAMILY_MAXII = is_maxii;
|
2374 |
|
|
end
|
2375 |
|
|
endfunction //IS_FAMILY_MAXII
|
2376 |
|
|
|
2377 |
|
|
function IS_FAMILY_STRATIXII;
|
2378 |
|
|
input[8*20:1] device;
|
2379 |
|
|
reg is_stratixii;
|
2380 |
|
|
begin
|
2381 |
|
|
if ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
|
2382 |
|
|
is_stratixii = 1;
|
2383 |
|
|
else
|
2384 |
|
|
is_stratixii = 0;
|
2385 |
|
|
|
2386 |
|
|
IS_FAMILY_STRATIXII = is_stratixii;
|
2387 |
|
|
end
|
2388 |
|
|
endfunction //IS_FAMILY_STRATIXII
|
2389 |
|
|
|
2390 |
|
|
function IS_FAMILY_STRATIXIIGX;
|
2391 |
|
|
input[8*20:1] device;
|
2392 |
|
|
reg is_stratixiigx;
|
2393 |
|
|
begin
|
2394 |
|
|
if ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
|
2395 |
|
|
is_stratixiigx = 1;
|
2396 |
|
|
else
|
2397 |
|
|
is_stratixiigx = 0;
|
2398 |
|
|
|
2399 |
|
|
IS_FAMILY_STRATIXIIGX = is_stratixiigx;
|
2400 |
|
|
end
|
2401 |
|
|
endfunction //IS_FAMILY_STRATIXIIGX
|
2402 |
|
|
|
2403 |
|
|
function IS_FAMILY_ARRIAGX;
|
2404 |
|
|
input[8*20:1] device;
|
2405 |
|
|
reg is_arriagx;
|
2406 |
|
|
begin
|
2407 |
|
|
if ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
|
2408 |
|
|
is_arriagx = 1;
|
2409 |
|
|
else
|
2410 |
|
|
is_arriagx = 0;
|
2411 |
|
|
|
2412 |
|
|
IS_FAMILY_ARRIAGX = is_arriagx;
|
2413 |
|
|
end
|
2414 |
|
|
endfunction //IS_FAMILY_ARRIAGX
|
2415 |
|
|
|
2416 |
|
|
function IS_FAMILY_CYCLONEII;
|
2417 |
|
|
input[8*20:1] device;
|
2418 |
|
|
reg is_cycloneii;
|
2419 |
|
|
begin
|
2420 |
|
|
if ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
|
2421 |
|
|
is_cycloneii = 1;
|
2422 |
|
|
else
|
2423 |
|
|
is_cycloneii = 0;
|
2424 |
|
|
|
2425 |
|
|
IS_FAMILY_CYCLONEII = is_cycloneii;
|
2426 |
|
|
end
|
2427 |
|
|
endfunction //IS_FAMILY_CYCLONEII
|
2428 |
|
|
|
2429 |
|
|
function IS_FAMILY_HARDCOPYII;
|
2430 |
|
|
input[8*20:1] device;
|
2431 |
|
|
reg is_hardcopyii;
|
2432 |
|
|
begin
|
2433 |
|
|
if ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
|
2434 |
|
|
is_hardcopyii = 1;
|
2435 |
|
|
else
|
2436 |
|
|
is_hardcopyii = 0;
|
2437 |
|
|
|
2438 |
|
|
IS_FAMILY_HARDCOPYII = is_hardcopyii;
|
2439 |
|
|
end
|
2440 |
|
|
endfunction //IS_FAMILY_HARDCOPYII
|
2441 |
|
|
|
2442 |
|
|
function IS_FAMILY_STRATIXIII;
|
2443 |
|
|
input[8*20:1] device;
|
2444 |
|
|
reg is_stratixiii;
|
2445 |
|
|
begin
|
2446 |
|
|
if ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
|
2447 |
|
|
is_stratixiii = 1;
|
2448 |
|
|
else
|
2449 |
|
|
is_stratixiii = 0;
|
2450 |
|
|
|
2451 |
|
|
IS_FAMILY_STRATIXIII = is_stratixiii;
|
2452 |
|
|
end
|
2453 |
|
|
endfunction //IS_FAMILY_STRATIXIII
|
2454 |
|
|
|
2455 |
|
|
function IS_FAMILY_CYCLONEIII;
|
2456 |
|
|
input[8*20:1] device;
|
2457 |
|
|
reg is_cycloneiii;
|
2458 |
|
|
begin
|
2459 |
|
|
if ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
|
2460 |
|
|
is_cycloneiii = 1;
|
2461 |
|
|
else
|
2462 |
|
|
is_cycloneiii = 0;
|
2463 |
|
|
|
2464 |
|
|
IS_FAMILY_CYCLONEIII = is_cycloneiii;
|
2465 |
|
|
end
|
2466 |
|
|
endfunction //IS_FAMILY_CYCLONEIII
|
2467 |
|
|
|
2468 |
|
|
function IS_FAMILY_STRATIXIV;
|
2469 |
|
|
input[8*20:1] device;
|
2470 |
|
|
reg is_stratixiv;
|
2471 |
|
|
begin
|
2472 |
|
|
if ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
|
2473 |
|
|
is_stratixiv = 1;
|
2474 |
|
|
else
|
2475 |
|
|
is_stratixiv = 0;
|
2476 |
|
|
|
2477 |
|
|
IS_FAMILY_STRATIXIV = is_stratixiv;
|
2478 |
|
|
end
|
2479 |
|
|
endfunction //IS_FAMILY_STRATIXIV
|
2480 |
|
|
|
2481 |
|
|
function IS_FAMILY_ARRIAIIGX;
|
2482 |
|
|
input[8*20:1] device;
|
2483 |
|
|
reg is_arriaiigx;
|
2484 |
|
|
begin
|
2485 |
|
|
if ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
|
2486 |
|
|
is_arriaiigx = 1;
|
2487 |
|
|
else
|
2488 |
|
|
is_arriaiigx = 0;
|
2489 |
|
|
|
2490 |
|
|
IS_FAMILY_ARRIAIIGX = is_arriaiigx;
|
2491 |
|
|
end
|
2492 |
|
|
endfunction //IS_FAMILY_ARRIAIIGX
|
2493 |
|
|
|
2494 |
|
|
function IS_FAMILY_HARDCOPYIII;
|
2495 |
|
|
input[8*20:1] device;
|
2496 |
|
|
reg is_hardcopyiii;
|
2497 |
|
|
begin
|
2498 |
|
|
if ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
|
2499 |
|
|
is_hardcopyiii = 1;
|
2500 |
|
|
else
|
2501 |
|
|
is_hardcopyiii = 0;
|
2502 |
|
|
|
2503 |
|
|
IS_FAMILY_HARDCOPYIII = is_hardcopyiii;
|
2504 |
|
|
end
|
2505 |
|
|
endfunction //IS_FAMILY_HARDCOPYIII
|
2506 |
|
|
|
2507 |
|
|
function IS_FAMILY_HARDCOPYIV;
|
2508 |
|
|
input[8*20:1] device;
|
2509 |
|
|
reg is_hardcopyiv;
|
2510 |
|
|
begin
|
2511 |
|
|
if ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)"))
|
2512 |
|
|
is_hardcopyiv = 1;
|
2513 |
|
|
else
|
2514 |
|
|
is_hardcopyiv = 0;
|
2515 |
|
|
|
2516 |
|
|
IS_FAMILY_HARDCOPYIV = is_hardcopyiv;
|
2517 |
|
|
end
|
2518 |
|
|
endfunction //IS_FAMILY_HARDCOPYIV
|
2519 |
|
|
|
2520 |
|
|
function IS_FAMILY_CYCLONEIIILS;
|
2521 |
|
|
input[8*20:1] device;
|
2522 |
|
|
reg is_cycloneiiils;
|
2523 |
|
|
begin
|
2524 |
|
|
if ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
|
2525 |
|
|
is_cycloneiiils = 1;
|
2526 |
|
|
else
|
2527 |
|
|
is_cycloneiiils = 0;
|
2528 |
|
|
|
2529 |
|
|
IS_FAMILY_CYCLONEIIILS = is_cycloneiiils;
|
2530 |
|
|
end
|
2531 |
|
|
endfunction //IS_FAMILY_CYCLONEIIILS
|
2532 |
|
|
|
2533 |
|
|
function IS_FAMILY_CYCLONEIVGX;
|
2534 |
|
|
input[8*20:1] device;
|
2535 |
|
|
reg is_cycloneivgx;
|
2536 |
|
|
begin
|
2537 |
|
|
if ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray"))
|
2538 |
|
|
is_cycloneivgx = 1;
|
2539 |
|
|
else
|
2540 |
|
|
is_cycloneivgx = 0;
|
2541 |
|
|
|
2542 |
|
|
IS_FAMILY_CYCLONEIVGX = is_cycloneivgx;
|
2543 |
|
|
end
|
2544 |
|
|
endfunction //IS_FAMILY_CYCLONEIVGX
|
2545 |
|
|
|
2546 |
|
|
function IS_FAMILY_CYCLONEIVE;
|
2547 |
|
|
input[8*20:1] device;
|
2548 |
|
|
reg is_cycloneive;
|
2549 |
|
|
begin
|
2550 |
|
|
if ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive"))
|
2551 |
|
|
is_cycloneive = 1;
|
2552 |
|
|
else
|
2553 |
|
|
is_cycloneive = 0;
|
2554 |
|
|
|
2555 |
|
|
IS_FAMILY_CYCLONEIVE = is_cycloneive;
|
2556 |
|
|
end
|
2557 |
|
|
endfunction //IS_FAMILY_CYCLONEIVE
|
2558 |
|
|
|
2559 |
|
|
function IS_FAMILY_STRATIXV;
|
2560 |
|
|
input[8*20:1] device;
|
2561 |
|
|
reg is_stratixv;
|
2562 |
|
|
begin
|
2563 |
|
|
if ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)"))
|
2564 |
|
|
is_stratixv = 1;
|
2565 |
|
|
else
|
2566 |
|
|
is_stratixv = 0;
|
2567 |
|
|
|
2568 |
|
|
IS_FAMILY_STRATIXV = is_stratixv;
|
2569 |
|
|
end
|
2570 |
|
|
endfunction //IS_FAMILY_STRATIXV
|
2571 |
|
|
|
2572 |
|
|
function IS_FAMILY_ARRIAIIGZ;
|
2573 |
|
|
input[8*20:1] device;
|
2574 |
|
|
reg is_arriaiigz;
|
2575 |
|
|
begin
|
2576 |
|
|
if ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz"))
|
2577 |
|
|
is_arriaiigz = 1;
|
2578 |
|
|
else
|
2579 |
|
|
is_arriaiigz = 0;
|
2580 |
|
|
|
2581 |
|
|
IS_FAMILY_ARRIAIIGZ = is_arriaiigz;
|
2582 |
|
|
end
|
2583 |
|
|
endfunction //IS_FAMILY_ARRIAIIGZ
|
2584 |
|
|
|
2585 |
|
|
function IS_FAMILY_MAXV;
|
2586 |
|
|
input[8*20:1] device;
|
2587 |
|
|
reg is_maxv;
|
2588 |
|
|
begin
|
2589 |
|
|
if ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade"))
|
2590 |
|
|
is_maxv = 1;
|
2591 |
|
|
else
|
2592 |
|
|
is_maxv = 0;
|
2593 |
|
|
|
2594 |
|
|
IS_FAMILY_MAXV = is_maxv;
|
2595 |
|
|
end
|
2596 |
|
|
endfunction //IS_FAMILY_MAXV
|
2597 |
|
|
|
2598 |
|
|
function FEATURE_FAMILY_STRATIXGX;
|
2599 |
|
|
input[8*20:1] device;
|
2600 |
|
|
reg var_family_stratixgx;
|
2601 |
|
|
begin
|
2602 |
|
|
if (IS_FAMILY_STRATIXGX(device) )
|
2603 |
|
|
var_family_stratixgx = 1;
|
2604 |
|
|
else
|
2605 |
|
|
var_family_stratixgx = 0;
|
2606 |
|
|
|
2607 |
|
|
FEATURE_FAMILY_STRATIXGX = var_family_stratixgx;
|
2608 |
|
|
end
|
2609 |
|
|
endfunction //FEATURE_FAMILY_STRATIXGX
|
2610 |
|
|
|
2611 |
|
|
function FEATURE_FAMILY_CYCLONE;
|
2612 |
|
|
input[8*20:1] device;
|
2613 |
|
|
reg var_family_cyclone;
|
2614 |
|
|
begin
|
2615 |
|
|
if (IS_FAMILY_CYCLONE(device) )
|
2616 |
|
|
var_family_cyclone = 1;
|
2617 |
|
|
else
|
2618 |
|
|
var_family_cyclone = 0;
|
2619 |
|
|
|
2620 |
|
|
FEATURE_FAMILY_CYCLONE = var_family_cyclone;
|
2621 |
|
|
end
|
2622 |
|
|
endfunction //FEATURE_FAMILY_CYCLONE
|
2623 |
|
|
|
2624 |
|
|
function FEATURE_FAMILY_STRATIXIIGX;
|
2625 |
|
|
input[8*20:1] device;
|
2626 |
|
|
reg var_family_stratixiigx;
|
2627 |
|
|
begin
|
2628 |
|
|
if (IS_FAMILY_STRATIXIIGX(device) || IS_FAMILY_ARRIAGX(device) )
|
2629 |
|
|
var_family_stratixiigx = 1;
|
2630 |
|
|
else
|
2631 |
|
|
var_family_stratixiigx = 0;
|
2632 |
|
|
|
2633 |
|
|
FEATURE_FAMILY_STRATIXIIGX = var_family_stratixiigx;
|
2634 |
|
|
end
|
2635 |
|
|
endfunction //FEATURE_FAMILY_STRATIXIIGX
|
2636 |
|
|
|
2637 |
|
|
function FEATURE_FAMILY_STRATIXIII;
|
2638 |
|
|
input[8*20:1] device;
|
2639 |
|
|
reg var_family_stratixiii;
|
2640 |
|
|
begin
|
2641 |
|
|
if (IS_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_STRATIXIV(device) || IS_FAMILY_HARDCOPYIII(device) )
|
2642 |
|
|
var_family_stratixiii = 1;
|
2643 |
|
|
else
|
2644 |
|
|
var_family_stratixiii = 0;
|
2645 |
|
|
|
2646 |
|
|
FEATURE_FAMILY_STRATIXIII = var_family_stratixiii;
|
2647 |
|
|
end
|
2648 |
|
|
endfunction //FEATURE_FAMILY_STRATIXIII
|
2649 |
|
|
|
2650 |
|
|
function FEATURE_FAMILY_STRATIXV;
|
2651 |
|
|
input[8*20:1] device;
|
2652 |
|
|
reg var_family_stratixv;
|
2653 |
|
|
begin
|
2654 |
|
|
if (IS_FAMILY_STRATIXV(device) )
|
2655 |
|
|
var_family_stratixv = 1;
|
2656 |
|
|
else
|
2657 |
|
|
var_family_stratixv = 0;
|
2658 |
|
|
|
2659 |
|
|
FEATURE_FAMILY_STRATIXV = var_family_stratixv;
|
2660 |
|
|
end
|
2661 |
|
|
endfunction //FEATURE_FAMILY_STRATIXV
|
2662 |
|
|
|
2663 |
|
|
function FEATURE_FAMILY_STRATIXII;
|
2664 |
|
|
input[8*20:1] device;
|
2665 |
|
|
reg var_family_stratixii;
|
2666 |
|
|
begin
|
2667 |
|
|
if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) || FEATURE_FAMILY_STRATIXIII(device) )
|
2668 |
|
|
var_family_stratixii = 1;
|
2669 |
|
|
else
|
2670 |
|
|
var_family_stratixii = 0;
|
2671 |
|
|
|
2672 |
|
|
FEATURE_FAMILY_STRATIXII = var_family_stratixii;
|
2673 |
|
|
end
|
2674 |
|
|
endfunction //FEATURE_FAMILY_STRATIXII
|
2675 |
|
|
|
2676 |
|
|
function FEATURE_FAMILY_CYCLONEIVGX;
|
2677 |
|
|
input[8*20:1] device;
|
2678 |
|
|
reg var_family_cycloneivgx;
|
2679 |
|
|
begin
|
2680 |
|
|
if (IS_FAMILY_CYCLONEIVGX(device) || IS_FAMILY_CYCLONEIVGX(device) )
|
2681 |
|
|
var_family_cycloneivgx = 1;
|
2682 |
|
|
else
|
2683 |
|
|
var_family_cycloneivgx = 0;
|
2684 |
|
|
|
2685 |
|
|
FEATURE_FAMILY_CYCLONEIVGX = var_family_cycloneivgx;
|
2686 |
|
|
end
|
2687 |
|
|
endfunction //FEATURE_FAMILY_CYCLONEIVGX
|
2688 |
|
|
|
2689 |
|
|
function FEATURE_FAMILY_CYCLONEIVE;
|
2690 |
|
|
input[8*20:1] device;
|
2691 |
|
|
reg var_family_cycloneive;
|
2692 |
|
|
begin
|
2693 |
|
|
if (IS_FAMILY_CYCLONEIVE(device) )
|
2694 |
|
|
var_family_cycloneive = 1;
|
2695 |
|
|
else
|
2696 |
|
|
var_family_cycloneive = 0;
|
2697 |
|
|
|
2698 |
|
|
FEATURE_FAMILY_CYCLONEIVE = var_family_cycloneive;
|
2699 |
|
|
end
|
2700 |
|
|
endfunction //FEATURE_FAMILY_CYCLONEIVE
|
2701 |
|
|
|
2702 |
|
|
function FEATURE_FAMILY_CYCLONEIII;
|
2703 |
|
|
input[8*20:1] device;
|
2704 |
|
|
reg var_family_cycloneiii;
|
2705 |
|
|
begin
|
2706 |
|
|
if (IS_FAMILY_CYCLONEIII(device) || IS_FAMILY_CYCLONEIIILS(device) || FEATURE_FAMILY_CYCLONEIVGX(device) || FEATURE_FAMILY_CYCLONEIVE(device) )
|
2707 |
|
|
var_family_cycloneiii = 1;
|
2708 |
|
|
else
|
2709 |
|
|
var_family_cycloneiii = 0;
|
2710 |
|
|
|
2711 |
|
|
FEATURE_FAMILY_CYCLONEIII = var_family_cycloneiii;
|
2712 |
|
|
end
|
2713 |
|
|
endfunction //FEATURE_FAMILY_CYCLONEIII
|
2714 |
|
|
|
2715 |
|
|
function FEATURE_FAMILY_STRATIX_HC;
|
2716 |
|
|
input[8*20:1] device;
|
2717 |
|
|
reg var_family_stratix_hc;
|
2718 |
|
|
begin
|
2719 |
|
|
if ((device == "StratixHC") )
|
2720 |
|
|
var_family_stratix_hc = 1;
|
2721 |
|
|
else
|
2722 |
|
|
var_family_stratix_hc = 0;
|
2723 |
|
|
|
2724 |
|
|
FEATURE_FAMILY_STRATIX_HC = var_family_stratix_hc;
|
2725 |
|
|
end
|
2726 |
|
|
endfunction //FEATURE_FAMILY_STRATIX_HC
|
2727 |
|
|
|
2728 |
|
|
function FEATURE_FAMILY_STRATIX;
|
2729 |
|
|
input[8*20:1] device;
|
2730 |
|
|
reg var_family_stratix;
|
2731 |
|
|
begin
|
2732 |
|
|
if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || FEATURE_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_MAXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
|
2733 |
|
|
var_family_stratix = 1;
|
2734 |
|
|
else
|
2735 |
|
|
var_family_stratix = 0;
|
2736 |
|
|
|
2737 |
|
|
FEATURE_FAMILY_STRATIX = var_family_stratix;
|
2738 |
|
|
end
|
2739 |
|
|
endfunction //FEATURE_FAMILY_STRATIX
|
2740 |
|
|
|
2741 |
|
|
function FEATURE_FAMILY_MAXII;
|
2742 |
|
|
input[8*20:1] device;
|
2743 |
|
|
reg var_family_maxii;
|
2744 |
|
|
begin
|
2745 |
|
|
if (IS_FAMILY_MAXII(device) || FEATURE_FAMILY_MAXV(device) )
|
2746 |
|
|
var_family_maxii = 1;
|
2747 |
|
|
else
|
2748 |
|
|
var_family_maxii = 0;
|
2749 |
|
|
|
2750 |
|
|
FEATURE_FAMILY_MAXII = var_family_maxii;
|
2751 |
|
|
end
|
2752 |
|
|
endfunction //FEATURE_FAMILY_MAXII
|
2753 |
|
|
|
2754 |
|
|
function FEATURE_FAMILY_MAXV;
|
2755 |
|
|
input[8*20:1] device;
|
2756 |
|
|
reg var_family_maxv;
|
2757 |
|
|
begin
|
2758 |
|
|
if (IS_FAMILY_MAXV(device) )
|
2759 |
|
|
var_family_maxv = 1;
|
2760 |
|
|
else
|
2761 |
|
|
var_family_maxv = 0;
|
2762 |
|
|
|
2763 |
|
|
FEATURE_FAMILY_MAXV = var_family_maxv;
|
2764 |
|
|
end
|
2765 |
|
|
endfunction //FEATURE_FAMILY_MAXV
|
2766 |
|
|
|
2767 |
|
|
function FEATURE_FAMILY_CYCLONEII;
|
2768 |
|
|
input[8*20:1] device;
|
2769 |
|
|
reg var_family_cycloneii;
|
2770 |
|
|
begin
|
2771 |
|
|
if (IS_FAMILY_CYCLONEII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
|
2772 |
|
|
var_family_cycloneii = 1;
|
2773 |
|
|
else
|
2774 |
|
|
var_family_cycloneii = 0;
|
2775 |
|
|
|
2776 |
|
|
FEATURE_FAMILY_CYCLONEII = var_family_cycloneii;
|
2777 |
|
|
end
|
2778 |
|
|
endfunction //FEATURE_FAMILY_CYCLONEII
|
2779 |
|
|
|
2780 |
|
|
function FEATURE_FAMILY_STRATIXIV;
|
2781 |
|
|
input[8*20:1] device;
|
2782 |
|
|
reg var_family_stratixiv;
|
2783 |
|
|
begin
|
2784 |
|
|
if (IS_FAMILY_STRATIXIV(device) || IS_FAMILY_ARRIAIIGX(device) || IS_FAMILY_HARDCOPYIV(device) || FEATURE_FAMILY_STRATIXV(device) || FEATURE_FAMILY_ARRIAIIGZ(device) )
|
2785 |
|
|
var_family_stratixiv = 1;
|
2786 |
|
|
else
|
2787 |
|
|
var_family_stratixiv = 0;
|
2788 |
|
|
|
2789 |
|
|
FEATURE_FAMILY_STRATIXIV = var_family_stratixiv;
|
2790 |
|
|
end
|
2791 |
|
|
endfunction //FEATURE_FAMILY_STRATIXIV
|
2792 |
|
|
|
2793 |
|
|
function FEATURE_FAMILY_ARRIAIIGZ;
|
2794 |
|
|
input[8*20:1] device;
|
2795 |
|
|
reg var_family_arriaiigz;
|
2796 |
|
|
begin
|
2797 |
|
|
if (IS_FAMILY_ARRIAIIGZ(device) )
|
2798 |
|
|
var_family_arriaiigz = 1;
|
2799 |
|
|
else
|
2800 |
|
|
var_family_arriaiigz = 0;
|
2801 |
|
|
|
2802 |
|
|
FEATURE_FAMILY_ARRIAIIGZ = var_family_arriaiigz;
|
2803 |
|
|
end
|
2804 |
|
|
endfunction //FEATURE_FAMILY_ARRIAIIGZ
|
2805 |
|
|
|
2806 |
|
|
function FEATURE_FAMILY_ARRIAIIGX;
|
2807 |
|
|
input[8*20:1] device;
|
2808 |
|
|
reg var_family_arriaiigx;
|
2809 |
|
|
begin
|
2810 |
|
|
if (IS_FAMILY_ARRIAIIGX(device) )
|
2811 |
|
|
var_family_arriaiigx = 1;
|
2812 |
|
|
else
|
2813 |
|
|
var_family_arriaiigx = 0;
|
2814 |
|
|
|
2815 |
|
|
FEATURE_FAMILY_ARRIAIIGX = var_family_arriaiigx;
|
2816 |
|
|
end
|
2817 |
|
|
endfunction //FEATURE_FAMILY_ARRIAIIGX
|
2818 |
|
|
|
2819 |
|
|
function FEATURE_FAMILY_BASE_STRATIXII;
|
2820 |
|
|
input[8*20:1] device;
|
2821 |
|
|
reg var_family_base_stratixii;
|
2822 |
|
|
begin
|
2823 |
|
|
if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) )
|
2824 |
|
|
var_family_base_stratixii = 1;
|
2825 |
|
|
else
|
2826 |
|
|
var_family_base_stratixii = 0;
|
2827 |
|
|
|
2828 |
|
|
FEATURE_FAMILY_BASE_STRATIXII = var_family_base_stratixii;
|
2829 |
|
|
end
|
2830 |
|
|
endfunction //FEATURE_FAMILY_BASE_STRATIXII
|
2831 |
|
|
|
2832 |
|
|
function FEATURE_FAMILY_BASE_STRATIX;
|
2833 |
|
|
input[8*20:1] device;
|
2834 |
|
|
reg var_family_base_stratix;
|
2835 |
|
|
begin
|
2836 |
|
|
if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) )
|
2837 |
|
|
var_family_base_stratix = 1;
|
2838 |
|
|
else
|
2839 |
|
|
var_family_base_stratix = 0;
|
2840 |
|
|
|
2841 |
|
|
FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix;
|
2842 |
|
|
end
|
2843 |
|
|
endfunction //FEATURE_FAMILY_BASE_STRATIX
|
2844 |
|
|
|
2845 |
|
|
function FEATURE_FAMILY_BASE_CYCLONEII;
|
2846 |
|
|
input[8*20:1] device;
|
2847 |
|
|
reg var_family_base_cycloneii;
|
2848 |
|
|
begin
|
2849 |
|
|
if (IS_FAMILY_CYCLONEII(device) )
|
2850 |
|
|
var_family_base_cycloneii = 1;
|
2851 |
|
|
else
|
2852 |
|
|
var_family_base_cycloneii = 0;
|
2853 |
|
|
|
2854 |
|
|
FEATURE_FAMILY_BASE_CYCLONEII = var_family_base_cycloneii;
|
2855 |
|
|
end
|
2856 |
|
|
endfunction //FEATURE_FAMILY_BASE_CYCLONEII
|
2857 |
|
|
|
2858 |
|
|
function FEATURE_FAMILY_BASE_CYCLONE;
|
2859 |
|
|
input[8*20:1] device;
|
2860 |
|
|
reg var_family_base_cyclone;
|
2861 |
|
|
begin
|
2862 |
|
|
if (IS_FAMILY_CYCLONE(device) )
|
2863 |
|
|
var_family_base_cyclone = 1;
|
2864 |
|
|
else
|
2865 |
|
|
var_family_base_cyclone = 0;
|
2866 |
|
|
|
2867 |
|
|
FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone;
|
2868 |
|
|
end
|
2869 |
|
|
endfunction //FEATURE_FAMILY_BASE_CYCLONE
|
2870 |
|
|
|
2871 |
|
|
function FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM;
|
2872 |
|
|
input[8*20:1] device;
|
2873 |
|
|
reg var_family_has_stratixii_style_ram;
|
2874 |
|
|
begin
|
2875 |
|
|
if (FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
|
2876 |
|
|
var_family_has_stratixii_style_ram = 1;
|
2877 |
|
|
else
|
2878 |
|
|
var_family_has_stratixii_style_ram = 0;
|
2879 |
|
|
|
2880 |
|
|
FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM = var_family_has_stratixii_style_ram;
|
2881 |
|
|
end
|
2882 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM
|
2883 |
|
|
|
2884 |
|
|
function FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM;
|
2885 |
|
|
input[8*20:1] device;
|
2886 |
|
|
reg var_family_has_stratixiii_style_ram;
|
2887 |
|
|
begin
|
2888 |
|
|
if (FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
|
2889 |
|
|
var_family_has_stratixiii_style_ram = 1;
|
2890 |
|
|
else
|
2891 |
|
|
var_family_has_stratixiii_style_ram = 0;
|
2892 |
|
|
|
2893 |
|
|
FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM = var_family_has_stratixiii_style_ram;
|
2894 |
|
|
end
|
2895 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM
|
2896 |
|
|
|
2897 |
|
|
function FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL;
|
2898 |
|
|
input[8*20:1] device;
|
2899 |
|
|
reg var_family_has_stratix_style_pll;
|
2900 |
|
|
begin
|
2901 |
|
|
if (FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIXGX(device) )
|
2902 |
|
|
var_family_has_stratix_style_pll = 1;
|
2903 |
|
|
else
|
2904 |
|
|
var_family_has_stratix_style_pll = 0;
|
2905 |
|
|
|
2906 |
|
|
FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL = var_family_has_stratix_style_pll;
|
2907 |
|
|
end
|
2908 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL
|
2909 |
|
|
|
2910 |
|
|
function FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL;
|
2911 |
|
|
input[8*20:1] device;
|
2912 |
|
|
reg var_family_has_stratixii_style_pll;
|
2913 |
|
|
begin
|
2914 |
|
|
if (FEATURE_FAMILY_STRATIXII(device) && ! FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEII(device) && ! FEATURE_FAMILY_CYCLONEIII(device) )
|
2915 |
|
|
var_family_has_stratixii_style_pll = 1;
|
2916 |
|
|
else
|
2917 |
|
|
var_family_has_stratixii_style_pll = 0;
|
2918 |
|
|
|
2919 |
|
|
FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL = var_family_has_stratixii_style_pll;
|
2920 |
|
|
end
|
2921 |
|
|
endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL
|
2922 |
|
|
|
2923 |
|
|
function FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO;
|
2924 |
|
|
input[8*20:1] device;
|
2925 |
|
|
reg var_family_has_inverted_output_ddio;
|
2926 |
|
|
begin
|
2927 |
|
|
if (FEATURE_FAMILY_CYCLONEII(device) )
|
2928 |
|
|
var_family_has_inverted_output_ddio = 1;
|
2929 |
|
|
else
|
2930 |
|
|
var_family_has_inverted_output_ddio = 0;
|
2931 |
|
|
|
2932 |
|
|
FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO = var_family_has_inverted_output_ddio;
|
2933 |
|
|
end
|
2934 |
|
|
endfunction //FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO
|
2935 |
|
|
|
2936 |
|
|
function IS_VALID_FAMILY;
|
2937 |
|
|
input[8*20:1] device;
|
2938 |
|
|
reg is_valid;
|
2939 |
|
|
begin
|
2940 |
|
|
if (((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
|
2941 |
|
|
|| ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
|
2942 |
|
|
|| ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
|
2943 |
|
|
|| ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
|
2944 |
|
|
|| ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
|
2945 |
|
|
|| ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
|
2946 |
|
|
|| ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
|
2947 |
|
|
|| ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
|
2948 |
|
|
|| ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
|
2949 |
|
|
|| ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
|
2950 |
|
|
|| ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
|
2951 |
|
|
|| ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
|
2952 |
|
|
|| ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
|
2953 |
|
|
|| ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
|
2954 |
|
|
|| ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
|
2955 |
|
|
|| ((device == "BS") || (device == "bs"))
|
2956 |
|
|
|| ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
|
2957 |
|
|
|| ((device == "tgx_commercial_v1_1") || (device == "TGX_COMMERCIAL_V1_1"))
|
2958 |
|
|
|| ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
|
2959 |
|
|
|| ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
|
2960 |
|
|
|| ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)"))
|
2961 |
|
|
|| ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
|
2962 |
|
|
|| ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray"))
|
2963 |
|
|
|| ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive"))
|
2964 |
|
|
|| ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)"))
|
2965 |
|
|
|| ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz"))
|
2966 |
|
|
|| ((device == "arriaiigz_commercial_v1_1") || (device == "ARRIAIIGZ_COMMERCIAL_V1_1"))
|
2967 |
|
|
|| ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade"))
|
2968 |
|
|
|| ((device == "ArriaV") || (device == "ARRIAV") || (device == "arriav") || (device == "Arria V") || (device == "ARRIA V") || (device == "arria v")))
|
2969 |
|
|
is_valid = 1;
|
2970 |
|
|
else
|
2971 |
|
|
is_valid = 0;
|
2972 |
|
|
|
2973 |
|
|
IS_VALID_FAMILY = is_valid;
|
2974 |
|
|
end
|
2975 |
|
|
endfunction // IS_VALID_FAMILY
|
2976 |
|
|
|
2977 |
|
|
|
2978 |
|
|
endmodule // ALTERA_DEVICE_FAMILIES
|
2979 |
|
|
|