OpenCores
URL https://opencores.org/ocsvn/bw_tiff_compression/bw_tiff_compression/trunk

Subversion Repositories bw_tiff_compression

[/] [bw_tiff_compression/] [trunk/] [CCITT4_v2_synthesis.vhd] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 amulder 
--------------------------------------------------------------------------------
2 
-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
3 
--------------------------------------------------------------------------------
4 
--   ____  ____
5 
--  /   /\/   /
6 
-- /___/  \  /    Vendor: Xilinx
7 
-- \   \   \/     Version: P.40xd
8 
--  \   \         Application: netgen
9 
--  /   /         Filename: CCITT4_v2_synthesis.vhd
10 
-- /___/   /\     Timestamp: Fri Dec  6 11:46:01 2013
11 
-- \   \  /  \
12 
--  \___\/\___\
13 
--
14 
-- Command      : -intstyle ise -ar Structure -tm CCITT4_v2 -w -dir netgen/synthesis -ofmt vhdl -sim CCITT4_v2.ngc CCITT4_v2_synthesis.vhd
15 
-- Device       : xc3s1200e-4-fg320
16 
-- Input file   : CCITT4_v2.ngc
17 
-- Output file  : /home/aart/Documents/Programming/Xilinx_ise/tiff_comp_send_prj_14.3/netgen/synthesis/CCITT4_v2_synthesis.vhd
18 
-- # of Entities        : 1
19 
-- Design Name  : CCITT4_v2
20 
-- Xilinx       : /opt/Xilinx/14.3/ISE_DS/ISE/
21 
--
22 
-- Purpose:
23 
--     This VHDL netlist is a verification model and uses simulation
24 
--     primitives which may not represent the true implementation of the
25 
--     device, however the netlist is functionally correct and should not
26 
--     be modified. This file cannot be synthesized and should only be used
27 
--     with supported simulation tools.
28 
--
29 
-- Reference:
30 
--     Command Line Tools User Guide, Chapter 23
31 
--     Synthesis and Simulation Design Guide, Chapter 6
32 
--
33 
--------------------------------------------------------------------------------
34 
 
35 
library IEEE;
36 
use IEEE.STD_LOGIC_1164.ALL;
37 
library UNISIM;
38 
use UNISIM.VCOMPONENTS.ALL;
39 
use UNISIM.VPKG.ALL;
40 
 
41 
entity CCITT4_v2 is
42 
  port (
43 
    pclk_i : in STD_LOGIC := 'X';
44 
    frame_finished_o : out STD_LOGIC;
45 
    fsync_i : in STD_LOGIC := 'X';
46 
    pix_i : in STD_LOGIC := 'X';
47 
    run_len_code_valid_o : out STD_LOGIC;
48 
    rsync_i : in STD_LOGIC := 'X';
49 
    run_len_code_o : out STD_LOGIC_VECTOR ( 27 downto 0 );
50 
    fax4_x : out STD_LOGIC_VECTOR ( 9 downto 0 );
51 
    fax4_y : out STD_LOGIC_VECTOR ( 8 downto 0 );
52 
    run_len_code_width_o : out STD_LOGIC_VECTOR ( 4 downto 0 )
53 
  );
54 
end CCITT4_v2;
55 
 
56 
architecture Structure of CCITT4_v2 is
57 
  signal N1 : STD_LOGIC;
58 
  signal N10 : STD_LOGIC;
59 
  signal N101 : STD_LOGIC;
60 
  signal N103 : STD_LOGIC;
61 
  signal N105 : STD_LOGIC;
62 
  signal N111 : STD_LOGIC;
63 
  signal N113 : STD_LOGIC;
64 
  signal N115 : STD_LOGIC;
65 
  signal N117 : STD_LOGIC;
66 
  signal N119 : STD_LOGIC;
67 
  signal N12 : STD_LOGIC;
68 
  signal N121 : STD_LOGIC;
69 
  signal N123 : STD_LOGIC;
70 
  signal N125 : STD_LOGIC;
71 
  signal N127 : STD_LOGIC;
72 
  signal N133 : STD_LOGIC;
73 
  signal N142 : STD_LOGIC;
74 
  signal N144 : STD_LOGIC;
75 
  signal N146 : STD_LOGIC;
76 
  signal N148 : STD_LOGIC;
77 
  signal N160 : STD_LOGIC;
78 
  signal N161 : STD_LOGIC;
79 
  signal N165 : STD_LOGIC;
80 
  signal N167 : STD_LOGIC;
81 
  signal N172 : STD_LOGIC;
82 
  signal N174 : STD_LOGIC;
83 
  signal N176 : STD_LOGIC;
84 
  signal N177 : STD_LOGIC;
85 
  signal N179 : STD_LOGIC;
86 
  signal N18 : STD_LOGIC;
87 
  signal N180 : STD_LOGIC;
88 
  signal N182 : STD_LOGIC;
89 
  signal N184 : STD_LOGIC;
90 
  signal N2 : STD_LOGIC;
91 
  signal N208 : STD_LOGIC;
92 
  signal N218 : STD_LOGIC;
93 
  signal N220 : STD_LOGIC;
94 
  signal N221 : STD_LOGIC;
95 
  signal N223 : STD_LOGIC;
96 
  signal N225 : STD_LOGIC;
97 
  signal N227 : STD_LOGIC;
98 
  signal N229 : STD_LOGIC;
99 
  signal N231 : STD_LOGIC;
100 
  signal N233 : STD_LOGIC;
101 
  signal N235 : STD_LOGIC;
102 
  signal N237 : STD_LOGIC;
103 
  signal N239 : STD_LOGIC;
104 
  signal N24 : STD_LOGIC;
105 
  signal N240 : STD_LOGIC;
106 
  signal N242 : STD_LOGIC;
107 
  signal N243 : STD_LOGIC;
108 
  signal N245 : STD_LOGIC;
109 
  signal N246 : STD_LOGIC;
110 
  signal N248 : STD_LOGIC;
111 
  signal N249 : STD_LOGIC;
112 
  signal N251 : STD_LOGIC;
113 
  signal N252 : STD_LOGIC;
114 
  signal N254 : STD_LOGIC;
115 
  signal N255 : STD_LOGIC;
116 
  signal N257 : STD_LOGIC;
117 
  signal N258 : STD_LOGIC;
118 
  signal N26 : STD_LOGIC;
119 
  signal N260 : STD_LOGIC;
120 
  signal N261 : STD_LOGIC;
121 
  signal N263 : STD_LOGIC;
122 
  signal N264 : STD_LOGIC;
123 
  signal N266 : STD_LOGIC;
124 
  signal N267 : STD_LOGIC;
125 
  signal N269 : STD_LOGIC;
126 
  signal N271 : STD_LOGIC;
127 
  signal N285 : STD_LOGIC;
128 
  signal N287 : STD_LOGIC;
129 
  signal N288 : STD_LOGIC;
130 
  signal N305 : STD_LOGIC;
131 
  signal N315 : STD_LOGIC;
132 
  signal N317 : STD_LOGIC;
133 
  signal N319 : STD_LOGIC;
134 
  signal N333 : STD_LOGIC;
135 
  signal N337 : STD_LOGIC;
136 
  signal N339 : STD_LOGIC;
137 
  signal N341 : STD_LOGIC;
138 
  signal N343 : STD_LOGIC;
139 
  signal N345 : STD_LOGIC;
140 
  signal N349 : STD_LOGIC;
141 
  signal N351 : STD_LOGIC;
142 
  signal N355 : STD_LOGIC;
143 
  signal N359 : STD_LOGIC;
144 
  signal N361 : STD_LOGIC;
145 
  signal N363 : STD_LOGIC;
146 
  signal N365 : STD_LOGIC;
147 
  signal N367 : STD_LOGIC;
148 
  signal N369 : STD_LOGIC;
149 
  signal N371 : STD_LOGIC;
150 
  signal N373 : STD_LOGIC;
151 
  signal N375 : STD_LOGIC;
152 
  signal N377 : STD_LOGIC;
153 
  signal N381 : STD_LOGIC;
154 
  signal N383 : STD_LOGIC;
155 
  signal N385 : STD_LOGIC;
156 
  signal N387 : STD_LOGIC;
157 
  signal N388 : STD_LOGIC;
158 
  signal N389 : STD_LOGIC;
159 
  signal N390 : STD_LOGIC;
160 
  signal N391 : STD_LOGIC;
161 
  signal N392 : STD_LOGIC;
162 
  signal N393 : STD_LOGIC;
163 
  signal N394 : STD_LOGIC;
164 
  signal N395 : STD_LOGIC;
165 
  signal N396 : STD_LOGIC;
166 
  signal N397 : STD_LOGIC;
167 
  signal N398 : STD_LOGIC;
168 
  signal N399 : STD_LOGIC;
169 
  signal N400 : STD_LOGIC;
170 
  signal N401 : STD_LOGIC;
171 
  signal N402 : STD_LOGIC;
172 
  signal N403 : STD_LOGIC;
173 
  signal N404 : STD_LOGIC;
174 
  signal N405 : STD_LOGIC;
175 
  signal N406 : STD_LOGIC;
176 
  signal N407 : STD_LOGIC;
177 
  signal N408 : STD_LOGIC;
178 
  signal N409 : STD_LOGIC;
179 
  signal N410 : STD_LOGIC;
180 
  signal N411 : STD_LOGIC;
181 
  signal N412 : STD_LOGIC;
182 
  signal N413 : STD_LOGIC;
183 
  signal N414 : STD_LOGIC;
184 
  signal N415 : STD_LOGIC;
185 
  signal N416 : STD_LOGIC;
186 
  signal N417 : STD_LOGIC;
187 
  signal N418 : STD_LOGIC;
188 
  signal N419 : STD_LOGIC;
189 
  signal N420 : STD_LOGIC;
190 
  signal N421 : STD_LOGIC;
191 
  signal N422 : STD_LOGIC;
192 
  signal N423 : STD_LOGIC;
193 
  signal N424 : STD_LOGIC;
194 
  signal N425 : STD_LOGIC;
195 
  signal N426 : STD_LOGIC;
196 
  signal N427 : STD_LOGIC;
197 
  signal N428 : STD_LOGIC;
198 
  signal N429 : STD_LOGIC;
199 
  signal N430 : STD_LOGIC;
200 
  signal N431 : STD_LOGIC;
201 
  signal N432 : STD_LOGIC;
202 
  signal N433 : STD_LOGIC;
203 
  signal N434 : STD_LOGIC;
204 
  signal N435 : STD_LOGIC;
205 
  signal N436 : STD_LOGIC;
206 
  signal N437 : STD_LOGIC;
207 
  signal N438 : STD_LOGIC;
208 
  signal N439 : STD_LOGIC;
209 
  signal N440 : STD_LOGIC;
210 
  signal N441 : STD_LOGIC;
211 
  signal N442 : STD_LOGIC;
212 
  signal N443 : STD_LOGIC;
213 
  signal N444 : STD_LOGIC;
214 
  signal N445 : STD_LOGIC;
215 
  signal N446 : STD_LOGIC;
216 
  signal N447 : STD_LOGIC;
217 
  signal N448 : STD_LOGIC;
218 
  signal N449 : STD_LOGIC;
219 
  signal N450 : STD_LOGIC;
220 
  signal N451 : STD_LOGIC;
221 
  signal N452 : STD_LOGIC;
222 
  signal N453 : STD_LOGIC;
223 
  signal N454 : STD_LOGIC;
224 
  signal N455 : STD_LOGIC;
225 
  signal N456 : STD_LOGIC;
226 
  signal N457 : STD_LOGIC;
227 
  signal N458 : STD_LOGIC;
228 
  signal N459 : STD_LOGIC;
229 
  signal N460 : STD_LOGIC;
230 
  signal N461 : STD_LOGIC;
231 
  signal N462 : STD_LOGIC;
232 
  signal N463 : STD_LOGIC;
233 
  signal N464 : STD_LOGIC;
234 
  signal N465 : STD_LOGIC;
235 
  signal N466 : STD_LOGIC;
236 
  signal N467 : STD_LOGIC;
237 
  signal N468 : STD_LOGIC;
238 
  signal N469 : STD_LOGIC;
239 
  signal N470 : STD_LOGIC;
240 
  signal N471 : STD_LOGIC;
241 
  signal N472 : STD_LOGIC;
242 
  signal N473 : STD_LOGIC;
243 
  signal N474 : STD_LOGIC;
244 
  signal N475 : STD_LOGIC;
245 
  signal N476 : STD_LOGIC;
246 
  signal N477 : STD_LOGIC;
247 
  signal N478 : STD_LOGIC;
248 
  signal N479 : STD_LOGIC;
249 
  signal N480 : STD_LOGIC;
250 
  signal N481 : STD_LOGIC;
251 
  signal N482 : STD_LOGIC;
252 
  signal N483 : STD_LOGIC;
253 
  signal N484 : STD_LOGIC;
254 
  signal N485 : STD_LOGIC;
255 
  signal N486 : STD_LOGIC;
256 
  signal N487 : STD_LOGIC;
257 
  signal N488 : STD_LOGIC;
258 
  signal N489 : STD_LOGIC;
259 
  signal N490 : STD_LOGIC;
260 
  signal N491 : STD_LOGIC;
261 
  signal N492 : STD_LOGIC;
262 
  signal N493 : STD_LOGIC;
263 
  signal N494 : STD_LOGIC;
264 
  signal N495 : STD_LOGIC;
265 
  signal N496 : STD_LOGIC;
266 
  signal N497 : STD_LOGIC;
267 
  signal N498 : STD_LOGIC;
268 
  signal N56 : STD_LOGIC;
269 
  signal N7 : STD_LOGIC;
270 
  signal N73 : STD_LOGIC;
271 
  signal N75 : STD_LOGIC;
272 
  signal N77 : STD_LOGIC;
273 
  signal N79 : STD_LOGIC;
274 
  signal N80 : STD_LOGIC;
275 
  signal N82 : STD_LOGIC;
276 
  signal N83 : STD_LOGIC;
277 
  signal N85 : STD_LOGIC;
278 
  signal N87 : STD_LOGIC;
279 
  signal N89 : STD_LOGIC;
280 
  signal N9 : STD_LOGIC;
281 
  signal N93 : STD_LOGIC;
282 
  signal N95 : STD_LOGIC;
283 
  signal N97 : STD_LOGIC;
284 
  signal N99 : STD_LOGIC;
285 
  signal fax4_ins_EOF_prev_228 : STD_LOGIC;
286 
  signal fax4_ins_EOL : STD_LOGIC;
287 
  signal fax4_ins_EOL_prev_230 : STD_LOGIC;
288 
  signal fax4_ins_EOL_prev_prev_231 : STD_LOGIC;
289 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_1_rt_234 : STD_LOGIC;
290 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_2_rt_236 : STD_LOGIC;
291 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_3_rt_238 : STD_LOGIC;
292 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_4_rt_240 : STD_LOGIC;
293 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_5_rt_242 : STD_LOGIC;
294 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_6_rt_244 : STD_LOGIC;
295 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_7_rt_246 : STD_LOGIC;
296 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_8_rt_248 : STD_LOGIC;
297 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_0 : STD_LOGIC;
298 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_1 : STD_LOGIC;
299 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_2 : STD_LOGIC;
300 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_3 : STD_LOGIC;
301 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_4 : STD_LOGIC;
302 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_5 : STD_LOGIC;
303 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_6 : STD_LOGIC;
304 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_7 : STD_LOGIC;
305 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_8 : STD_LOGIC;
306 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_9 : STD_LOGIC;
307 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_9_rt_260 : STD_LOGIC;
308 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_1_rt_282 : STD_LOGIC;
309 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_2_rt_284 : STD_LOGIC;
310 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_3_rt_286 : STD_LOGIC;
311 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_4_rt_288 : STD_LOGIC;
312 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_5_rt_290 : STD_LOGIC;
313 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_6_rt_292 : STD_LOGIC;
314 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_7_rt_294 : STD_LOGIC;
315 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_8_rt_296 : STD_LOGIC;
316 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_0 : STD_LOGIC;
317 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_1 : STD_LOGIC;
318 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_2 : STD_LOGIC;
319 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_3 : STD_LOGIC;
320 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_4 : STD_LOGIC;
321 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_5 : STD_LOGIC;
322 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_6 : STD_LOGIC;
323 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_7 : STD_LOGIC;
324 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_8 : STD_LOGIC;
325 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_9 : STD_LOGIC;
326 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_9_rt_308 : STD_LOGIC;
327 
  signal fax4_ins_FIFO1_multi_read_ins_N11 : STD_LOGIC;
328 
  signal fax4_ins_FIFO1_multi_read_ins_N4 : STD_LOGIC;
329 
  signal fax4_ins_FIFO1_multi_read_ins_N7 : STD_LOGIC;
330 
  signal fax4_ins_FIFO1_multi_read_ins_N8 : STD_LOGIC;
331 
  signal fax4_ins_FIFO1_multi_read_ins_Result_0_1 : STD_LOGIC;
332 
  signal fax4_ins_FIFO1_multi_read_ins_Result_0_2 : STD_LOGIC;
333 
  signal fax4_ins_FIFO1_multi_read_ins_Result_1_1 : STD_LOGIC;
334 
  signal fax4_ins_FIFO1_multi_read_ins_Result_1_2 : STD_LOGIC;
335 
  signal fax4_ins_FIFO1_multi_read_ins_Result_2_1 : STD_LOGIC;
336 
  signal fax4_ins_FIFO1_multi_read_ins_Result_2_2 : STD_LOGIC;
337 
  signal fax4_ins_FIFO1_multi_read_ins_Result_3_1 : STD_LOGIC;
338 
  signal fax4_ins_FIFO1_multi_read_ins_Result_3_2 : STD_LOGIC;
339 
  signal fax4_ins_FIFO1_multi_read_ins_Result_4_1 : STD_LOGIC;
340 
  signal fax4_ins_FIFO1_multi_read_ins_Result_4_2 : STD_LOGIC;
341 
  signal fax4_ins_FIFO1_multi_read_ins_Result_5_1 : STD_LOGIC;
342 
  signal fax4_ins_FIFO1_multi_read_ins_Result_5_2 : STD_LOGIC;
343 
  signal fax4_ins_FIFO1_multi_read_ins_Result_6_1 : STD_LOGIC;
344 
  signal fax4_ins_FIFO1_multi_read_ins_Result_6_2 : STD_LOGIC;
345 
  signal fax4_ins_FIFO1_multi_read_ins_Result_7_1 : STD_LOGIC;
346 
  signal fax4_ins_FIFO1_multi_read_ins_Result_7_2 : STD_LOGIC;
347 
  signal fax4_ins_FIFO1_multi_read_ins_Result_8_1 : STD_LOGIC;
348 
  signal fax4_ins_FIFO1_multi_read_ins_Result_8_2 : STD_LOGIC;
349 
  signal fax4_ins_FIFO1_multi_read_ins_Result_9_1 : STD_LOGIC;
350 
  signal fax4_ins_FIFO1_multi_read_ins_Result_9_2 : STD_LOGIC;
351 
  signal fax4_ins_FIFO1_multi_read_ins_latch1 : STD_LOGIC;
352 
  signal fax4_ins_FIFO1_multi_read_ins_latch2 : STD_LOGIC;
353 
  signal fax4_ins_FIFO1_multi_read_ins_latch3 : STD_LOGIC;
354 
  signal fax4_ins_FIFO1_multi_read_ins_mem_rd_387 : STD_LOGIC;
355 
  signal fax4_ins_FIFO1_multi_read_ins_mux1_to_white : STD_LOGIC;
356 
  signal fax4_ins_FIFO1_multi_read_ins_mux1_valid : STD_LOGIC;
357 
  signal fax4_ins_FIFO1_multi_read_ins_mux2 : STD_LOGIC;
358 
  signal fax4_ins_FIFO1_multi_read_ins_mux2_to_white : STD_LOGIC;
359 
  signal fax4_ins_FIFO1_multi_read_ins_mux2_valid : STD_LOGIC;
360 
  signal fax4_ins_FIFO1_multi_read_ins_mux3 : STD_LOGIC;
361 
  signal fax4_ins_FIFO1_multi_read_ins_mux3_to_white : STD_LOGIC;
362 
  signal fax4_ins_FIFO1_multi_read_ins_mux3_valid : STD_LOGIC;
363 
  signal fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_426 : STD_LOGIC;
364 
  signal fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_rstpot_427 : STD_LOGIC;
365 
  signal fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000 : STD_LOGIC;
366 
  signal fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq000015_439 : STD_LOGIC;
367 
  signal fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq00007_440 : STD_LOGIC;
368 
  signal fax4_ins_FIFO1_multi_read_ins_to_white1_o_441 : STD_LOGIC;
369 
  signal fax4_ins_FIFO1_multi_read_ins_to_white2_o_442 : STD_LOGIC;
370 
  signal fax4_ins_FIFO1_multi_read_ins_to_white3_o_443 : STD_LOGIC;
371 
  signal fax4_ins_FIFO1_multi_read_ins_used_not0002_454 : STD_LOGIC;
372 
  signal fax4_ins_FIFO1_multi_read_ins_used_not0003_inv : STD_LOGIC;
373 
  signal fax4_ins_FIFO1_multi_read_ins_valid1_o_456 : STD_LOGIC;
374 
  signal fax4_ins_FIFO1_multi_read_ins_valid2_o_457 : STD_LOGIC;
375 
  signal fax4_ins_FIFO1_multi_read_ins_valid3_o_458 : STD_LOGIC;
376 
  signal fax4_ins_FIFO1_multi_read_ins_wr_459 : STD_LOGIC;
377 
  signal fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000 : STD_LOGIC;
378 
  signal fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq000015_471 : STD_LOGIC;
379 
  signal fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq00007_472 : STD_LOGIC;
380 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_1_rt_475 : STD_LOGIC;
381 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_2_rt_477 : STD_LOGIC;
382 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_3_rt_479 : STD_LOGIC;
383 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_4_rt_481 : STD_LOGIC;
384 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_5_rt_483 : STD_LOGIC;
385 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_6_rt_485 : STD_LOGIC;
386 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_7_rt_487 : STD_LOGIC;
387 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_8_rt_489 : STD_LOGIC;
388 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_0 : STD_LOGIC;
389 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_1 : STD_LOGIC;
390 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_2 : STD_LOGIC;
391 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_3 : STD_LOGIC;
392 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_4 : STD_LOGIC;
393 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_5 : STD_LOGIC;
394 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_6 : STD_LOGIC;
395 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_7 : STD_LOGIC;
396 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_8 : STD_LOGIC;
397 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_9 : STD_LOGIC;
398 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_9_rt_501 : STD_LOGIC;
399 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_1_rt_523 : STD_LOGIC;
400 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_2_rt_525 : STD_LOGIC;
401 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_3_rt_527 : STD_LOGIC;
402 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_4_rt_529 : STD_LOGIC;
403 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_5_rt_531 : STD_LOGIC;
404 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_6_rt_533 : STD_LOGIC;
405 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_7_rt_535 : STD_LOGIC;
406 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_8_rt_537 : STD_LOGIC;
407 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_0 : STD_LOGIC;
408 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_1 : STD_LOGIC;
409 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_2 : STD_LOGIC;
410 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_3 : STD_LOGIC;
411 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_4 : STD_LOGIC;
412 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_5 : STD_LOGIC;
413 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_6 : STD_LOGIC;
414 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_7 : STD_LOGIC;
415 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_8 : STD_LOGIC;
416 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_9 : STD_LOGIC;
417 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_9_rt_549 : STD_LOGIC;
418 
  signal fax4_ins_FIFO2_multi_read_ins_N11 : STD_LOGIC;
419 
  signal fax4_ins_FIFO2_multi_read_ins_N4 : STD_LOGIC;
420 
  signal fax4_ins_FIFO2_multi_read_ins_N7 : STD_LOGIC;
421 
  signal fax4_ins_FIFO2_multi_read_ins_N8 : STD_LOGIC;
422 
  signal fax4_ins_FIFO2_multi_read_ins_Result_0_1 : STD_LOGIC;
423 
  signal fax4_ins_FIFO2_multi_read_ins_Result_0_2 : STD_LOGIC;
424 
  signal fax4_ins_FIFO2_multi_read_ins_Result_1_1 : STD_LOGIC;
425 
  signal fax4_ins_FIFO2_multi_read_ins_Result_1_2 : STD_LOGIC;
426 
  signal fax4_ins_FIFO2_multi_read_ins_Result_2_1 : STD_LOGIC;
427 
  signal fax4_ins_FIFO2_multi_read_ins_Result_2_2 : STD_LOGIC;
428 
  signal fax4_ins_FIFO2_multi_read_ins_Result_3_1 : STD_LOGIC;
429 
  signal fax4_ins_FIFO2_multi_read_ins_Result_3_2 : STD_LOGIC;
430 
  signal fax4_ins_FIFO2_multi_read_ins_Result_4_1 : STD_LOGIC;
431 
  signal fax4_ins_FIFO2_multi_read_ins_Result_4_2 : STD_LOGIC;
432 
  signal fax4_ins_FIFO2_multi_read_ins_Result_5_1 : STD_LOGIC;
433 
  signal fax4_ins_FIFO2_multi_read_ins_Result_5_2 : STD_LOGIC;
434 
  signal fax4_ins_FIFO2_multi_read_ins_Result_6_1 : STD_LOGIC;
435 
  signal fax4_ins_FIFO2_multi_read_ins_Result_6_2 : STD_LOGIC;
436 
  signal fax4_ins_FIFO2_multi_read_ins_Result_7_1 : STD_LOGIC;
437 
  signal fax4_ins_FIFO2_multi_read_ins_Result_7_2 : STD_LOGIC;
438 
  signal fax4_ins_FIFO2_multi_read_ins_Result_8_1 : STD_LOGIC;
439 
  signal fax4_ins_FIFO2_multi_read_ins_Result_8_2 : STD_LOGIC;
440 
  signal fax4_ins_FIFO2_multi_read_ins_Result_9_1 : STD_LOGIC;
441 
  signal fax4_ins_FIFO2_multi_read_ins_Result_9_2 : STD_LOGIC;
442 
  signal fax4_ins_FIFO2_multi_read_ins_latch1 : STD_LOGIC;
443 
  signal fax4_ins_FIFO2_multi_read_ins_latch2 : STD_LOGIC;
444 
  signal fax4_ins_FIFO2_multi_read_ins_latch3 : STD_LOGIC;
445 
  signal fax4_ins_FIFO2_multi_read_ins_mem_rd_628 : STD_LOGIC;
446 
  signal fax4_ins_FIFO2_multi_read_ins_mux1_to_white : STD_LOGIC;
447 
  signal fax4_ins_FIFO2_multi_read_ins_mux1_valid : STD_LOGIC;
448 
  signal fax4_ins_FIFO2_multi_read_ins_mux2 : STD_LOGIC;
449 
  signal fax4_ins_FIFO2_multi_read_ins_mux2_to_white : STD_LOGIC;
450 
  signal fax4_ins_FIFO2_multi_read_ins_mux2_valid : STD_LOGIC;
451 
  signal fax4_ins_FIFO2_multi_read_ins_mux3 : STD_LOGIC;
452 
  signal fax4_ins_FIFO2_multi_read_ins_mux3_and0000 : STD_LOGIC;
453 
  signal fax4_ins_FIFO2_multi_read_ins_mux3_to_white : STD_LOGIC;
454 
  signal fax4_ins_FIFO2_multi_read_ins_mux3_valid : STD_LOGIC;
455 
  signal fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_668 : STD_LOGIC;
456 
  signal fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_rstpot_669 : STD_LOGIC;
457 
  signal fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000 : STD_LOGIC;
458 
  signal fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq000015_681 : STD_LOGIC;
459 
  signal fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq00007_682 : STD_LOGIC;
460 
  signal fax4_ins_FIFO2_multi_read_ins_to_white1_o_683 : STD_LOGIC;
461 
  signal fax4_ins_FIFO2_multi_read_ins_to_white2_o_684 : STD_LOGIC;
462 
  signal fax4_ins_FIFO2_multi_read_ins_to_white3_o_685 : STD_LOGIC;
463 
  signal fax4_ins_FIFO2_multi_read_ins_used_not0002_696 : STD_LOGIC;
464 
  signal fax4_ins_FIFO2_multi_read_ins_used_not0003_inv : STD_LOGIC;
465 
  signal fax4_ins_FIFO2_multi_read_ins_valid1_o_698 : STD_LOGIC;
466 
  signal fax4_ins_FIFO2_multi_read_ins_valid2_o_699 : STD_LOGIC;
467 
  signal fax4_ins_FIFO2_multi_read_ins_valid3_o_700 : STD_LOGIC;
468 
  signal fax4_ins_FIFO2_multi_read_ins_wr : STD_LOGIC;
469 
  signal fax4_ins_FIFO2_multi_read_ins_wr1_702 : STD_LOGIC;
470 
  signal fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000 : STD_LOGIC;
471 
  signal fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq000015_714 : STD_LOGIC;
472 
  signal fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq00007_715 : STD_LOGIC;
473 
  signal fax4_ins_Madd_a1b1_addsub0001_cy_1_rt_717 : STD_LOGIC;
474 
  signal fax4_ins_Madd_a1b1_addsub0001_cy_4_rt_721 : STD_LOGIC;
475 
  signal fax4_ins_Madd_a1b1_addsub0001_cy_5_rt_723 : STD_LOGIC;
476 
  signal fax4_ins_Madd_a1b1_addsub0001_cy_6_rt_725 : STD_LOGIC;
477 
  signal fax4_ins_Madd_a1b1_addsub0001_cy_7_rt_727 : STD_LOGIC;
478 
  signal fax4_ins_Madd_a1b1_addsub0001_cy_9_rt_730 : STD_LOGIC;
479 
  signal fax4_ins_Madd_fifo_rd_addsub0000_cy_1_rt_733 : STD_LOGIC;
480 
  signal fax4_ins_Madd_fifo_rd_addsub0000_cy_2_rt_735 : STD_LOGIC;
481 
  signal fax4_ins_Madd_fifo_rd_addsub0000_cy_3_rt_737 : STD_LOGIC;
482 
  signal fax4_ins_Madd_fifo_rd_addsub0000_cy_4_rt_739 : STD_LOGIC;
483 
  signal fax4_ins_Madd_fifo_rd_addsub0000_cy_5_rt_741 : STD_LOGIC;
484 
  signal fax4_ins_Madd_fifo_rd_addsub0000_cy_6_rt_743 : STD_LOGIC;
485 
  signal fax4_ins_Madd_fifo_rd_addsub0000_cy_7_rt_745 : STD_LOGIC;
486 
  signal fax4_ins_Madd_fifo_rd_addsub0000_cy_8_rt_747 : STD_LOGIC;
487 
  signal fax4_ins_Madd_fifo_rd_addsub0000_xor_9_rt_749 : STD_LOGIC;
488 
  signal fax4_ins_N01 : STD_LOGIC;
489 
  signal fax4_ins_N13 : STD_LOGIC;
490 
  signal fax4_ins_N15 : STD_LOGIC;
491 
  signal fax4_ins_N19 : STD_LOGIC;
492 
  signal fax4_ins_N20 : STD_LOGIC;
493 
  signal fax4_ins_N53 : STD_LOGIC;
494 
  signal fax4_ins_a0_to_white_946 : STD_LOGIC;
495 
  signal fax4_ins_a0_to_white_mux0000 : STD_LOGIC;
496 
  signal fax4_ins_a0_to_white_mux000026_948 : STD_LOGIC;
497 
  signal fax4_ins_a0_to_white_mux00007_949 : STD_LOGIC;
498 
  signal fax4_ins_a0_value_o_950 : STD_LOGIC;
499 
  signal fax4_ins_a1b1_not0000_2_Q : STD_LOGIC;
500 
  signal fax4_ins_a1b1_not0000_3_Q : STD_LOGIC;
501 
  signal fax4_ins_a1b1_not0000_8_Q : STD_LOGIC;
502 
  signal fax4_ins_b1_mux0004_0_18_1027 : STD_LOGIC;
503 
  signal fax4_ins_b1_mux0004_1_12_1029 : STD_LOGIC;
504 
  signal fax4_ins_b1_mux0004_1_42 : STD_LOGIC;
505 
  signal fax4_ins_b1_mux0004_1_421_1031 : STD_LOGIC;
506 
  signal fax4_ins_b1_mux0004_2_12_1033 : STD_LOGIC;
507 
  signal fax4_ins_b1_mux0004_2_42 : STD_LOGIC;
508 
  signal fax4_ins_b1_mux0004_2_421_1035 : STD_LOGIC;
509 
  signal fax4_ins_b1_mux0004_3_12_1037 : STD_LOGIC;
510 
  signal fax4_ins_b1_mux0004_3_42 : STD_LOGIC;
511 
  signal fax4_ins_b1_mux0004_3_421_1039 : STD_LOGIC;
512 
  signal fax4_ins_b1_mux0004_4_18_1041 : STD_LOGIC;
513 
  signal fax4_ins_b1_mux0004_5_18_1043 : STD_LOGIC;
514 
  signal fax4_ins_b1_mux0004_6_18_1045 : STD_LOGIC;
515 
  signal fax4_ins_b1_mux0004_7_18_1047 : STD_LOGIC;
516 
  signal fax4_ins_b1_mux0004_8_12_1049 : STD_LOGIC;
517 
  signal fax4_ins_b1_mux0004_8_42 : STD_LOGIC;
518 
  signal fax4_ins_b1_mux0004_8_421_1051 : STD_LOGIC;
519 
  signal fax4_ins_b1_mux0004_9_18_1053 : STD_LOGIC;
520 
  signal fax4_ins_b2_mux0004_0_10_1065 : STD_LOGIC;
521 
  signal fax4_ins_b2_mux0004_0_36_1066 : STD_LOGIC;
522 
  signal fax4_ins_b2_mux0004_1_10_1068 : STD_LOGIC;
523 
  signal fax4_ins_b2_mux0004_1_33_1069 : STD_LOGIC;
524 
  signal fax4_ins_b2_mux0004_2_10_1071 : STD_LOGIC;
525 
  signal fax4_ins_b2_mux0004_2_33_1072 : STD_LOGIC;
526 
  signal fax4_ins_b2_mux0004_3_10_1074 : STD_LOGIC;
527 
  signal fax4_ins_b2_mux0004_3_33_1075 : STD_LOGIC;
528 
  signal fax4_ins_b2_mux0004_4_10_1077 : STD_LOGIC;
529 
  signal fax4_ins_b2_mux0004_4_36_1078 : STD_LOGIC;
530 
  signal fax4_ins_b2_mux0004_5_10_1080 : STD_LOGIC;
531 
  signal fax4_ins_b2_mux0004_5_36_1081 : STD_LOGIC;
532 
  signal fax4_ins_b2_mux0004_6_10_1083 : STD_LOGIC;
533 
  signal fax4_ins_b2_mux0004_6_36_1084 : STD_LOGIC;
534 
  signal fax4_ins_b2_mux0004_7_10_1086 : STD_LOGIC;
535 
  signal fax4_ins_b2_mux0004_7_36_1087 : STD_LOGIC;
536 
  signal fax4_ins_b2_mux0004_8_10_1089 : STD_LOGIC;
537 
  signal fax4_ins_b2_mux0004_8_33_1090 : STD_LOGIC;
538 
  signal fax4_ins_b2_mux0004_9_10_1092 : STD_LOGIC;
539 
  signal fax4_ins_b2_mux0004_9_36_1093 : STD_LOGIC;
540 
  signal fax4_ins_b2_to_white_1094 : STD_LOGIC;
541 
  signal fax4_ins_b2_to_white_and0000 : STD_LOGIC;
542 
  signal fax4_ins_b2_to_white_and0001 : STD_LOGIC;
543 
  signal fax4_ins_b2_to_white_mux0004 : STD_LOGIC;
544 
  signal fax4_ins_b2_to_white_mux000410_1098 : STD_LOGIC;
545 
  signal fax4_ins_b2_to_white_mux000452_1099 : STD_LOGIC;
546 
  signal fax4_ins_counter_xy_v2_ins_cnt_x_en : STD_LOGIC;
547 
  signal fax4_ins_counter_xy_v2_ins_cnt_x_overflow_prev_1101 : STD_LOGIC;
548 
  signal fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102 : STD_LOGIC;
549 
  signal fax4_ins_counter_xy_v2_ins_cnt_x_reset_or0000 : STD_LOGIC;
550 
  signal fax4_ins_counter_xy_v2_ins_cnt_y_overflow_prev_1104 : STD_LOGIC;
551 
  signal fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105 : STD_LOGIC;
552 
  signal fax4_ins_counter_xy_v2_ins_cnt_y_reset_or0000 : STD_LOGIC;
553 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_1_rt_1109 : STD_LOGIC;
554 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_2_rt_1111 : STD_LOGIC;
555 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_3_rt_1113 : STD_LOGIC;
556 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_4_rt_1115 : STD_LOGIC;
557 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_5_rt_1117 : STD_LOGIC;
558 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_6_rt_1119 : STD_LOGIC;
559 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_7_rt_1121 : STD_LOGIC;
560 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_8_rt_1123 : STD_LOGIC;
561 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_9_rt_1125 : STD_LOGIC;
562 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000 : STD_LOGIC;
563 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157 : STD_LOGIC;
564 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_mux0002 : STD_LOGIC;
565 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_1_rt_1161 : STD_LOGIC;
566 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_2_rt_1163 : STD_LOGIC;
567 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_3_rt_1165 : STD_LOGIC;
568 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_4_rt_1167 : STD_LOGIC;
569 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_5_rt_1169 : STD_LOGIC;
570 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_6_rt_1171 : STD_LOGIC;
571 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_7_rt_1173 : STD_LOGIC;
572 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_8_rt_1175 : STD_LOGIC;
573 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000 : STD_LOGIC;
574 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_overflow_o_1204 : STD_LOGIC;
575 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_overflow_o_mux0002 : STD_LOGIC;
576 
  signal fax4_ins_counter_xy_v2_ins_frame_valid_1206 : STD_LOGIC;
577 
  signal fax4_ins_counter_xy_v2_ins_frame_valid_and0000 : STD_LOGIC;
578 
  signal fax4_ins_counter_xy_v2_ins_frame_valid_and0001 : STD_LOGIC;
579 
  signal fax4_ins_counter_xy_v2_ins_fsync_i_prev_1209 : STD_LOGIC;
580 
  signal fax4_ins_counter_xy_v2_ins_line_valid_1210 : STD_LOGIC;
581 
  signal fax4_ins_counter_xy_v2_ins_line_valid_and0000 : STD_LOGIC;
582 
  signal fax4_ins_counter_xy_v2_ins_rsync_i_prev_1212 : STD_LOGIC;
583 
  signal fax4_ins_fifo1_rd : STD_LOGIC;
584 
  signal fax4_ins_fifo1_wr : STD_LOGIC;
585 
  signal fax4_ins_fifo2_rd : STD_LOGIC;
586 
  signal fax4_ins_fifo2_wr : STD_LOGIC;
587 
  signal fax4_ins_fifo_out1_to_white : STD_LOGIC;
588 
  signal fax4_ins_fifo_out2_valid : STD_LOGIC;
589 
  signal fax4_ins_fifo_out_prev1_to_white_1239 : STD_LOGIC;
590 
  signal fax4_ins_fifo_out_prev1_valid_1240 : STD_LOGIC;
591 
  signal fax4_ins_fifo_out_prev1_valid_mux0001 : STD_LOGIC;
592 
  signal fax4_ins_fifo_out_prev2_to_white_1252 : STD_LOGIC;
593 
  signal fax4_ins_fifo_out_prev2_valid_1253 : STD_LOGIC;
594 
  signal fax4_ins_fifo_out_prev2_valid_mux0001 : STD_LOGIC;
595 
  signal fax4_ins_fifo_rd : STD_LOGIC;
596 
  signal fax4_ins_fifo_rd0_1266 : STD_LOGIC;
597 
  signal fax4_ins_fifo_rd22_1267 : STD_LOGIC;
598 
  signal fax4_ins_fifo_rd3_1268 : STD_LOGIC;
599 
  signal fax4_ins_fifo_sel_prev_1279 : STD_LOGIC;
600 
  signal fax4_ins_load_a0 : STD_LOGIC;
601 
  signal fax4_ins_load_a1_or0000 : STD_LOGIC;
602 
  signal fax4_ins_load_a1_or0001 : STD_LOGIC;
603 
  signal fax4_ins_load_a2 : STD_LOGIC;
604 
  signal fax4_ins_load_mux_a0_1284 : STD_LOGIC;
605 
  signal fax4_ins_load_mux_b_1285 : STD_LOGIC;
606 
  signal fax4_ins_mode_indicator_o_0_rstpot_1287 : STD_LOGIC;
607 
  signal fax4_ins_mode_indicator_o_1_rstpot_1289 : STD_LOGIC;
608 
  signal fax4_ins_mode_indicator_o_2_rstpot_1291 : STD_LOGIC;
609 
  signal fax4_ins_mode_indicator_o_2_rstpot_SW1 : STD_LOGIC;
610 
  signal fax4_ins_mode_indicator_o_2_rstpot_SW11_1293 : STD_LOGIC;
611 
  signal fax4_ins_mode_indicator_o_3_rstpot_1295 : STD_LOGIC;
612 
  signal fax4_ins_mode_indicator_o_mux0001_2_232_1296 : STD_LOGIC;
613 
  signal fax4_ins_mode_indicator_o_mux0001_2_261_1297 : STD_LOGIC;
614 
  signal fax4_ins_mode_indicator_o_mux0001_2_3111_1298 : STD_LOGIC;
615 
  signal fax4_ins_mode_indicator_o_mux0001_2_341_1299 : STD_LOGIC;
616 
  signal fax4_ins_mode_indicator_o_mux0001_2_36_1300 : STD_LOGIC;
617 
  signal fax4_ins_mode_indicator_o_mux0001_3_9_1302 : STD_LOGIC;
618 
  signal fax4_ins_mux_a0_0_Q : STD_LOGIC;
619 
  signal fax4_ins_mux_a0_1_Q : STD_LOGIC;
620 
  signal fax4_ins_mux_a0_3_Q : STD_LOGIC;
621 
  signal fax4_ins_mux_b1_2_and000019_1310 : STD_LOGIC;
622 
  signal fax4_ins_output_valid_o_1311 : STD_LOGIC;
623 
  signal fax4_ins_output_valid_o_mux000315 : STD_LOGIC;
624 
  signal fax4_ins_output_valid_o_mux0003151_1313 : STD_LOGIC;
625 
  signal fax4_ins_output_valid_o_mux000336 : STD_LOGIC;
626 
  signal fax4_ins_pass_mode : STD_LOGIC;
627 
  signal fax4_ins_pclk_not : STD_LOGIC;
628 
  signal fax4_ins_pix_change_detector_reset : STD_LOGIC;
629 
  signal fax4_ins_pix_change_detector_reset_inv : STD_LOGIC;
630 
  signal fax4_ins_pix_changed_1319 : STD_LOGIC;
631 
  signal fax4_ins_pix_changed_mux0001 : STD_LOGIC;
632 
  signal fax4_ins_pix_prev_1321 : STD_LOGIC;
633 
  signal fax4_ins_state_FSM_FFd1_1322 : STD_LOGIC;
634 
  signal fax4_ins_state_FSM_FFd10_1323 : STD_LOGIC;
635 
  signal fax4_ins_state_FSM_FFd10_In_1324 : STD_LOGIC;
636 
  signal fax4_ins_state_FSM_FFd11_1325 : STD_LOGIC;
637 
  signal fax4_ins_state_FSM_FFd11_In1 : STD_LOGIC;
638 
  signal fax4_ins_state_FSM_FFd2_1327 : STD_LOGIC;
639 
  signal fax4_ins_state_FSM_FFd2_In_1328 : STD_LOGIC;
640 
  signal fax4_ins_state_FSM_FFd3_1329 : STD_LOGIC;
641 
  signal fax4_ins_state_FSM_FFd3_In : STD_LOGIC;
642 
  signal fax4_ins_state_FSM_FFd4_1331 : STD_LOGIC;
643 
  signal fax4_ins_state_FSM_FFd4_In11 : STD_LOGIC;
644 
  signal fax4_ins_state_FSM_FFd5_1333 : STD_LOGIC;
645 
  signal fax4_ins_state_FSM_FFd5_In : STD_LOGIC;
646 
  signal fax4_ins_state_FSM_FFd5_In5_1335 : STD_LOGIC;
647 
  signal fax4_ins_state_FSM_FFd6_1336 : STD_LOGIC;
648 
  signal fax4_ins_state_FSM_FFd6_In_1337 : STD_LOGIC;
649 
  signal fax4_ins_state_FSM_FFd8_1338 : STD_LOGIC;
650 
  signal fax4_ins_state_FSM_FFd8_In25 : STD_LOGIC;
651 
  signal fax4_ins_state_FSM_FFd8_In7_1340 : STD_LOGIC;
652 
  signal fax4_ins_state_FSM_FFd9_1341 : STD_LOGIC;
653 
  signal fax4_ins_state_FSM_FFd9_In1 : STD_LOGIC;
654 
  signal fax4_ins_state_FSM_N12 : STD_LOGIC;
655 
  signal fax4_ins_state_FSM_N7 : STD_LOGIC;
656 
  signal fax4_ins_state_updated_1345 : STD_LOGIC;
657 
  signal fax4_ins_state_updated_mux000824_1346 : STD_LOGIC;
658 
  signal fax4_ins_state_updated_mux000840_1347 : STD_LOGIC;
659 
  signal fax4_ins_state_updated_mux000854_1348 : STD_LOGIC;
660 
  signal fax4_ins_to_white_1349 : STD_LOGIC;
661 
  signal fax4_ins_to_white_mux0000 : STD_LOGIC;
662 
  signal fax4_ins_vertical_mode_cmp_le0000 : STD_LOGIC;
663 
  signal fax4_ins_vertical_mode_cmp_le000020_1361 : STD_LOGIC;
664 
  signal fax4_ins_vertical_mode_cmp_le00002114_1362 : STD_LOGIC;
665 
  signal fax4_ins_vertical_mode_cmp_le0000213_1363 : STD_LOGIC;
666 
  signal fax4_ins_vertical_mode_cmp_le00002169_1364 : STD_LOGIC;
667 
  signal fax4_ins_vertical_mode_cmp_le0000226_1365 : STD_LOGIC;
668 
  signal fax4_ins_vertical_mode_cmp_le0000245_1366 : STD_LOGIC;
669 
  signal fax4_ins_vertical_mode_cmp_le0000281_1367 : STD_LOGIC;
670 
  signal frame_finished_wire : STD_LOGIC;
671 
  signal huffman_ins_v2_Madd_code_black_width_add0000_cy_1_Q : STD_LOGIC;
672 
  signal huffman_ins_v2_Madd_code_black_width_add0000_cy_3_Q : STD_LOGIC;
673 
  signal huffman_ins_v2_Madd_code_black_width_add0000_cy_3_1 : STD_LOGIC;
674 
  signal huffman_ins_v2_Madd_code_black_width_add0000_cy_3_11_1373 : STD_LOGIC;
675 
  signal huffman_ins_v2_Madd_code_black_width_add0000_xor_3_11 : STD_LOGIC;
676 
  signal huffman_ins_v2_Madd_code_black_width_add0000_xor_3_111_1376 : STD_LOGIC;
677 
  signal huffman_ins_v2_Madd_code_white_width_add0000_cy_1_Q : STD_LOGIC;
678 
  signal huffman_ins_v2_Madd_code_white_width_add0000_cy_3_Q : STD_LOGIC;
679 
  signal huffman_ins_v2_Madd_code_white_width_add0000_cy_3_1 : STD_LOGIC;
680 
  signal huffman_ins_v2_Madd_code_white_width_add0000_cy_3_11_1380 : STD_LOGIC;
681 
  signal huffman_ins_v2_Madd_code_white_width_add0000_xor_3_11 : STD_LOGIC;
682 
  signal huffman_ins_v2_Madd_code_white_width_add0000_xor_3_111_1383 : STD_LOGIC;
683 
  signal huffman_ins_v2_Mrom_run_length_i_rom0000111 : STD_LOGIC;
684 
  signal huffman_ins_v2_Mrom_run_length_i_rom000012 : STD_LOGIC;
685 
  signal huffman_ins_v2_Mrom_run_length_i_rom00002 : STD_LOGIC;
686 
  signal huffman_ins_v2_Mrom_run_length_i_rom00003 : STD_LOGIC;
687 
  signal huffman_ins_v2_Mrom_run_length_i_rom00005 : STD_LOGIC;
688 
  signal huffman_ins_v2_Mshreg_a0_value_2_1394 : STD_LOGIC;
689 
  signal huffman_ins_v2_Mshreg_frame_finished_o_1395 : STD_LOGIC;
690 
  signal huffman_ins_v2_Mshreg_horizontal_mode_3_1396 : STD_LOGIC;
691 
  signal huffman_ins_v2_Mshreg_pass_vert_code_3_0_1397 : STD_LOGIC;
692 
  signal huffman_ins_v2_Mshreg_pass_vert_code_3_1_1398 : STD_LOGIC;
693 
  signal huffman_ins_v2_Mshreg_pass_vert_code_3_2_1399 : STD_LOGIC;
694 
  signal huffman_ins_v2_Mshreg_pass_vert_code_width_3_0_1400 : STD_LOGIC;
695 
  signal huffman_ins_v2_Mshreg_pass_vert_code_width_3_2_1401 : STD_LOGIC;
696 
  signal huffman_ins_v2_Mshreg_run_len_code_valid_o_1402 : STD_LOGIC;
697 
  signal huffman_ins_v2_Msub_run_length_white_addsub0000_cy_0_rt_1404 : STD_LOGIC;
698 
  signal huffman_ins_v2_N100 : STD_LOGIC;
699 
  signal huffman_ins_v2_N102 : STD_LOGIC;
700 
  signal huffman_ins_v2_N103 : STD_LOGIC;
701 
  signal huffman_ins_v2_N105 : STD_LOGIC;
702 
  signal huffman_ins_v2_N107 : STD_LOGIC;
703 
  signal huffman_ins_v2_N109 : STD_LOGIC;
704 
  signal huffman_ins_v2_N11 : STD_LOGIC;
705 
  signal huffman_ins_v2_N110 : STD_LOGIC;
706 
  signal huffman_ins_v2_N14 : STD_LOGIC;
707 
  signal huffman_ins_v2_N16 : STD_LOGIC;
708 
  signal huffman_ins_v2_N166 : STD_LOGIC;
709 
  signal huffman_ins_v2_N169 : STD_LOGIC;
710 
  signal huffman_ins_v2_N170 : STD_LOGIC;
711 
  signal huffman_ins_v2_N186 : STD_LOGIC;
712 
  signal huffman_ins_v2_N203 : STD_LOGIC;
713 
  signal huffman_ins_v2_N223 : STD_LOGIC;
714 
  signal huffman_ins_v2_N228 : STD_LOGIC;
715 
  signal huffman_ins_v2_N232 : STD_LOGIC;
716 
  signal huffman_ins_v2_N239 : STD_LOGIC;
717 
  signal huffman_ins_v2_N244 : STD_LOGIC;
718 
  signal huffman_ins_v2_N245 : STD_LOGIC;
719 
  signal huffman_ins_v2_N246 : STD_LOGIC;
720 
  signal huffman_ins_v2_N248 : STD_LOGIC;
721 
  signal huffman_ins_v2_N250 : STD_LOGIC;
722 
  signal huffman_ins_v2_N251 : STD_LOGIC;
723 
  signal huffman_ins_v2_N3 : STD_LOGIC;
724 
  signal huffman_ins_v2_N34 : STD_LOGIC;
725 
  signal huffman_ins_v2_N38 : STD_LOGIC;
726 
  signal huffman_ins_v2_N39 : STD_LOGIC;
727 
  signal huffman_ins_v2_N40 : STD_LOGIC;
728 
  signal huffman_ins_v2_N44 : STD_LOGIC;
729 
  signal huffman_ins_v2_N45 : STD_LOGIC;
730 
  signal huffman_ins_v2_N48 : STD_LOGIC;
731 
  signal huffman_ins_v2_N51 : STD_LOGIC;
732 
  signal huffman_ins_v2_N52 : STD_LOGIC;
733 
  signal huffman_ins_v2_N55 : STD_LOGIC;
734 
  signal huffman_ins_v2_N59 : STD_LOGIC;
735 
  signal huffman_ins_v2_N60 : STD_LOGIC;
736 
  signal huffman_ins_v2_N62 : STD_LOGIC;
737 
  signal huffman_ins_v2_N65 : STD_LOGIC;
738 
  signal huffman_ins_v2_N67 : STD_LOGIC;
739 
  signal huffman_ins_v2_N70 : STD_LOGIC;
740 
  signal huffman_ins_v2_N71 : STD_LOGIC;
741 
  signal huffman_ins_v2_N78 : STD_LOGIC;
742 
  signal huffman_ins_v2_N82 : STD_LOGIC;
743 
  signal huffman_ins_v2_N87 : STD_LOGIC;
744 
  signal huffman_ins_v2_N89 : STD_LOGIC;
745 
  signal huffman_ins_v2_N95 : STD_LOGIC;
746 
  signal huffman_ins_v2_N98 : STD_LOGIC;
747 
  signal huffman_ins_v2_N99 : STD_LOGIC;
748 
  signal huffman_ins_v2_a0_value_2_1510 : STD_LOGIC;
749 
  signal huffman_ins_v2_code_black_0_mux0000 : STD_LOGIC;
750 
  signal huffman_ins_v2_code_black_10_mux0000 : STD_LOGIC;
751 
  signal huffman_ins_v2_code_black_10_mux000010_1516 : STD_LOGIC;
752 
  signal huffman_ins_v2_code_black_10_mux00001103_1517 : STD_LOGIC;
753 
  signal huffman_ins_v2_code_black_10_mux00001116_1518 : STD_LOGIC;
754 
  signal huffman_ins_v2_code_black_10_mux0000115_1519 : STD_LOGIC;
755 
  signal huffman_ins_v2_code_black_10_mux0000152 : STD_LOGIC;
756 
  signal huffman_ins_v2_code_black_10_mux00001521_1521 : STD_LOGIC;
757 
  signal huffman_ins_v2_code_black_10_mux00001522_1522 : STD_LOGIC;
758 
  signal huffman_ins_v2_code_black_10_mux0000_bdd2 : STD_LOGIC;
759 
  signal huffman_ins_v2_code_black_10_mux0000_bdd3 : STD_LOGIC;
760 
  signal huffman_ins_v2_code_black_10_mux0000_bdd4 : STD_LOGIC;
761 
  signal huffman_ins_v2_code_black_10_mux0000_bdd5 : STD_LOGIC;
762 
  signal huffman_ins_v2_code_black_11_mux0000 : STD_LOGIC;
763 
  signal huffman_ins_v2_code_black_11_mux00001107_1529 : STD_LOGIC;
764 
  signal huffman_ins_v2_code_black_11_mux0000112_1530 : STD_LOGIC;
765 
  signal huffman_ins_v2_code_black_11_mux0000143 : STD_LOGIC;
766 
  signal huffman_ins_v2_code_black_11_mux00001431_1532 : STD_LOGIC;
767 
  signal huffman_ins_v2_code_black_11_mux00001432_1533 : STD_LOGIC;
768 
  signal huffman_ins_v2_code_black_11_mux0000_bdd0 : STD_LOGIC;
769 
  signal huffman_ins_v2_code_black_11_mux0000_bdd2 : STD_LOGIC;
770 
  signal huffman_ins_v2_code_black_11_mux0000_bdd3 : STD_LOGIC;
771 
  signal huffman_ins_v2_code_black_11_mux0000_bdd5 : STD_LOGIC;
772 
  signal huffman_ins_v2_code_black_12_mux0000 : STD_LOGIC;
773 
  signal huffman_ins_v2_code_black_12_mux00001107_1540 : STD_LOGIC;
774 
  signal huffman_ins_v2_code_black_12_mux0000112_1541 : STD_LOGIC;
775 
  signal huffman_ins_v2_code_black_12_mux0000143 : STD_LOGIC;
776 
  signal huffman_ins_v2_code_black_12_mux00001431_1543 : STD_LOGIC;
777 
  signal huffman_ins_v2_code_black_12_mux00001432_1544 : STD_LOGIC;
778 
  signal huffman_ins_v2_code_black_13_mux0000 : STD_LOGIC;
779 
  signal huffman_ins_v2_code_black_13_mux00001107_1547 : STD_LOGIC;
780 
  signal huffman_ins_v2_code_black_13_mux0000112_1548 : STD_LOGIC;
781 
  signal huffman_ins_v2_code_black_13_mux0000143 : STD_LOGIC;
782 
  signal huffman_ins_v2_code_black_13_mux00001431_1550 : STD_LOGIC;
783 
  signal huffman_ins_v2_code_black_13_mux00001432_1551 : STD_LOGIC;
784 
  signal huffman_ins_v2_code_black_14_mux0000 : STD_LOGIC;
785 
  signal huffman_ins_v2_code_black_14_mux00001107_1554 : STD_LOGIC;
786 
  signal huffman_ins_v2_code_black_14_mux0000112_1555 : STD_LOGIC;
787 
  signal huffman_ins_v2_code_black_14_mux0000143 : STD_LOGIC;
788 
  signal huffman_ins_v2_code_black_14_mux00001431_1557 : STD_LOGIC;
789 
  signal huffman_ins_v2_code_black_14_mux00001432_1558 : STD_LOGIC;
790 
  signal huffman_ins_v2_code_black_15_mux0000 : STD_LOGIC;
791 
  signal huffman_ins_v2_code_black_15_mux00001107 : STD_LOGIC;
792 
  signal huffman_ins_v2_code_black_15_mux000011071_1562 : STD_LOGIC;
793 
  signal huffman_ins_v2_code_black_15_mux000011072_1563 : STD_LOGIC;
794 
  signal huffman_ins_v2_code_black_15_mux0000112_1564 : STD_LOGIC;
795 
  signal huffman_ins_v2_code_black_15_mux0000143 : STD_LOGIC;
796 
  signal huffman_ins_v2_code_black_15_mux00001431_1566 : STD_LOGIC;
797 
  signal huffman_ins_v2_code_black_15_mux00001432_1567 : STD_LOGIC;
798 
  signal huffman_ins_v2_code_black_15_mux0000_bdd1 : STD_LOGIC;
799 
  signal huffman_ins_v2_code_black_16_mux0000 : STD_LOGIC;
800 
  signal huffman_ins_v2_code_black_16_mux00001 : STD_LOGIC;
801 
  signal huffman_ins_v2_code_black_16_mux000011_1572 : STD_LOGIC;
802 
  signal huffman_ins_v2_code_black_16_mux000012_1573 : STD_LOGIC;
803 
  signal huffman_ins_v2_code_black_16_mux00001_f5_1574 : STD_LOGIC;
804 
  signal huffman_ins_v2_code_black_17_mux0000 : STD_LOGIC;
805 
  signal huffman_ins_v2_code_black_17_mux00001 : STD_LOGIC;
806 
  signal huffman_ins_v2_code_black_17_mux000011_1578 : STD_LOGIC;
807 
  signal huffman_ins_v2_code_black_17_mux000012_1579 : STD_LOGIC;
808 
  signal huffman_ins_v2_code_black_17_mux000013_1580 : STD_LOGIC;
809 
  signal huffman_ins_v2_code_black_17_mux00001_f5_1581 : STD_LOGIC;
810 
  signal huffman_ins_v2_code_black_17_mux00001_f51 : STD_LOGIC;
811 
  signal huffman_ins_v2_code_black_18_mux0000 : STD_LOGIC;
812 
  signal huffman_ins_v2_code_black_18_mux00001 : STD_LOGIC;
813 
  signal huffman_ins_v2_code_black_18_mux000011_1586 : STD_LOGIC;
814 
  signal huffman_ins_v2_code_black_18_mux000012_1587 : STD_LOGIC;
815 
  signal huffman_ins_v2_code_black_18_mux00001_f5_1588 : STD_LOGIC;
816 
  signal huffman_ins_v2_code_black_19_mux0000 : STD_LOGIC;
817 
  signal huffman_ins_v2_code_black_19_mux00001 : STD_LOGIC;
818 
  signal huffman_ins_v2_code_black_19_mux000011_1592 : STD_LOGIC;
819 
  signal huffman_ins_v2_code_black_19_mux00001_f5_1593 : STD_LOGIC;
820 
  signal huffman_ins_v2_code_black_19_mux00001_f5_rt_1594 : STD_LOGIC;
821 
  signal huffman_ins_v2_code_black_1_mux0000 : STD_LOGIC;
822 
  signal huffman_ins_v2_code_black_20_mux0000166_1598 : STD_LOGIC;
823 
  signal huffman_ins_v2_code_black_20_mux0000187_1599 : STD_LOGIC;
824 
  signal huffman_ins_v2_code_black_21_mux0000 : STD_LOGIC;
825 
  signal huffman_ins_v2_code_black_21_mux00001 : STD_LOGIC;
826 
  signal huffman_ins_v2_code_black_21_mux000011_1603 : STD_LOGIC;
827 
  signal huffman_ins_v2_code_black_21_mux000012_1604 : STD_LOGIC;
828 
  signal huffman_ins_v2_code_black_21_mux00001_f5_1605 : STD_LOGIC;
829 
  signal huffman_ins_v2_code_black_22_mux0000112_1607 : STD_LOGIC;
830 
  signal huffman_ins_v2_code_black_22_mux0000123 : STD_LOGIC;
831 
  signal huffman_ins_v2_code_black_22_mux0000128_1609 : STD_LOGIC;
832 
  signal huffman_ins_v2_code_black_22_mux0000169_1610 : STD_LOGIC;
833 
  signal huffman_ins_v2_code_black_22_mux0000172 : STD_LOGIC;
834 
  signal huffman_ins_v2_code_black_23_mux0000112_1613 : STD_LOGIC;
835 
  signal huffman_ins_v2_code_black_23_mux0000128_1614 : STD_LOGIC;
836 
  signal huffman_ins_v2_code_black_23_mux0000169_1615 : STD_LOGIC;
837 
  signal huffman_ins_v2_code_black_23_mux0000172 : STD_LOGIC;
838 
  signal huffman_ins_v2_code_black_24_mux0000 : STD_LOGIC;
839 
  signal huffman_ins_v2_code_black_2_mux0000 : STD_LOGIC;
840 
  signal huffman_ins_v2_code_black_2_mux00002 : STD_LOGIC;
841 
  signal huffman_ins_v2_code_black_2_mux000021_1621 : STD_LOGIC;
842 
  signal huffman_ins_v2_code_black_2_mux000022_1622 : STD_LOGIC;
843 
  signal huffman_ins_v2_code_black_2_mux000023_1623 : STD_LOGIC;
844 
  signal huffman_ins_v2_code_black_2_mux00002_f5_1624 : STD_LOGIC;
845 
  signal huffman_ins_v2_code_black_2_mux00002_f51 : STD_LOGIC;
846 
  signal huffman_ins_v2_code_black_3_mux0000 : STD_LOGIC;
847 
  signal huffman_ins_v2_code_black_3_mux00001 : STD_LOGIC;
848 
  signal huffman_ins_v2_code_black_3_mux000011_1629 : STD_LOGIC;
849 
  signal huffman_ins_v2_code_black_3_mux000012_1630 : STD_LOGIC;
850 
  signal huffman_ins_v2_code_black_3_mux000013_1631 : STD_LOGIC;
851 
  signal huffman_ins_v2_code_black_3_mux00001_f5_1632 : STD_LOGIC;
852 
  signal huffman_ins_v2_code_black_3_mux00001_f51 : STD_LOGIC;
853 
  signal huffman_ins_v2_code_black_4_mux0000 : STD_LOGIC;
854 
  signal huffman_ins_v2_code_black_4_mux00001 : STD_LOGIC;
855 
  signal huffman_ins_v2_code_black_4_mux000011_1637 : STD_LOGIC;
856 
  signal huffman_ins_v2_code_black_4_mux000012_1638 : STD_LOGIC;
857 
  signal huffman_ins_v2_code_black_4_mux000013_1639 : STD_LOGIC;
858 
  signal huffman_ins_v2_code_black_4_mux00001_f5_1640 : STD_LOGIC;
859 
  signal huffman_ins_v2_code_black_4_mux00001_f51 : STD_LOGIC;
860 
  signal huffman_ins_v2_code_black_5_mux0000 : STD_LOGIC;
861 
  signal huffman_ins_v2_code_black_5_mux00001 : STD_LOGIC;
862 
  signal huffman_ins_v2_code_black_5_mux000011_1645 : STD_LOGIC;
863 
  signal huffman_ins_v2_code_black_5_mux000012_1646 : STD_LOGIC;
864 
  signal huffman_ins_v2_code_black_5_mux000013_1647 : STD_LOGIC;
865 
  signal huffman_ins_v2_code_black_5_mux00001_f5_1648 : STD_LOGIC;
866 
  signal huffman_ins_v2_code_black_5_mux00001_f51 : STD_LOGIC;
867 
  signal huffman_ins_v2_code_black_6_mux0000 : STD_LOGIC;
868 
  signal huffman_ins_v2_code_black_6_mux00002126_1652 : STD_LOGIC;
869 
  signal huffman_ins_v2_code_black_6_mux00002155 : STD_LOGIC;
870 
  signal huffman_ins_v2_code_black_6_mux0000282_1654 : STD_LOGIC;
871 
  signal huffman_ins_v2_code_black_7_mux0000 : STD_LOGIC;
872 
  signal huffman_ins_v2_code_black_7_mux00001 : STD_LOGIC;
873 
  signal huffman_ins_v2_code_black_7_mux000011_1658 : STD_LOGIC;
874 
  signal huffman_ins_v2_code_black_7_mux000012_1659 : STD_LOGIC;
875 
  signal huffman_ins_v2_code_black_7_mux000013_1660 : STD_LOGIC;
876 
  signal huffman_ins_v2_code_black_7_mux00001_f5_1661 : STD_LOGIC;
877 
  signal huffman_ins_v2_code_black_7_mux00001_f51 : STD_LOGIC;
878 
  signal huffman_ins_v2_code_black_8_mux0000 : STD_LOGIC;
879 
  signal huffman_ins_v2_code_black_8_mux00001126_1665 : STD_LOGIC;
880 
  signal huffman_ins_v2_code_black_8_mux0000172_1666 : STD_LOGIC;
881 
  signal huffman_ins_v2_code_black_9_mux0000 : STD_LOGIC;
882 
  signal huffman_ins_v2_code_black_9_mux00002107_1669 : STD_LOGIC;
883 
  signal huffman_ins_v2_code_black_9_mux0000212_1670 : STD_LOGIC;
884 
  signal huffman_ins_v2_code_black_9_mux0000243 : STD_LOGIC;
885 
  signal huffman_ins_v2_code_black_9_mux00002431_1672 : STD_LOGIC;
886 
  signal huffman_ins_v2_code_black_9_mux00002432_1673 : STD_LOGIC;
887 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00011 : STD_LOGIC;
888 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux0001101 : STD_LOGIC;
889 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000112 : STD_LOGIC;
890 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000115 : STD_LOGIC;
891 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00012 : STD_LOGIC;
892 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00013 : STD_LOGIC;
893 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00014 : STD_LOGIC;
894 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00015 : STD_LOGIC;
895 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000161 : STD_LOGIC;
896 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000171 : STD_LOGIC;
897 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001 : STD_LOGIC;
898 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00011 : STD_LOGIC;
899 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001101 : STD_LOGIC;
900 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00011111 : STD_LOGIC;
901 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001121 : STD_LOGIC;
902 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00012 : STD_LOGIC;
903 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00013 : STD_LOGIC;
904 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00014 : STD_LOGIC;
905 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00015 : STD_LOGIC;
906 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000161 : STD_LOGIC;
907 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00017 : STD_LOGIC;
908 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000181 : STD_LOGIC;
909 
  signal huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00019 : STD_LOGIC;
910 
  signal huffman_ins_v2_code_table_ins_makeup_black_0_Q : STD_LOGIC;
911 
  signal huffman_ins_v2_code_table_ins_makeup_black_1_Q : STD_LOGIC;
912 
  signal huffman_ins_v2_code_table_ins_makeup_black_13_Q : STD_LOGIC;
913 
  signal huffman_ins_v2_code_table_ins_makeup_black_14_Q : STD_LOGIC;
914 
  signal huffman_ins_v2_code_table_ins_makeup_black_15_Q : STD_LOGIC;
915 
  signal huffman_ins_v2_code_table_ins_makeup_black_16_Q : STD_LOGIC;
916 
  signal huffman_ins_v2_code_table_ins_makeup_black_2_Q : STD_LOGIC;
917 
  signal huffman_ins_v2_code_table_ins_makeup_black_3_Q : STD_LOGIC;
918 
  signal huffman_ins_v2_code_table_ins_makeup_black_4_Q : STD_LOGIC;
919 
  signal huffman_ins_v2_code_table_ins_makeup_black_5_Q : STD_LOGIC;
920 
  signal huffman_ins_v2_code_table_ins_makeup_black_6_Q : STD_LOGIC;
921 
  signal huffman_ins_v2_code_table_ins_makeup_black_7_Q : STD_LOGIC;
922 
  signal huffman_ins_v2_code_table_ins_makeup_black_8_Q : STD_LOGIC;
923 
  signal huffman_ins_v2_code_white_0_mux0000 : STD_LOGIC;
924 
  signal huffman_ins_v2_code_white_10_mux000010_1735 : STD_LOGIC;
925 
  signal huffman_ins_v2_code_white_10_mux000021_1736 : STD_LOGIC;
926 
  signal huffman_ins_v2_code_white_10_mux00004_1737 : STD_LOGIC;
927 
  signal huffman_ins_v2_code_white_10_mux00009_1738 : STD_LOGIC;
928 
  signal huffman_ins_v2_code_white_11_mux000010_1740 : STD_LOGIC;
929 
  signal huffman_ins_v2_code_white_11_mux000021_1741 : STD_LOGIC;
930 
  signal huffman_ins_v2_code_white_11_mux00004_1742 : STD_LOGIC;
931 
  signal huffman_ins_v2_code_white_11_mux00009_1743 : STD_LOGIC;
932 
  signal huffman_ins_v2_code_white_12_mux000010_1745 : STD_LOGIC;
933 
  signal huffman_ins_v2_code_white_12_mux000021_1746 : STD_LOGIC;
934 
  signal huffman_ins_v2_code_white_12_mux00004_1747 : STD_LOGIC;
935 
  signal huffman_ins_v2_code_white_12_mux00009_1748 : STD_LOGIC;
936 
  signal huffman_ins_v2_code_white_13_mux000015_1750 : STD_LOGIC;
937 
  signal huffman_ins_v2_code_white_13_mux00006_1751 : STD_LOGIC;
938 
  signal huffman_ins_v2_code_white_14_mux000014 : STD_LOGIC;
939 
  signal huffman_ins_v2_code_white_14_mux00004_1754 : STD_LOGIC;
940 
  signal huffman_ins_v2_code_white_15_mux00001_1756 : STD_LOGIC;
941 
  signal huffman_ins_v2_code_white_16_mux0000 : STD_LOGIC;
942 
  signal huffman_ins_v2_code_white_1_mux0000 : STD_LOGIC;
943 
  signal huffman_ins_v2_code_white_2_mux0000 : STD_LOGIC;
944 
  signal huffman_ins_v2_code_white_3_mux0000 : STD_LOGIC;
945 
  signal huffman_ins_v2_code_white_4_mux000016_1765 : STD_LOGIC;
946 
  signal huffman_ins_v2_code_white_4_mux000028 : STD_LOGIC;
947 
  signal huffman_ins_v2_code_white_4_mux0000281_1767 : STD_LOGIC;
948 
  signal huffman_ins_v2_code_white_4_mux0000282_1768 : STD_LOGIC;
949 
  signal huffman_ins_v2_code_white_4_mux000039_1769 : STD_LOGIC;
950 
  signal huffman_ins_v2_code_white_5_mux000028 : STD_LOGIC;
951 
  signal huffman_ins_v2_code_white_5_mux0000281_1772 : STD_LOGIC;
952 
  signal huffman_ins_v2_code_white_5_mux0000282_1773 : STD_LOGIC;
953 
  signal huffman_ins_v2_code_white_5_mux000039_1774 : STD_LOGIC;
954 
  signal huffman_ins_v2_code_white_6_mux000014_1776 : STD_LOGIC;
955 
  signal huffman_ins_v2_code_white_6_mux000021_1777 : STD_LOGIC;
956 
  signal huffman_ins_v2_code_white_6_mux00004_1778 : STD_LOGIC;
957 
  signal huffman_ins_v2_code_white_7_mux000010_1780 : STD_LOGIC;
958 
  signal huffman_ins_v2_code_white_7_mux000021_1781 : STD_LOGIC;
959 
  signal huffman_ins_v2_code_white_7_mux00004_1782 : STD_LOGIC;
960 
  signal huffman_ins_v2_code_white_7_mux00009_1783 : STD_LOGIC;
961 
  signal huffman_ins_v2_code_white_8_cmp_eq0000 : STD_LOGIC;
962 
  signal huffman_ins_v2_code_white_8_cmp_eq0001 : STD_LOGIC;
963 
  signal huffman_ins_v2_code_white_8_cmp_eq0004 : STD_LOGIC;
964 
  signal huffman_ins_v2_code_white_8_mux000010_1788 : STD_LOGIC;
965 
  signal huffman_ins_v2_code_white_8_mux000021_1789 : STD_LOGIC;
966 
  signal huffman_ins_v2_code_white_8_mux00004_1790 : STD_LOGIC;
967 
  signal huffman_ins_v2_code_white_8_mux00009_1791 : STD_LOGIC;
968 
  signal huffman_ins_v2_code_white_8_or0000 : STD_LOGIC;
969 
  signal huffman_ins_v2_code_white_9_mux000010_1794 : STD_LOGIC;
970 
  signal huffman_ins_v2_code_white_9_mux000021_1795 : STD_LOGIC;
971 
  signal huffman_ins_v2_code_white_9_mux00004_1796 : STD_LOGIC;
972 
  signal huffman_ins_v2_code_white_9_mux00009_1797 : STD_LOGIC;
973 
  signal huffman_ins_v2_frame_finished_o_1814 : STD_LOGIC;
974 
  signal huffman_ins_v2_hor_code_0_mux000310_1816 : STD_LOGIC;
975 
  signal huffman_ins_v2_hor_code_0_mux000322_1817 : STD_LOGIC;
976 
  signal huffman_ins_v2_hor_code_0_mux000324_1818 : STD_LOGIC;
977 
  signal huffman_ins_v2_hor_code_0_mux000352_1819 : STD_LOGIC;
978 
  signal huffman_ins_v2_hor_code_10_mux0003112_1822 : STD_LOGIC;
979 
  signal huffman_ins_v2_hor_code_10_mux000329_1823 : STD_LOGIC;
980 
  signal huffman_ins_v2_hor_code_10_mux000359_1824 : STD_LOGIC;
981 
  signal huffman_ins_v2_hor_code_10_mux000362_1825 : STD_LOGIC;
982 
  signal huffman_ins_v2_hor_code_10_mux000369_1826 : STD_LOGIC;
983 
  signal huffman_ins_v2_hor_code_10_mux000393_1827 : STD_LOGIC;
984 
  signal huffman_ins_v2_hor_code_10_mux000399_1828 : STD_LOGIC;
985 
  signal huffman_ins_v2_hor_code_11_mux0003121 : STD_LOGIC;
986 
  signal huffman_ins_v2_hor_code_11_mux0003129_1831 : STD_LOGIC;
987 
  signal huffman_ins_v2_hor_code_11_mux0003141 : STD_LOGIC;
988 
  signal huffman_ins_v2_hor_code_11_mux000321_1833 : STD_LOGIC;
989 
  signal huffman_ins_v2_hor_code_11_mux000338_1834 : STD_LOGIC;
990 
  signal huffman_ins_v2_hor_code_11_mux000373_1835 : STD_LOGIC;
991 
  signal huffman_ins_v2_hor_code_11_mux000374_1836 : STD_LOGIC;
992 
  signal huffman_ins_v2_hor_code_12_mux0003104_1838 : STD_LOGIC;
993 
  signal huffman_ins_v2_hor_code_12_mux000311_1839 : STD_LOGIC;
994 
  signal huffman_ins_v2_hor_code_12_mux0003117_1840 : STD_LOGIC;
995 
  signal huffman_ins_v2_hor_code_12_mux0003135_1841 : STD_LOGIC;
996 
  signal huffman_ins_v2_hor_code_12_mux0003163_1842 : STD_LOGIC;
997 
  signal huffman_ins_v2_hor_code_12_mux0003175_1843 : STD_LOGIC;
998 
  signal huffman_ins_v2_hor_code_12_mux0003216_1844 : STD_LOGIC;
999 
  signal huffman_ins_v2_hor_code_12_mux0003219_1845 : STD_LOGIC;
1000 
  signal huffman_ins_v2_hor_code_12_mux000324_1846 : STD_LOGIC;
1001 
  signal huffman_ins_v2_hor_code_12_mux0003249_1847 : STD_LOGIC;
1002 
  signal huffman_ins_v2_hor_code_12_mux000339_1848 : STD_LOGIC;
1003 
  signal huffman_ins_v2_hor_code_12_mux000364_1849 : STD_LOGIC;
1004 
  signal huffman_ins_v2_hor_code_13_cmp_eq0000 : STD_LOGIC;
1005 
  signal huffman_ins_v2_hor_code_13_mux0003137_1852 : STD_LOGIC;
1006 
  signal huffman_ins_v2_hor_code_13_mux0003161_1853 : STD_LOGIC;
1007 
  signal huffman_ins_v2_hor_code_13_mux0003181_1854 : STD_LOGIC;
1008 
  signal huffman_ins_v2_hor_code_13_mux0003198 : STD_LOGIC;
1009 
  signal huffman_ins_v2_hor_code_13_mux000320_1856 : STD_LOGIC;
1010 
  signal huffman_ins_v2_hor_code_13_mux000325_1857 : STD_LOGIC;
1011 
  signal huffman_ins_v2_hor_code_13_mux000350_1858 : STD_LOGIC;
1012 
  signal huffman_ins_v2_hor_code_13_mux000386_1859 : STD_LOGIC;
1013 
  signal huffman_ins_v2_hor_code_13_mux000389_1860 : STD_LOGIC;
1014 
  signal huffman_ins_v2_hor_code_13_mux00039_1861 : STD_LOGIC;
1015 
  signal huffman_ins_v2_hor_code_13_or0003 : STD_LOGIC;
1016 
  signal huffman_ins_v2_hor_code_13_or0005 : STD_LOGIC;
1017 
  signal huffman_ins_v2_hor_code_14_mux0003117_1865 : STD_LOGIC;
1018 
  signal huffman_ins_v2_hor_code_14_mux0003126_1866 : STD_LOGIC;
1019 
  signal huffman_ins_v2_hor_code_14_mux0003139_1867 : STD_LOGIC;
1020 
  signal huffman_ins_v2_hor_code_14_mux0003155_1868 : STD_LOGIC;
1021 
  signal huffman_ins_v2_hor_code_14_mux0003173_1869 : STD_LOGIC;
1022 
  signal huffman_ins_v2_hor_code_14_mux0003186_1870 : STD_LOGIC;
1023 
  signal huffman_ins_v2_hor_code_14_mux0003203_1871 : STD_LOGIC;
1024 
  signal huffman_ins_v2_hor_code_14_mux0003213_1872 : STD_LOGIC;
1025 
  signal huffman_ins_v2_hor_code_14_mux0003227_1873 : STD_LOGIC;
1026 
  signal huffman_ins_v2_hor_code_14_mux0003256_1874 : STD_LOGIC;
1027 
  signal huffman_ins_v2_hor_code_14_mux0003264_1875 : STD_LOGIC;
1028 
  signal huffman_ins_v2_hor_code_14_mux000327_1876 : STD_LOGIC;
1029 
  signal huffman_ins_v2_hor_code_14_mux0003277_1877 : STD_LOGIC;
1030 
  signal huffman_ins_v2_hor_code_14_mux0003301_1878 : STD_LOGIC;
1031 
  signal huffman_ins_v2_hor_code_14_mux000343_1879 : STD_LOGIC;
1032 
  signal huffman_ins_v2_hor_code_14_mux000371_1880 : STD_LOGIC;
1033 
  signal huffman_ins_v2_hor_code_14_mux000379_1881 : STD_LOGIC;
1034 
  signal huffman_ins_v2_hor_code_14_mux00038_1882 : STD_LOGIC;
1035 
  signal huffman_ins_v2_hor_code_15_mux0003122_1884 : STD_LOGIC;
1036 
  signal huffman_ins_v2_hor_code_15_mux0003157 : STD_LOGIC;
1037 
  signal huffman_ins_v2_hor_code_15_mux000321 : STD_LOGIC;
1038 
  signal huffman_ins_v2_hor_code_15_mux000326_1887 : STD_LOGIC;
1039 
  signal huffman_ins_v2_hor_code_15_mux00035_1888 : STD_LOGIC;
1040 
  signal huffman_ins_v2_hor_code_15_mux000355 : STD_LOGIC;
1041 
  signal huffman_ins_v2_hor_code_15_mux0003551_1890 : STD_LOGIC;
1042 
  signal huffman_ins_v2_hor_code_15_mux0003552_1891 : STD_LOGIC;
1043 
  signal huffman_ins_v2_hor_code_15_mux000378_1892 : STD_LOGIC;
1044 
  signal huffman_ins_v2_hor_code_15_mux00038_1893 : STD_LOGIC;
1045 
  signal huffman_ins_v2_hor_code_15_mux000380_1894 : STD_LOGIC;
1046 
  signal huffman_ins_v2_hor_code_16_mux0003102_1896 : STD_LOGIC;
1047 
  signal huffman_ins_v2_hor_code_16_mux0003117_1897 : STD_LOGIC;
1048 
  signal huffman_ins_v2_hor_code_16_mux0003136_1898 : STD_LOGIC;
1049 
  signal huffman_ins_v2_hor_code_16_mux0003138_1899 : STD_LOGIC;
1050 
  signal huffman_ins_v2_hor_code_16_mux000359_1900 : STD_LOGIC;
1051 
  signal huffman_ins_v2_hor_code_16_mux000393_1901 : STD_LOGIC;
1052 
  signal huffman_ins_v2_hor_code_16_mux000394_1902 : STD_LOGIC;
1053 
  signal huffman_ins_v2_hor_code_17_mux0003110_1904 : STD_LOGIC;
1054 
  signal huffman_ins_v2_hor_code_17_mux0003153 : STD_LOGIC;
1055 
  signal huffman_ins_v2_hor_code_17_mux00031531 : STD_LOGIC;
1056 
  signal huffman_ins_v2_hor_code_17_mux000316_1907 : STD_LOGIC;
1057 
  signal huffman_ins_v2_hor_code_17_mux000319_1908 : STD_LOGIC;
1058 
  signal huffman_ins_v2_hor_code_17_mux000350_1909 : STD_LOGIC;
1059 
  signal huffman_ins_v2_hor_code_17_mux000353_1910 : STD_LOGIC;
1060 
  signal huffman_ins_v2_hor_code_17_mux000371_1911 : STD_LOGIC;
1061 
  signal huffman_ins_v2_hor_code_17_mux000378_1912 : STD_LOGIC;
1062 
  signal huffman_ins_v2_hor_code_18_and0001 : STD_LOGIC;
1063 
  signal huffman_ins_v2_hor_code_18_mux0003127_1915 : STD_LOGIC;
1064 
  signal huffman_ins_v2_hor_code_18_mux0003130_1916 : STD_LOGIC;
1065 
  signal huffman_ins_v2_hor_code_18_mux0003164_1917 : STD_LOGIC;
1066 
  signal huffman_ins_v2_hor_code_18_mux0003181_1918 : STD_LOGIC;
1067 
  signal huffman_ins_v2_hor_code_18_mux0003199_1919 : STD_LOGIC;
1068 
  signal huffman_ins_v2_hor_code_18_mux0003230_1920 : STD_LOGIC;
1069 
  signal huffman_ins_v2_hor_code_18_mux000328_1921 : STD_LOGIC;
1070 
  signal huffman_ins_v2_hor_code_18_mux000346_1922 : STD_LOGIC;
1071 
  signal huffman_ins_v2_hor_code_18_mux000381_1923 : STD_LOGIC;
1072 
  signal huffman_ins_v2_hor_code_19_mux0003138_1925 : STD_LOGIC;
1073 
  signal huffman_ins_v2_hor_code_19_mux000323_1926 : STD_LOGIC;
1074 
  signal huffman_ins_v2_hor_code_19_mux00036_1927 : STD_LOGIC;
1075 
  signal huffman_ins_v2_hor_code_19_mux000380_1928 : STD_LOGIC;
1076 
  signal huffman_ins_v2_hor_code_1_mux0003116_1929 : STD_LOGIC;
1077 
  signal huffman_ins_v2_hor_code_1_mux0003120_1930 : STD_LOGIC;
1078 
  signal huffman_ins_v2_hor_code_1_mux000339_1931 : STD_LOGIC;
1079 
  signal huffman_ins_v2_hor_code_1_mux000347_1932 : STD_LOGIC;
1080 
  signal huffman_ins_v2_hor_code_1_mux000354_1933 : STD_LOGIC;
1081 
  signal huffman_ins_v2_hor_code_1_mux000379_1934 : STD_LOGIC;
1082 
  signal huffman_ins_v2_hor_code_1_mux000386_1935 : STD_LOGIC;
1083 
  signal huffman_ins_v2_hor_code_20_mux00030_1938 : STD_LOGIC;
1084 
  signal huffman_ins_v2_hor_code_20_mux0003105_1939 : STD_LOGIC;
1085 
  signal huffman_ins_v2_hor_code_20_mux0003127_1940 : STD_LOGIC;
1086 
  signal huffman_ins_v2_hor_code_20_mux0003145_1941 : STD_LOGIC;
1087 
  signal huffman_ins_v2_hor_code_20_mux000315_1942 : STD_LOGIC;
1088 
  signal huffman_ins_v2_hor_code_20_mux0003158_1943 : STD_LOGIC;
1089 
  signal huffman_ins_v2_hor_code_20_mux0003171 : STD_LOGIC;
1090 
  signal huffman_ins_v2_hor_code_20_mux000346_1945 : STD_LOGIC;
1091 
  signal huffman_ins_v2_hor_code_20_mux000350_1946 : STD_LOGIC;
1092 
  signal huffman_ins_v2_hor_code_20_mux000370_1947 : STD_LOGIC;
1093 
  signal huffman_ins_v2_hor_code_21_mux000310_1949 : STD_LOGIC;
1094 
  signal huffman_ins_v2_hor_code_21_mux0003123_1950 : STD_LOGIC;
1095 
  signal huffman_ins_v2_hor_code_21_mux0003168_1951 : STD_LOGIC;
1096 
  signal huffman_ins_v2_hor_code_21_mux0003179_1952 : STD_LOGIC;
1097 
  signal huffman_ins_v2_hor_code_21_mux000334_1953 : STD_LOGIC;
1098 
  signal huffman_ins_v2_hor_code_21_mux000335_1954 : STD_LOGIC;
1099 
  signal huffman_ins_v2_hor_code_21_mux000376_1955 : STD_LOGIC;
1100 
  signal huffman_ins_v2_hor_code_21_mux000379_1956 : STD_LOGIC;
1101 
  signal huffman_ins_v2_hor_code_21_mux000395_1957 : STD_LOGIC;
1102 
  signal huffman_ins_v2_hor_code_22_mux0003112_1959 : STD_LOGIC;
1103 
  signal huffman_ins_v2_hor_code_22_mux0003135_1960 : STD_LOGIC;
1104 
  signal huffman_ins_v2_hor_code_22_mux000317_1961 : STD_LOGIC;
1105 
  signal huffman_ins_v2_hor_code_22_mux000320_1962 : STD_LOGIC;
1106 
  signal huffman_ins_v2_hor_code_22_mux000360_1963 : STD_LOGIC;
1107 
  signal huffman_ins_v2_hor_code_22_mux000375_1964 : STD_LOGIC;
1108 
  signal huffman_ins_v2_hor_code_22_mux000385_1965 : STD_LOGIC;
1109 
  signal huffman_ins_v2_hor_code_23_and0000 : STD_LOGIC;
1110 
  signal huffman_ins_v2_hor_code_23_mux000322_1968 : STD_LOGIC;
1111 
  signal huffman_ins_v2_hor_code_23_mux000356_1969 : STD_LOGIC;
1112 
  signal huffman_ins_v2_hor_code_23_mux000373 : STD_LOGIC;
1113 
  signal huffman_ins_v2_hor_code_23_mux00039_1971 : STD_LOGIC;
1114 
  signal huffman_ins_v2_hor_code_24_mux000312_1973 : STD_LOGIC;
1115 
  signal huffman_ins_v2_hor_code_24_mux000316_1974 : STD_LOGIC;
1116 
  signal huffman_ins_v2_hor_code_24_mux000335_1975 : STD_LOGIC;
1117 
  signal huffman_ins_v2_hor_code_24_mux000348_1976 : STD_LOGIC;
1118 
  signal huffman_ins_v2_hor_code_24_mux000371_1977 : STD_LOGIC;
1119 
  signal huffman_ins_v2_hor_code_25_mux00030_1979 : STD_LOGIC;
1120 
  signal huffman_ins_v2_hor_code_25_mux0003112 : STD_LOGIC;
1121 
  signal huffman_ins_v2_hor_code_25_mux000342_1981 : STD_LOGIC;
1122 
  signal huffman_ins_v2_hor_code_25_mux000380_1982 : STD_LOGIC;
1123 
  signal huffman_ins_v2_hor_code_2_mux0003104_1983 : STD_LOGIC;
1124 
  signal huffman_ins_v2_hor_code_2_mux0003117_1984 : STD_LOGIC;
1125 
  signal huffman_ins_v2_hor_code_2_mux0003129 : STD_LOGIC;
1126 
  signal huffman_ins_v2_hor_code_2_mux000330_1986 : STD_LOGIC;
1127 
  signal huffman_ins_v2_hor_code_2_mux000335_1987 : STD_LOGIC;
1128 
  signal huffman_ins_v2_hor_code_2_mux000379_1988 : STD_LOGIC;
1129 
  signal huffman_ins_v2_hor_code_2_mux000385_1989 : STD_LOGIC;
1130 
  signal huffman_ins_v2_hor_code_3_mux000318_1991 : STD_LOGIC;
1131 
  signal huffman_ins_v2_hor_code_3_mux00033_1992 : STD_LOGIC;
1132 
  signal huffman_ins_v2_hor_code_3_mux000340_1993 : STD_LOGIC;
1133 
  signal huffman_ins_v2_hor_code_3_mux000342_1994 : STD_LOGIC;
1134 
  signal huffman_ins_v2_hor_code_3_mux000397_1995 : STD_LOGIC;
1135 
  signal huffman_ins_v2_hor_code_4_mux000310_1997 : STD_LOGIC;
1136 
  signal huffman_ins_v2_hor_code_4_mux0003110 : STD_LOGIC;
1137 
  signal huffman_ins_v2_hor_code_4_mux00033_1999 : STD_LOGIC;
1138 
  signal huffman_ins_v2_hor_code_4_mux000331_2000 : STD_LOGIC;
1139 
  signal huffman_ins_v2_hor_code_4_mux000333_2001 : STD_LOGIC;
1140 
  signal huffman_ins_v2_hor_code_4_mux000358_2002 : STD_LOGIC;
1141 
  signal huffman_ins_v2_hor_code_4_mux000384_2003 : STD_LOGIC;
1142 
  signal huffman_ins_v2_hor_code_4_mux000388_2004 : STD_LOGIC;
1143 
  signal huffman_ins_v2_hor_code_5_mux0003102 : STD_LOGIC;
1144 
  signal huffman_ins_v2_hor_code_5_mux000315_2007 : STD_LOGIC;
1145 
  signal huffman_ins_v2_hor_code_5_mux000327_2008 : STD_LOGIC;
1146 
  signal huffman_ins_v2_hor_code_5_mux000349_2009 : STD_LOGIC;
1147 
  signal huffman_ins_v2_hor_code_5_mux00037_2010 : STD_LOGIC;
1148 
  signal huffman_ins_v2_hor_code_5_mux000376_2011 : STD_LOGIC;
1149 
  signal huffman_ins_v2_hor_code_5_mux000380_2012 : STD_LOGIC;
1150 
  signal huffman_ins_v2_hor_code_6_mux000310_2014 : STD_LOGIC;
1151 
  signal huffman_ins_v2_hor_code_6_mux000327_2015 : STD_LOGIC;
1152 
  signal huffman_ins_v2_hor_code_6_mux000329_2016 : STD_LOGIC;
1153 
  signal huffman_ins_v2_hor_code_6_mux000343_2017 : STD_LOGIC;
1154 
  signal huffman_ins_v2_hor_code_6_mux000361_2018 : STD_LOGIC;
1155 
  signal huffman_ins_v2_hor_code_6_mux000367_2019 : STD_LOGIC;
1156 
  signal huffman_ins_v2_hor_code_6_mux000371 : STD_LOGIC;
1157 
  signal huffman_ins_v2_hor_code_7_mux000324_2022 : STD_LOGIC;
1158 
  signal huffman_ins_v2_hor_code_7_mux000325_2023 : STD_LOGIC;
1159 
  signal huffman_ins_v2_hor_code_7_mux00035_2024 : STD_LOGIC;
1160 
  signal huffman_ins_v2_hor_code_7_mux000356_2025 : STD_LOGIC;
1161 
  signal huffman_ins_v2_hor_code_7_mux000368_2026 : STD_LOGIC;
1162 
  signal huffman_ins_v2_hor_code_7_mux000370_2027 : STD_LOGIC;
1163 
  signal huffman_ins_v2_hor_code_7_mux000381 : STD_LOGIC;
1164 
  signal huffman_ins_v2_hor_code_8_mux0003129_2030 : STD_LOGIC;
1165 
  signal huffman_ins_v2_hor_code_8_mux000313_2031 : STD_LOGIC;
1166 
  signal huffman_ins_v2_hor_code_8_mux0003149_2032 : STD_LOGIC;
1167 
  signal huffman_ins_v2_hor_code_8_mux0003151_2033 : STD_LOGIC;
1168 
  signal huffman_ins_v2_hor_code_8_mux0003165 : STD_LOGIC;
1169 
  signal huffman_ins_v2_hor_code_8_mux000327_2035 : STD_LOGIC;
1170 
  signal huffman_ins_v2_hor_code_8_mux000341_2036 : STD_LOGIC;
1171 
  signal huffman_ins_v2_hor_code_8_mux000390_2037 : STD_LOGIC;
1172 
  signal huffman_ins_v2_hor_code_8_mux000392_2038 : STD_LOGIC;
1173 
  signal huffman_ins_v2_hor_code_9_mux0003104_2040 : STD_LOGIC;
1174 
  signal huffman_ins_v2_hor_code_9_mux0003114_2041 : STD_LOGIC;
1175 
  signal huffman_ins_v2_hor_code_9_mux000313_2042 : STD_LOGIC;
1176 
  signal huffman_ins_v2_hor_code_9_mux0003147 : STD_LOGIC;
1177 
  signal huffman_ins_v2_hor_code_9_mux000320_2044 : STD_LOGIC;
1178 
  signal huffman_ins_v2_hor_code_9_mux000342_2045 : STD_LOGIC;
1179 
  signal huffman_ins_v2_hor_code_9_mux000366 : STD_LOGIC;
1180 
  signal huffman_ins_v2_hor_code_9_mux0003661_2047 : STD_LOGIC;
1181 
  signal huffman_ins_v2_hor_code_9_mux0003662_2048 : STD_LOGIC;
1182 
  signal huffman_ins_v2_hor_code_9_mux000398_2049 : STD_LOGIC;
1183 
  signal huffman_ins_v2_horizontal_mode_1_2060 : STD_LOGIC;
1184 
  signal huffman_ins_v2_horizontal_mode_1_cmp_eq0001 : STD_LOGIC;
1185 
  signal huffman_ins_v2_horizontal_mode_1_or0000 : STD_LOGIC;
1186 
  signal huffman_ins_v2_horizontal_mode_3_2063 : STD_LOGIC;
1187 
  signal huffman_ins_v2_horizontal_mode_part_1_2064 : STD_LOGIC;
1188 
  signal huffman_ins_v2_horizontal_mode_part_2_2065 : STD_LOGIC;
1189 
  signal huffman_ins_v2_pass_vert_code_width_1_0_Q : STD_LOGIC;
1190 
  signal huffman_ins_v2_pass_vert_code_width_1_2_Q : STD_LOGIC;
1191 
  signal huffman_ins_v2_pass_vert_code_width_3_0_Q : STD_LOGIC;
1192 
  signal huffman_ins_v2_pass_vert_code_width_3_2_Q : STD_LOGIC;
1193 
  signal huffman_ins_v2_run_len_code_valid_o_2082 : STD_LOGIC;
1194 
  signal huffman_ins_v2_run_length_white_0_1_2094 : STD_LOGIC;
1195 
  signal huffman_ins_v2_run_length_white_0_2_2095 : STD_LOGIC;
1196 
  signal huffman_ins_v2_run_length_white_1_1_2097 : STD_LOGIC;
1197 
  signal huffman_ins_v2_run_length_white_1_2_2098 : STD_LOGIC;
1198 
  signal huffman_ins_v2_run_length_white_2_1_2100 : STD_LOGIC;
1199 
  signal huffman_ins_v2_run_length_white_2_2_2101 : STD_LOGIC;
1200 
  signal huffman_ins_v2_run_length_white_3_1_2103 : STD_LOGIC;
1201 
  signal huffman_ins_v2_run_length_white_3_2_2104 : STD_LOGIC;
1202 
  signal huffman_ins_v2_run_length_white_4_1_2106 : STD_LOGIC;
1203 
  signal huffman_ins_v2_run_length_white_4_2_2107 : STD_LOGIC;
1204 
  signal huffman_ins_v2_run_length_white_5_1_2109 : STD_LOGIC;
1205 
  signal huffman_ins_v2_run_length_white_5_2_2110 : STD_LOGIC;
1206 
  signal huffman_ins_v2_run_length_white_6_1_2112 : STD_LOGIC;
1207 
  signal huffman_ins_v2_run_length_white_6_2_2113 : STD_LOGIC;
1208 
  signal huffman_ins_v2_run_length_white_7_1_2115 : STD_LOGIC;
1209 
  signal huffman_ins_v2_run_length_white_7_2_2116 : STD_LOGIC;
1210 
  signal huffman_ins_v2_run_length_white_8_1_2118 : STD_LOGIC;
1211 
  signal huffman_ins_v2_run_length_white_8_2_2119 : STD_LOGIC;
1212 
  signal huffman_ins_v2_run_length_white_9_1_2121 : STD_LOGIC;
1213 
  signal huffman_ins_v2_run_length_white_9_2_2122 : STD_LOGIC;
1214 
  signal huffman_ins_v2_run_length_white_and0000 : STD_LOGIC;
1215 
  signal huffman_ins_v2_run_length_white_and000020_2134 : STD_LOGIC;
1216 
  signal huffman_ins_v2_run_length_white_and000043_2135 : STD_LOGIC;
1217 
  signal huffman_ins_v2_run_length_white_and00007_2136 : STD_LOGIC;
1218 
  signal NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DO_15_UNCONNECTED : STD_LOGIC;
1219 
  signal NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DO_14_UNCONNECTED : STD_LOGIC;
1220 
  signal NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DO_13_UNCONNECTED : STD_LOGIC;
1221 
  signal NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DO_12_UNCONNECTED : STD_LOGIC;
1222 
  signal NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DOP_1_UNCONNECTED : STD_LOGIC;
1223 
  signal NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DOP_0_UNCONNECTED : STD_LOGIC;
1224 
  signal NLW_huffman_ins_v2_code_table_ins_Mrom_black_code_mux0001_DOP_1_UNCONNECTED : STD_LOGIC;
1225 
  signal NLW_huffman_ins_v2_code_table_ins_Mrom_black_code_mux0001_DOP_0_UNCONNECTED : STD_LOGIC;
1226 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_15_UNCONNECTED : STD_LOGIC;
1227 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_14_UNCONNECTED : STD_LOGIC;
1228 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_13_UNCONNECTED : STD_LOGIC;
1229 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_12_UNCONNECTED : STD_LOGIC;
1230 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_11_UNCONNECTED : STD_LOGIC;
1231 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_10_UNCONNECTED : STD_LOGIC;
1232 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_9_UNCONNECTED : STD_LOGIC;
1233 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_8_UNCONNECTED : STD_LOGIC;
1234 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_7_UNCONNECTED : STD_LOGIC;
1235 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_6_UNCONNECTED : STD_LOGIC;
1236 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_5_UNCONNECTED : STD_LOGIC;
1237 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_4_UNCONNECTED : STD_LOGIC;
1238 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_3_UNCONNECTED : STD_LOGIC;
1239 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_2_UNCONNECTED : STD_LOGIC;
1240 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_1_UNCONNECTED : STD_LOGIC;
1241 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_0_UNCONNECTED : STD_LOGIC;
1242 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIPB_1_UNCONNECTED : STD_LOGIC;
1243 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIPB_0_UNCONNECTED : STD_LOGIC;
1244 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_15_UNCONNECTED : STD_LOGIC;
1245 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_14_UNCONNECTED : STD_LOGIC;
1246 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_13_UNCONNECTED : STD_LOGIC;
1247 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_12_UNCONNECTED : STD_LOGIC;
1248 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_11_UNCONNECTED : STD_LOGIC;
1249 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_10_UNCONNECTED : STD_LOGIC;
1250 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_9_UNCONNECTED : STD_LOGIC;
1251 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_8_UNCONNECTED : STD_LOGIC;
1252 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_7_UNCONNECTED : STD_LOGIC;
1253 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_6_UNCONNECTED : STD_LOGIC;
1254 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_5_UNCONNECTED : STD_LOGIC;
1255 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_4_UNCONNECTED : STD_LOGIC;
1256 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_3_UNCONNECTED : STD_LOGIC;
1257 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_2_UNCONNECTED : STD_LOGIC;
1258 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_1_UNCONNECTED : STD_LOGIC;
1259 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_0_UNCONNECTED : STD_LOGIC;
1260 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOPA_1_UNCONNECTED : STD_LOGIC;
1261 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOPA_0_UNCONNECTED : STD_LOGIC;
1262 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOB_15_UNCONNECTED : STD_LOGIC;
1263 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOB_14_UNCONNECTED : STD_LOGIC;
1264 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOB_13_UNCONNECTED : STD_LOGIC;
1265 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOB_12_UNCONNECTED : STD_LOGIC;
1266 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOB_11_UNCONNECTED : STD_LOGIC;
1267 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOPB_1_UNCONNECTED : STD_LOGIC;
1268 
  signal NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOPB_0_UNCONNECTED : STD_LOGIC;
1269 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_15_UNCONNECTED : STD_LOGIC;
1270 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_14_UNCONNECTED : STD_LOGIC;
1271 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_13_UNCONNECTED : STD_LOGIC;
1272 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_12_UNCONNECTED : STD_LOGIC;
1273 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_11_UNCONNECTED : STD_LOGIC;
1274 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_10_UNCONNECTED : STD_LOGIC;
1275 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_9_UNCONNECTED : STD_LOGIC;
1276 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_8_UNCONNECTED : STD_LOGIC;
1277 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_7_UNCONNECTED : STD_LOGIC;
1278 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_6_UNCONNECTED : STD_LOGIC;
1279 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_5_UNCONNECTED : STD_LOGIC;
1280 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_4_UNCONNECTED : STD_LOGIC;
1281 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_3_UNCONNECTED : STD_LOGIC;
1282 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_2_UNCONNECTED : STD_LOGIC;
1283 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_1_UNCONNECTED : STD_LOGIC;
1284 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_0_UNCONNECTED : STD_LOGIC;
1285 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIPB_1_UNCONNECTED : STD_LOGIC;
1286 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIPB_0_UNCONNECTED : STD_LOGIC;
1287 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_15_UNCONNECTED : STD_LOGIC;
1288 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_14_UNCONNECTED : STD_LOGIC;
1289 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_13_UNCONNECTED : STD_LOGIC;
1290 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_12_UNCONNECTED : STD_LOGIC;
1291 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_11_UNCONNECTED : STD_LOGIC;
1292 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_10_UNCONNECTED : STD_LOGIC;
1293 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_9_UNCONNECTED : STD_LOGIC;
1294 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_8_UNCONNECTED : STD_LOGIC;
1295 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_7_UNCONNECTED : STD_LOGIC;
1296 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_6_UNCONNECTED : STD_LOGIC;
1297 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_5_UNCONNECTED : STD_LOGIC;
1298 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_4_UNCONNECTED : STD_LOGIC;
1299 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_3_UNCONNECTED : STD_LOGIC;
1300 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_2_UNCONNECTED : STD_LOGIC;
1301 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_1_UNCONNECTED : STD_LOGIC;
1302 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_0_UNCONNECTED : STD_LOGIC;
1303 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOPA_1_UNCONNECTED : STD_LOGIC;
1304 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOPA_0_UNCONNECTED : STD_LOGIC;
1305 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOB_15_UNCONNECTED : STD_LOGIC;
1306 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOB_14_UNCONNECTED : STD_LOGIC;
1307 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOB_13_UNCONNECTED : STD_LOGIC;
1308 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOB_12_UNCONNECTED : STD_LOGIC;
1309 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOB_11_UNCONNECTED : STD_LOGIC;
1310 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOPB_1_UNCONNECTED : STD_LOGIC;
1311 
  signal NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOPB_0_UNCONNECTED : STD_LOGIC;
1312 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
1313 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
1314 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
1315 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
1316 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
1317 
  signal fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
1318 
  signal fax4_ins_FIFO1_multi_read_ins_Result : STD_LOGIC_VECTOR ( 9 downto 0 );
1319 
  signal fax4_ins_FIFO1_multi_read_ins_data1_o : STD_LOGIC_VECTOR ( 9 downto 0 );
1320 
  signal fax4_ins_FIFO1_multi_read_ins_data2_o : STD_LOGIC_VECTOR ( 9 downto 0 );
1321 
  signal fax4_ins_FIFO1_multi_read_ins_data3_o : STD_LOGIC_VECTOR ( 9 downto 0 );
1322 
  signal fax4_ins_FIFO1_multi_read_ins_mem_data_out : STD_LOGIC_VECTOR ( 10 downto 0 );
1323 
  signal fax4_ins_FIFO1_multi_read_ins_mux1_x : STD_LOGIC_VECTOR ( 9 downto 0 );
1324 
  signal fax4_ins_FIFO1_multi_read_ins_mux2_x : STD_LOGIC_VECTOR ( 9 downto 0 );
1325 
  signal fax4_ins_FIFO1_multi_read_ins_mux3_x : STD_LOGIC_VECTOR ( 9 downto 0 );
1326 
  signal fax4_ins_FIFO1_multi_read_ins_read_pos : STD_LOGIC_VECTOR ( 9 downto 0 );
1327 
  signal fax4_ins_FIFO1_multi_read_ins_used : STD_LOGIC_VECTOR ( 9 downto 0 );
1328 
  signal fax4_ins_FIFO1_multi_read_ins_write_pos : STD_LOGIC_VECTOR ( 9 downto 0 );
1329 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
1330 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
1331 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
1332 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
1333 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
1334 
  signal fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
1335 
  signal fax4_ins_FIFO2_multi_read_ins_Result : STD_LOGIC_VECTOR ( 9 downto 0 );
1336 
  signal fax4_ins_FIFO2_multi_read_ins_data1_o : STD_LOGIC_VECTOR ( 9 downto 0 );
1337 
  signal fax4_ins_FIFO2_multi_read_ins_data2_o : STD_LOGIC_VECTOR ( 9 downto 0 );
1338 
  signal fax4_ins_FIFO2_multi_read_ins_data3_o : STD_LOGIC_VECTOR ( 9 downto 0 );
1339 
  signal fax4_ins_FIFO2_multi_read_ins_mem_data_out : STD_LOGIC_VECTOR ( 10 downto 0 );
1340 
  signal fax4_ins_FIFO2_multi_read_ins_mux1_x : STD_LOGIC_VECTOR ( 9 downto 0 );
1341 
  signal fax4_ins_FIFO2_multi_read_ins_mux2_x : STD_LOGIC_VECTOR ( 9 downto 0 );
1342 
  signal fax4_ins_FIFO2_multi_read_ins_mux3_x : STD_LOGIC_VECTOR ( 9 downto 0 );
1343 
  signal fax4_ins_FIFO2_multi_read_ins_read_pos : STD_LOGIC_VECTOR ( 9 downto 0 );
1344 
  signal fax4_ins_FIFO2_multi_read_ins_used : STD_LOGIC_VECTOR ( 9 downto 0 );
1345 
  signal fax4_ins_FIFO2_multi_read_ins_write_pos : STD_LOGIC_VECTOR ( 9 downto 0 );
1346 
  signal fax4_ins_Madd_a1b1_addsub0001_cy : STD_LOGIC_VECTOR ( 9 downto 1 );
1347 
  signal fax4_ins_Madd_fifo_rd_addsub0000_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
1348 
  signal fax4_ins_Madd_fifo_rd_addsub0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
1349 
  signal fax4_ins_Madd_vertical_mode_addsub0000_cy : STD_LOGIC_VECTOR ( 9 downto 0 );
1350 
  signal fax4_ins_Madd_vertical_mode_not0000 : STD_LOGIC_VECTOR ( 10 downto 1 );
1351 
  signal fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy : STD_LOGIC_VECTOR ( 9 downto 0 );
1352 
  signal fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
1353 
  signal fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy : STD_LOGIC_VECTOR ( 9 downto 0 );
1354 
  signal fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
1355 
  signal fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy : STD_LOGIC_VECTOR ( 9 downto 0 );
1356 
  signal fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
1357 
  signal fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy : STD_LOGIC_VECTOR ( 9 downto 0 );
1358 
  signal fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
1359 
  signal fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy : STD_LOGIC_VECTOR ( 9 downto 0 );
1360 
  signal fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
1361 
  signal fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy : STD_LOGIC_VECTOR ( 9 downto 0 );
1362 
  signal fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
1363 
  signal fax4_ins_Msub_a1b1_addsub0000_cy : STD_LOGIC_VECTOR ( 9 downto 0 );
1364 
  signal fax4_ins_Msub_a1b1_addsub0000_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
1365 
  signal fax4_ins_a0 : STD_LOGIC_VECTOR ( 9 downto 0 );
1366 
  signal fax4_ins_a0_mux0000 : STD_LOGIC_VECTOR ( 9 downto 0 );
1367 
  signal fax4_ins_a0_o : STD_LOGIC_VECTOR ( 9 downto 0 );
1368 
  signal fax4_ins_a1_o : STD_LOGIC_VECTOR ( 9 downto 0 );
1369 
  signal fax4_ins_a1_o_mux0000 : STD_LOGIC_VECTOR ( 9 downto 0 );
1370 
  signal fax4_ins_a1b1 : STD_LOGIC_VECTOR ( 10 downto 0 );
1371 
  signal fax4_ins_a1b1_addsub0000 : STD_LOGIC_VECTOR ( 10 downto 0 );
1372 
  signal fax4_ins_a1b1_addsub0001 : STD_LOGIC_VECTOR ( 10 downto 1 );
1373 
  signal fax4_ins_a2_o : STD_LOGIC_VECTOR ( 9 downto 0 );
1374 
  signal fax4_ins_b1 : STD_LOGIC_VECTOR ( 9 downto 0 );
1375 
  signal fax4_ins_b1_mux0004 : STD_LOGIC_VECTOR ( 9 downto 0 );
1376 
  signal fax4_ins_b2 : STD_LOGIC_VECTOR ( 9 downto 0 );
1377 
  signal fax4_ins_b2_mux0004 : STD_LOGIC_VECTOR ( 9 downto 0 );
1378 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
1379 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
1380 
  signal NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt : STD_LOGIC_VECTOR ( 9 downto 0 );
1381 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000 : STD_LOGIC_VECTOR ( 9 downto 0 );
1382 
  signal fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000 : STD_LOGIC_VECTOR ( 9 downto 0 );
1383 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
1384 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
1385 
  signal NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt : STD_LOGIC_VECTOR ( 8 downto 0 );
1386 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000 : STD_LOGIC_VECTOR ( 8 downto 0 );
1387 
  signal fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000 : STD_LOGIC_VECTOR ( 8 downto 0 );
1388 
  signal fax4_ins_fifo_out1_x : STD_LOGIC_VECTOR ( 9 downto 0 );
1389 
  signal fax4_ins_fifo_out2_x : STD_LOGIC_VECTOR ( 9 downto 0 );
1390 
  signal fax4_ins_fifo_out_prev1_x : STD_LOGIC_VECTOR ( 9 downto 0 );
1391 
  signal fax4_ins_fifo_out_prev2_x : STD_LOGIC_VECTOR ( 9 downto 0 );
1392 
  signal fax4_ins_fifo_rd_addsub0000 : STD_LOGIC_VECTOR ( 9 downto 0 );
1393 
  signal fax4_ins_mode_indicator_o : STD_LOGIC_VECTOR ( 3 downto 0 );
1394 
  signal fax4_ins_mode_indicator_o_mux0001 : STD_LOGIC_VECTOR ( 3 downto 3 );
1395 
  signal fax4_ins_mux_b1 : STD_LOGIC_VECTOR ( 3 downto 0 );
1396 
  signal fax4_ins_vertical_mode_addsub0000 : STD_LOGIC_VECTOR ( 10 downto 2 );
1397 
  signal huffman_ins_v2_Madd_code_black_width_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
1398 
  signal huffman_ins_v2_Madd_code_white_width_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
1399 
  signal huffman_ins_v2_Madd_hor_code_width_addsub0000_cy : STD_LOGIC_VECTOR ( 1 downto 0 );
1400 
  signal huffman_ins_v2_Madd_hor_code_width_addsub0000_lut : STD_LOGIC_VECTOR ( 4 downto 2 );
1401 
  signal huffman_ins_v2_Msub_run_length_white_addsub0000_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
1402 
  signal huffman_ins_v2_Msub_run_length_white_addsub0000_lut : STD_LOGIC_VECTOR ( 9 downto 1 );
1403 
  signal huffman_ins_v2_Msub_run_length_white_sub0000_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
1404 
  signal huffman_ins_v2_Msub_run_length_white_sub0000_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
1405 
  signal huffman_ins_v2_Msub_run_length_white_sub0001_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
1406 
  signal huffman_ins_v2_Msub_run_length_white_sub0001_lut : STD_LOGIC_VECTOR ( 9 downto 0 );
1407 
  signal huffman_ins_v2_code_black : STD_LOGIC_VECTOR ( 24 downto 0 );
1408 
  signal huffman_ins_v2_code_black_width : STD_LOGIC_VECTOR ( 4 downto 0 );
1409 
  signal huffman_ins_v2_code_black_width_add0000 : STD_LOGIC_VECTOR ( 3 downto 1 );
1410 
  signal huffman_ins_v2_code_table_ins_makeup_white : STD_LOGIC_VECTOR ( 12 downto 0 );
1411 
  signal huffman_ins_v2_code_white : STD_LOGIC_VECTOR ( 16 downto 0 );
1412 
  signal huffman_ins_v2_code_white_width : STD_LOGIC_VECTOR ( 4 downto 0 );
1413 
  signal huffman_ins_v2_code_white_width_add0000 : STD_LOGIC_VECTOR ( 3 downto 1 );
1414 
  signal huffman_ins_v2_codetab_ter_black_width : STD_LOGIC_VECTOR ( 3 downto 0 );
1415 
  signal huffman_ins_v2_codetab_ter_white_width : STD_LOGIC_VECTOR ( 3 downto 0 );
1416 
  signal huffman_ins_v2_hor_code : STD_LOGIC_VECTOR ( 25 downto 0 );
1417 
  signal huffman_ins_v2_hor_code_width : STD_LOGIC_VECTOR ( 4 downto 0 );
1418 
  signal huffman_ins_v2_hor_code_width_mux0001 : STD_LOGIC_VECTOR ( 4 downto 0 );
1419 
  signal huffman_ins_v2_mux_code_black_width : STD_LOGIC_VECTOR ( 4 downto 0 );
1420 
  signal huffman_ins_v2_mux_code_white_width : STD_LOGIC_VECTOR ( 1 downto 1 );
1421 
  signal huffman_ins_v2_pass_vert_code_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
1422 
  signal huffman_ins_v2_pass_vert_code_3 : STD_LOGIC_VECTOR ( 2 downto 0 );
1423 
  signal huffman_ins_v2_run_length_black : STD_LOGIC_VECTOR ( 9 downto 0 );
1424 
  signal huffman_ins_v2_run_length_white : STD_LOGIC_VECTOR ( 9 downto 0 );
1425 
  signal huffman_ins_v2_run_length_white_addsub0000 : STD_LOGIC_VECTOR ( 9 downto 0 );
1426 
  signal huffman_ins_v2_run_length_white_sub0000 : STD_LOGIC_VECTOR ( 9 downto 0 );
1427 
  signal huffman_ins_v2_run_length_white_sub0001 : STD_LOGIC_VECTOR ( 9 downto 0 );
1428 
  signal huffman_ins_v2_ter_black_code : STD_LOGIC_VECTOR ( 11 downto 0 );
1429 
  signal huffman_ins_v2_ter_white_code : STD_LOGIC_VECTOR ( 7 downto 0 );
1430 
  signal NlwRenamedSig_OI_run_len_code_o : STD_LOGIC_VECTOR ( 26 downto 26 );
1431 
begin
1432 
  frame_finished_o <= huffman_ins_v2_frame_finished_o_1814;
1433 
  run_len_code_valid_o <= huffman_ins_v2_run_len_code_valid_o_2082;
1434 
  run_len_code_o(27) <= NlwRenamedSig_OI_run_len_code_o(26);
1435 
  run_len_code_o(26) <= NlwRenamedSig_OI_run_len_code_o(26);
1436 
  fax4_x(9) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9);
1437 
  fax4_x(8) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8);
1438 
  fax4_x(7) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7);
1439 
  fax4_x(6) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6);
1440 
  fax4_x(5) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5);
1441 
  fax4_x(4) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4);
1442 
  fax4_x(3) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3);
1443 
  fax4_x(2) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2);
1444 
  fax4_x(1) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1);
1445 
  fax4_x(0) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0);
1446 
  fax4_y(8) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(8);
1447 
  fax4_y(7) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(7);
1448 
  fax4_y(6) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(6);
1449 
  fax4_y(5) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(5);
1450 
  fax4_y(4) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(4);
1451 
  fax4_y(3) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(3);
1452 
  fax4_y(2) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(2);
1453 
  fax4_y(1) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(1);
1454 
  fax4_y(0) <= NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0);
1455 
  XST_GND : GND
1456 
    port map (
1457 
      G => NlwRenamedSig_OI_run_len_code_o(26)
1458 
    );
1459 
  XST_VCC : VCC
1460 
    port map (
1461 
      P => N1
1462 
    );
1463 
  huffman_ins_v2_code_table_ins_makeup_white_0 : FD
1464 
    generic map(
1465 
      INIT => '0'
1466 
    )
1467 
    port map (
1468 
      C => pclk_i,
1469 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001,
1470 
      Q => huffman_ins_v2_code_table_ins_makeup_white(0)
1471 
    );
1472 
  huffman_ins_v2_code_table_ins_makeup_white_1 : FD
1473 
    generic map(
1474 
      INIT => '0'
1475 
    )
1476 
    port map (
1477 
      C => pclk_i,
1478 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00011,
1479 
      Q => huffman_ins_v2_code_table_ins_makeup_white(1)
1480 
    );
1481 
  huffman_ins_v2_code_table_ins_makeup_white_2 : FD
1482 
    generic map(
1483 
      INIT => '0'
1484 
    )
1485 
    port map (
1486 
      C => pclk_i,
1487 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00012,
1488 
      Q => huffman_ins_v2_code_table_ins_makeup_white(2)
1489 
    );
1490 
  huffman_ins_v2_code_table_ins_makeup_white_3 : FD
1491 
    generic map(
1492 
      INIT => '0'
1493 
    )
1494 
    port map (
1495 
      C => pclk_i,
1496 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00013,
1497 
      Q => huffman_ins_v2_code_table_ins_makeup_white(3)
1498 
    );
1499 
  huffman_ins_v2_code_table_ins_makeup_white_4 : FD
1500 
    generic map(
1501 
      INIT => '0'
1502 
    )
1503 
    port map (
1504 
      C => pclk_i,
1505 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00014,
1506 
      Q => huffman_ins_v2_code_table_ins_makeup_white(4)
1507 
    );
1508 
  huffman_ins_v2_code_table_ins_makeup_white_5 : FD
1509 
    generic map(
1510 
      INIT => '0'
1511 
    )
1512 
    port map (
1513 
      C => pclk_i,
1514 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00015,
1515 
      Q => huffman_ins_v2_code_table_ins_makeup_white(5)
1516 
    );
1517 
  huffman_ins_v2_code_table_ins_makeup_white_7 : FD
1518 
    generic map(
1519 
      INIT => '0'
1520 
    )
1521 
    port map (
1522 
      C => pclk_i,
1523 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00017,
1524 
      Q => huffman_ins_v2_code_table_ins_makeup_white(7)
1525 
    );
1526 
  huffman_ins_v2_code_table_ins_makeup_white_9 : FD
1527 
    generic map(
1528 
      INIT => '0'
1529 
    )
1530 
    port map (
1531 
      C => pclk_i,
1532 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00019,
1533 
      Q => huffman_ins_v2_code_table_ins_makeup_white(9)
1534 
    );
1535 
  huffman_ins_v2_code_table_ins_makeup_black_1 : FD
1536 
    generic map(
1537 
      INIT => '0'
1538 
    )
1539 
    port map (
1540 
      C => pclk_i,
1541 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00011,
1542 
      Q => huffman_ins_v2_code_table_ins_makeup_black_1_Q
1543 
    );
1544 
  huffman_ins_v2_code_table_ins_makeup_black_2 : FD
1545 
    generic map(
1546 
      INIT => '0'
1547 
    )
1548 
    port map (
1549 
      C => pclk_i,
1550 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00012,
1551 
      Q => huffman_ins_v2_code_table_ins_makeup_black_2_Q
1552 
    );
1553 
  huffman_ins_v2_code_table_ins_makeup_black_3 : FD
1554 
    generic map(
1555 
      INIT => '0'
1556 
    )
1557 
    port map (
1558 
      C => pclk_i,
1559 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00013,
1560 
      Q => huffman_ins_v2_code_table_ins_makeup_black_3_Q
1561 
    );
1562 
  huffman_ins_v2_code_table_ins_makeup_black_4 : FD
1563 
    generic map(
1564 
      INIT => '0'
1565 
    )
1566 
    port map (
1567 
      C => pclk_i,
1568 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00014,
1569 
      Q => huffman_ins_v2_code_table_ins_makeup_black_4_Q
1570 
    );
1571 
  huffman_ins_v2_code_table_ins_makeup_black_5 : FD
1572 
    generic map(
1573 
      INIT => '0'
1574 
    )
1575 
    port map (
1576 
      C => pclk_i,
1577 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00015,
1578 
      Q => huffman_ins_v2_code_table_ins_makeup_black_5_Q
1579 
    );
1580 
  huffman_ins_v2_code_table_ins_makeup_black_13 : FD
1581 
    generic map(
1582 
      INIT => '0'
1583 
    )
1584 
    port map (
1585 
      C => pclk_i,
1586 
      D => huffman_ins_v2_run_length_black(9),
1587 
      Q => huffman_ins_v2_code_table_ins_makeup_black_13_Q
1588 
    );
1589 
  huffman_ins_v2_code_table_ins_makeup_black_15 : FD
1590 
    generic map(
1591 
      INIT => '0'
1592 
    )
1593 
    port map (
1594 
      C => pclk_i,
1595 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000115,
1596 
      Q => huffman_ins_v2_code_table_ins_makeup_black_15_Q
1597 
    );
1598 
  huffman_ins_v2_Msub_run_length_white_addsub0000_xor_9_Q : XORCY
1599 
    port map (
1600 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(8),
1601 
      LI => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(9),
1602 
      O => huffman_ins_v2_run_length_white_addsub0000(9)
1603 
    );
1604 
  huffman_ins_v2_Msub_run_length_white_addsub0000_xor_8_Q : XORCY
1605 
    port map (
1606 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(7),
1607 
      LI => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(8),
1608 
      O => huffman_ins_v2_run_length_white_addsub0000(8)
1609 
    );
1610 
  huffman_ins_v2_Msub_run_length_white_addsub0000_cy_8_Q : MUXCY
1611 
    port map (
1612 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(7),
1613 
      DI => N1,
1614 
      S => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(8),
1615 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(8)
1616 
    );
1617 
  huffman_ins_v2_Msub_run_length_white_addsub0000_xor_7_Q : XORCY
1618 
    port map (
1619 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(6),
1620 
      LI => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(7),
1621 
      O => huffman_ins_v2_run_length_white_addsub0000(7)
1622 
    );
1623 
  huffman_ins_v2_Msub_run_length_white_addsub0000_cy_7_Q : MUXCY
1624 
    port map (
1625 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(6),
1626 
      DI => N1,
1627 
      S => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(7),
1628 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(7)
1629 
    );
1630 
  huffman_ins_v2_Msub_run_length_white_addsub0000_xor_6_Q : XORCY
1631 
    port map (
1632 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(5),
1633 
      LI => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(6),
1634 
      O => huffman_ins_v2_run_length_white_addsub0000(6)
1635 
    );
1636 
  huffman_ins_v2_Msub_run_length_white_addsub0000_cy_6_Q : MUXCY
1637 
    port map (
1638 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(5),
1639 
      DI => N1,
1640 
      S => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(6),
1641 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(6)
1642 
    );
1643 
  huffman_ins_v2_Msub_run_length_white_addsub0000_xor_5_Q : XORCY
1644 
    port map (
1645 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(4),
1646 
      LI => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(5),
1647 
      O => huffman_ins_v2_run_length_white_addsub0000(5)
1648 
    );
1649 
  huffman_ins_v2_Msub_run_length_white_addsub0000_cy_5_Q : MUXCY
1650 
    port map (
1651 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(4),
1652 
      DI => N1,
1653 
      S => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(5),
1654 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(5)
1655 
    );
1656 
  huffman_ins_v2_Msub_run_length_white_addsub0000_xor_4_Q : XORCY
1657 
    port map (
1658 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(3),
1659 
      LI => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(4),
1660 
      O => huffman_ins_v2_run_length_white_addsub0000(4)
1661 
    );
1662 
  huffman_ins_v2_Msub_run_length_white_addsub0000_cy_4_Q : MUXCY
1663 
    port map (
1664 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(3),
1665 
      DI => N1,
1666 
      S => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(4),
1667 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(4)
1668 
    );
1669 
  huffman_ins_v2_Msub_run_length_white_addsub0000_xor_3_Q : XORCY
1670 
    port map (
1671 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(2),
1672 
      LI => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(3),
1673 
      O => huffman_ins_v2_run_length_white_addsub0000(3)
1674 
    );
1675 
  huffman_ins_v2_Msub_run_length_white_addsub0000_cy_3_Q : MUXCY
1676 
    port map (
1677 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(2),
1678 
      DI => N1,
1679 
      S => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(3),
1680 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(3)
1681 
    );
1682 
  huffman_ins_v2_Msub_run_length_white_addsub0000_xor_2_Q : XORCY
1683 
    port map (
1684 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(1),
1685 
      LI => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(2),
1686 
      O => huffman_ins_v2_run_length_white_addsub0000(2)
1687 
    );
1688 
  huffman_ins_v2_Msub_run_length_white_addsub0000_cy_2_Q : MUXCY
1689 
    port map (
1690 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(1),
1691 
      DI => N1,
1692 
      S => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(2),
1693 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(2)
1694 
    );
1695 
  huffman_ins_v2_Msub_run_length_white_addsub0000_xor_1_Q : XORCY
1696 
    port map (
1697 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(0),
1698 
      LI => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(1),
1699 
      O => huffman_ins_v2_run_length_white_addsub0000(1)
1700 
    );
1701 
  huffman_ins_v2_Msub_run_length_white_addsub0000_cy_1_Q : MUXCY
1702 
    port map (
1703 
      CI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(0),
1704 
      DI => N1,
1705 
      S => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(1),
1706 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(1)
1707 
    );
1708 
  huffman_ins_v2_Msub_run_length_white_addsub0000_xor_0_Q : XORCY
1709 
    port map (
1710 
      CI => N1,
1711 
      LI => huffman_ins_v2_Msub_run_length_white_addsub0000_cy_0_rt_1404,
1712 
      O => huffman_ins_v2_run_length_white_addsub0000(0)
1713 
    );
1714 
  huffman_ins_v2_Msub_run_length_white_addsub0000_cy_0_Q : MUXCY
1715 
    port map (
1716 
      CI => N1,
1717 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
1718 
      S => huffman_ins_v2_Msub_run_length_white_addsub0000_cy_0_rt_1404,
1719 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_cy(0)
1720 
    );
1721 
  huffman_ins_v2_Msub_run_length_white_sub0001_xor_9_Q : XORCY
1722 
    port map (
1723 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(8),
1724 
      LI => huffman_ins_v2_Msub_run_length_white_sub0001_lut(9),
1725 
      O => huffman_ins_v2_run_length_white_sub0001(9)
1726 
    );
1727 
  huffman_ins_v2_Msub_run_length_white_sub0001_lut_9_Q : LUT2
1728 
    generic map(
1729 
      INIT => X"9"
1730 
    )
1731 
    port map (
1732 
      I0 => fax4_ins_a2_o(9),
1733 
      I1 => fax4_ins_a1_o(9),
1734 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_lut(9)
1735 
    );
1736 
  huffman_ins_v2_Msub_run_length_white_sub0001_xor_8_Q : XORCY
1737 
    port map (
1738 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(7),
1739 
      LI => huffman_ins_v2_Msub_run_length_white_sub0001_lut(8),
1740 
      O => huffman_ins_v2_run_length_white_sub0001(8)
1741 
    );
1742 
  huffman_ins_v2_Msub_run_length_white_sub0001_cy_8_Q : MUXCY
1743 
    port map (
1744 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(7),
1745 
      DI => fax4_ins_a2_o(8),
1746 
      S => huffman_ins_v2_Msub_run_length_white_sub0001_lut(8),
1747 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_cy(8)
1748 
    );
1749 
  huffman_ins_v2_Msub_run_length_white_sub0001_lut_8_Q : LUT2
1750 
    generic map(
1751 
      INIT => X"9"
1752 
    )
1753 
    port map (
1754 
      I0 => fax4_ins_a2_o(8),
1755 
      I1 => fax4_ins_a1_o(8),
1756 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_lut(8)
1757 
    );
1758 
  huffman_ins_v2_Msub_run_length_white_sub0001_xor_7_Q : XORCY
1759 
    port map (
1760 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(6),
1761 
      LI => huffman_ins_v2_Msub_run_length_white_sub0001_lut(7),
1762 
      O => huffman_ins_v2_run_length_white_sub0001(7)
1763 
    );
1764 
  huffman_ins_v2_Msub_run_length_white_sub0001_cy_7_Q : MUXCY
1765 
    port map (
1766 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(6),
1767 
      DI => fax4_ins_a2_o(7),
1768 
      S => huffman_ins_v2_Msub_run_length_white_sub0001_lut(7),
1769 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_cy(7)
1770 
    );
1771 
  huffman_ins_v2_Msub_run_length_white_sub0001_lut_7_Q : LUT2
1772 
    generic map(
1773 
      INIT => X"9"
1774 
    )
1775 
    port map (
1776 
      I0 => fax4_ins_a2_o(7),
1777 
      I1 => fax4_ins_a1_o(7),
1778 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_lut(7)
1779 
    );
1780 
  huffman_ins_v2_Msub_run_length_white_sub0001_xor_6_Q : XORCY
1781 
    port map (
1782 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(5),
1783 
      LI => huffman_ins_v2_Msub_run_length_white_sub0001_lut(6),
1784 
      O => huffman_ins_v2_run_length_white_sub0001(6)
1785 
    );
1786 
  huffman_ins_v2_Msub_run_length_white_sub0001_cy_6_Q : MUXCY
1787 
    port map (
1788 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(5),
1789 
      DI => fax4_ins_a2_o(6),
1790 
      S => huffman_ins_v2_Msub_run_length_white_sub0001_lut(6),
1791 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_cy(6)
1792 
    );
1793 
  huffman_ins_v2_Msub_run_length_white_sub0001_lut_6_Q : LUT2
1794 
    generic map(
1795 
      INIT => X"9"
1796 
    )
1797 
    port map (
1798 
      I0 => fax4_ins_a2_o(6),
1799 
      I1 => fax4_ins_a1_o(6),
1800 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_lut(6)
1801 
    );
1802 
  huffman_ins_v2_Msub_run_length_white_sub0001_xor_5_Q : XORCY
1803 
    port map (
1804 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(4),
1805 
      LI => huffman_ins_v2_Msub_run_length_white_sub0001_lut(5),
1806 
      O => huffman_ins_v2_run_length_white_sub0001(5)
1807 
    );
1808 
  huffman_ins_v2_Msub_run_length_white_sub0001_cy_5_Q : MUXCY
1809 
    port map (
1810 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(4),
1811 
      DI => fax4_ins_a2_o(5),
1812 
      S => huffman_ins_v2_Msub_run_length_white_sub0001_lut(5),
1813 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_cy(5)
1814 
    );
1815 
  huffman_ins_v2_Msub_run_length_white_sub0001_lut_5_Q : LUT2
1816 
    generic map(
1817 
      INIT => X"9"
1818 
    )
1819 
    port map (
1820 
      I0 => fax4_ins_a2_o(5),
1821 
      I1 => fax4_ins_a1_o(5),
1822 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_lut(5)
1823 
    );
1824 
  huffman_ins_v2_Msub_run_length_white_sub0001_xor_4_Q : XORCY
1825 
    port map (
1826 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(3),
1827 
      LI => huffman_ins_v2_Msub_run_length_white_sub0001_lut(4),
1828 
      O => huffman_ins_v2_run_length_white_sub0001(4)
1829 
    );
1830 
  huffman_ins_v2_Msub_run_length_white_sub0001_cy_4_Q : MUXCY
1831 
    port map (
1832 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(3),
1833 
      DI => fax4_ins_a2_o(4),
1834 
      S => huffman_ins_v2_Msub_run_length_white_sub0001_lut(4),
1835 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_cy(4)
1836 
    );
1837 
  huffman_ins_v2_Msub_run_length_white_sub0001_lut_4_Q : LUT2
1838 
    generic map(
1839 
      INIT => X"9"
1840 
    )
1841 
    port map (
1842 
      I0 => fax4_ins_a2_o(4),
1843 
      I1 => fax4_ins_a1_o(4),
1844 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_lut(4)
1845 
    );
1846 
  huffman_ins_v2_Msub_run_length_white_sub0001_xor_3_Q : XORCY
1847 
    port map (
1848 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(2),
1849 
      LI => huffman_ins_v2_Msub_run_length_white_sub0001_lut(3),
1850 
      O => huffman_ins_v2_run_length_white_sub0001(3)
1851 
    );
1852 
  huffman_ins_v2_Msub_run_length_white_sub0001_cy_3_Q : MUXCY
1853 
    port map (
1854 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(2),
1855 
      DI => fax4_ins_a2_o(3),
1856 
      S => huffman_ins_v2_Msub_run_length_white_sub0001_lut(3),
1857 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_cy(3)
1858 
    );
1859 
  huffman_ins_v2_Msub_run_length_white_sub0001_lut_3_Q : LUT2
1860 
    generic map(
1861 
      INIT => X"9"
1862 
    )
1863 
    port map (
1864 
      I0 => fax4_ins_a2_o(3),
1865 
      I1 => fax4_ins_a1_o(3),
1866 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_lut(3)
1867 
    );
1868 
  huffman_ins_v2_Msub_run_length_white_sub0001_xor_2_Q : XORCY
1869 
    port map (
1870 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(1),
1871 
      LI => huffman_ins_v2_Msub_run_length_white_sub0001_lut(2),
1872 
      O => huffman_ins_v2_run_length_white_sub0001(2)
1873 
    );
1874 
  huffman_ins_v2_Msub_run_length_white_sub0001_cy_2_Q : MUXCY
1875 
    port map (
1876 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(1),
1877 
      DI => fax4_ins_a2_o(2),
1878 
      S => huffman_ins_v2_Msub_run_length_white_sub0001_lut(2),
1879 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_cy(2)
1880 
    );
1881 
  huffman_ins_v2_Msub_run_length_white_sub0001_lut_2_Q : LUT2
1882 
    generic map(
1883 
      INIT => X"9"
1884 
    )
1885 
    port map (
1886 
      I0 => fax4_ins_a2_o(2),
1887 
      I1 => fax4_ins_a1_o(2),
1888 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_lut(2)
1889 
    );
1890 
  huffman_ins_v2_Msub_run_length_white_sub0001_xor_1_Q : XORCY
1891 
    port map (
1892 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(0),
1893 
      LI => huffman_ins_v2_Msub_run_length_white_sub0001_lut(1),
1894 
      O => huffman_ins_v2_run_length_white_sub0001(1)
1895 
    );
1896 
  huffman_ins_v2_Msub_run_length_white_sub0001_cy_1_Q : MUXCY
1897 
    port map (
1898 
      CI => huffman_ins_v2_Msub_run_length_white_sub0001_cy(0),
1899 
      DI => fax4_ins_a2_o(1),
1900 
      S => huffman_ins_v2_Msub_run_length_white_sub0001_lut(1),
1901 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_cy(1)
1902 
    );
1903 
  huffman_ins_v2_Msub_run_length_white_sub0001_lut_1_Q : LUT2
1904 
    generic map(
1905 
      INIT => X"9"
1906 
    )
1907 
    port map (
1908 
      I0 => fax4_ins_a2_o(1),
1909 
      I1 => fax4_ins_a1_o(1),
1910 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_lut(1)
1911 
    );
1912 
  huffman_ins_v2_Msub_run_length_white_sub0001_xor_0_Q : XORCY
1913 
    port map (
1914 
      CI => N1,
1915 
      LI => huffman_ins_v2_Msub_run_length_white_sub0001_lut(0),
1916 
      O => huffman_ins_v2_run_length_white_sub0001(0)
1917 
    );
1918 
  huffman_ins_v2_Msub_run_length_white_sub0001_cy_0_Q : MUXCY
1919 
    port map (
1920 
      CI => N1,
1921 
      DI => fax4_ins_a2_o(0),
1922 
      S => huffman_ins_v2_Msub_run_length_white_sub0001_lut(0),
1923 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_cy(0)
1924 
    );
1925 
  huffman_ins_v2_Msub_run_length_white_sub0001_lut_0_Q : LUT2
1926 
    generic map(
1927 
      INIT => X"9"
1928 
    )
1929 
    port map (
1930 
      I0 => fax4_ins_a2_o(0),
1931 
      I1 => fax4_ins_a1_o(0),
1932 
      O => huffman_ins_v2_Msub_run_length_white_sub0001_lut(0)
1933 
    );
1934 
  huffman_ins_v2_Msub_run_length_white_sub0000_xor_9_Q : XORCY
1935 
    port map (
1936 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(8),
1937 
      LI => huffman_ins_v2_Msub_run_length_white_sub0000_lut(9),
1938 
      O => huffman_ins_v2_run_length_white_sub0000(9)
1939 
    );
1940 
  huffman_ins_v2_Msub_run_length_white_sub0000_lut_9_Q : LUT2
1941 
    generic map(
1942 
      INIT => X"9"
1943 
    )
1944 
    port map (
1945 
      I0 => fax4_ins_a1_o(9),
1946 
      I1 => fax4_ins_a0_o(9),
1947 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_lut(9)
1948 
    );
1949 
  huffman_ins_v2_Msub_run_length_white_sub0000_xor_8_Q : XORCY
1950 
    port map (
1951 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(7),
1952 
      LI => huffman_ins_v2_Msub_run_length_white_sub0000_lut(8),
1953 
      O => huffman_ins_v2_run_length_white_sub0000(8)
1954 
    );
1955 
  huffman_ins_v2_Msub_run_length_white_sub0000_cy_8_Q : MUXCY
1956 
    port map (
1957 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(7),
1958 
      DI => fax4_ins_a1_o(8),
1959 
      S => huffman_ins_v2_Msub_run_length_white_sub0000_lut(8),
1960 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_cy(8)
1961 
    );
1962 
  huffman_ins_v2_Msub_run_length_white_sub0000_lut_8_Q : LUT2
1963 
    generic map(
1964 
      INIT => X"9"
1965 
    )
1966 
    port map (
1967 
      I0 => fax4_ins_a1_o(8),
1968 
      I1 => fax4_ins_a0_o(8),
1969 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_lut(8)
1970 
    );
1971 
  huffman_ins_v2_Msub_run_length_white_sub0000_xor_7_Q : XORCY
1972 
    port map (
1973 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(6),
1974 
      LI => huffman_ins_v2_Msub_run_length_white_sub0000_lut(7),
1975 
      O => huffman_ins_v2_run_length_white_sub0000(7)
1976 
    );
1977 
  huffman_ins_v2_Msub_run_length_white_sub0000_cy_7_Q : MUXCY
1978 
    port map (
1979 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(6),
1980 
      DI => fax4_ins_a1_o(7),
1981 
      S => huffman_ins_v2_Msub_run_length_white_sub0000_lut(7),
1982 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_cy(7)
1983 
    );
1984 
  huffman_ins_v2_Msub_run_length_white_sub0000_lut_7_Q : LUT2
1985 
    generic map(
1986 
      INIT => X"9"
1987 
    )
1988 
    port map (
1989 
      I0 => fax4_ins_a1_o(7),
1990 
      I1 => fax4_ins_a0_o(7),
1991 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_lut(7)
1992 
    );
1993 
  huffman_ins_v2_Msub_run_length_white_sub0000_xor_6_Q : XORCY
1994 
    port map (
1995 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(5),
1996 
      LI => huffman_ins_v2_Msub_run_length_white_sub0000_lut(6),
1997 
      O => huffman_ins_v2_run_length_white_sub0000(6)
1998 
    );
1999 
  huffman_ins_v2_Msub_run_length_white_sub0000_cy_6_Q : MUXCY
2000 
    port map (
2001 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(5),
2002 
      DI => fax4_ins_a1_o(6),
2003 
      S => huffman_ins_v2_Msub_run_length_white_sub0000_lut(6),
2004 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_cy(6)
2005 
    );
2006 
  huffman_ins_v2_Msub_run_length_white_sub0000_lut_6_Q : LUT2
2007 
    generic map(
2008 
      INIT => X"9"
2009 
    )
2010 
    port map (
2011 
      I0 => fax4_ins_a1_o(6),
2012 
      I1 => fax4_ins_a0_o(6),
2013 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_lut(6)
2014 
    );
2015 
  huffman_ins_v2_Msub_run_length_white_sub0000_xor_5_Q : XORCY
2016 
    port map (
2017 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(4),
2018 
      LI => huffman_ins_v2_Msub_run_length_white_sub0000_lut(5),
2019 
      O => huffman_ins_v2_run_length_white_sub0000(5)
2020 
    );
2021 
  huffman_ins_v2_Msub_run_length_white_sub0000_cy_5_Q : MUXCY
2022 
    port map (
2023 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(4),
2024 
      DI => fax4_ins_a1_o(5),
2025 
      S => huffman_ins_v2_Msub_run_length_white_sub0000_lut(5),
2026 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_cy(5)
2027 
    );
2028 
  huffman_ins_v2_Msub_run_length_white_sub0000_lut_5_Q : LUT2
2029 
    generic map(
2030 
      INIT => X"9"
2031 
    )
2032 
    port map (
2033 
      I0 => fax4_ins_a1_o(5),
2034 
      I1 => fax4_ins_a0_o(5),
2035 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_lut(5)
2036 
    );
2037 
  huffman_ins_v2_Msub_run_length_white_sub0000_xor_4_Q : XORCY
2038 
    port map (
2039 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(3),
2040 
      LI => huffman_ins_v2_Msub_run_length_white_sub0000_lut(4),
2041 
      O => huffman_ins_v2_run_length_white_sub0000(4)
2042 
    );
2043 
  huffman_ins_v2_Msub_run_length_white_sub0000_cy_4_Q : MUXCY
2044 
    port map (
2045 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(3),
2046 
      DI => fax4_ins_a1_o(4),
2047 
      S => huffman_ins_v2_Msub_run_length_white_sub0000_lut(4),
2048 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_cy(4)
2049 
    );
2050 
  huffman_ins_v2_Msub_run_length_white_sub0000_lut_4_Q : LUT2
2051 
    generic map(
2052 
      INIT => X"9"
2053 
    )
2054 
    port map (
2055 
      I0 => fax4_ins_a1_o(4),
2056 
      I1 => fax4_ins_a0_o(4),
2057 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_lut(4)
2058 
    );
2059 
  huffman_ins_v2_Msub_run_length_white_sub0000_xor_3_Q : XORCY
2060 
    port map (
2061 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(2),
2062 
      LI => huffman_ins_v2_Msub_run_length_white_sub0000_lut(3),
2063 
      O => huffman_ins_v2_run_length_white_sub0000(3)
2064 
    );
2065 
  huffman_ins_v2_Msub_run_length_white_sub0000_cy_3_Q : MUXCY
2066 
    port map (
2067 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(2),
2068 
      DI => fax4_ins_a1_o(3),
2069 
      S => huffman_ins_v2_Msub_run_length_white_sub0000_lut(3),
2070 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_cy(3)
2071 
    );
2072 
  huffman_ins_v2_Msub_run_length_white_sub0000_lut_3_Q : LUT2
2073 
    generic map(
2074 
      INIT => X"9"
2075 
    )
2076 
    port map (
2077 
      I0 => fax4_ins_a1_o(3),
2078 
      I1 => fax4_ins_a0_o(3),
2079 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_lut(3)
2080 
    );
2081 
  huffman_ins_v2_Msub_run_length_white_sub0000_xor_2_Q : XORCY
2082 
    port map (
2083 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(1),
2084 
      LI => huffman_ins_v2_Msub_run_length_white_sub0000_lut(2),
2085 
      O => huffman_ins_v2_run_length_white_sub0000(2)
2086 
    );
2087 
  huffman_ins_v2_Msub_run_length_white_sub0000_cy_2_Q : MUXCY
2088 
    port map (
2089 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(1),
2090 
      DI => fax4_ins_a1_o(2),
2091 
      S => huffman_ins_v2_Msub_run_length_white_sub0000_lut(2),
2092 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_cy(2)
2093 
    );
2094 
  huffman_ins_v2_Msub_run_length_white_sub0000_lut_2_Q : LUT2
2095 
    generic map(
2096 
      INIT => X"9"
2097 
    )
2098 
    port map (
2099 
      I0 => fax4_ins_a1_o(2),
2100 
      I1 => fax4_ins_a0_o(2),
2101 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_lut(2)
2102 
    );
2103 
  huffman_ins_v2_Msub_run_length_white_sub0000_xor_1_Q : XORCY
2104 
    port map (
2105 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(0),
2106 
      LI => huffman_ins_v2_Msub_run_length_white_sub0000_lut(1),
2107 
      O => huffman_ins_v2_run_length_white_sub0000(1)
2108 
    );
2109 
  huffman_ins_v2_Msub_run_length_white_sub0000_cy_1_Q : MUXCY
2110 
    port map (
2111 
      CI => huffman_ins_v2_Msub_run_length_white_sub0000_cy(0),
2112 
      DI => fax4_ins_a1_o(1),
2113 
      S => huffman_ins_v2_Msub_run_length_white_sub0000_lut(1),
2114 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_cy(1)
2115 
    );
2116 
  huffman_ins_v2_Msub_run_length_white_sub0000_lut_1_Q : LUT2
2117 
    generic map(
2118 
      INIT => X"9"
2119 
    )
2120 
    port map (
2121 
      I0 => fax4_ins_a1_o(1),
2122 
      I1 => fax4_ins_a0_o(1),
2123 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_lut(1)
2124 
    );
2125 
  huffman_ins_v2_Msub_run_length_white_sub0000_xor_0_Q : XORCY
2126 
    port map (
2127 
      CI => N1,
2128 
      LI => huffman_ins_v2_Msub_run_length_white_sub0000_lut(0),
2129 
      O => huffman_ins_v2_run_length_white_sub0000(0)
2130 
    );
2131 
  huffman_ins_v2_Msub_run_length_white_sub0000_cy_0_Q : MUXCY
2132 
    port map (
2133 
      CI => N1,
2134 
      DI => fax4_ins_a1_o(0),
2135 
      S => huffman_ins_v2_Msub_run_length_white_sub0000_lut(0),
2136 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_cy(0)
2137 
    );
2138 
  huffman_ins_v2_Msub_run_length_white_sub0000_lut_0_Q : LUT2
2139 
    generic map(
2140 
      INIT => X"9"
2141 
    )
2142 
    port map (
2143 
      I0 => fax4_ins_a1_o(0),
2144 
      I1 => fax4_ins_a0_o(0),
2145 
      O => huffman_ins_v2_Msub_run_length_white_sub0000_lut(0)
2146 
    );
2147 
  huffman_ins_v2_code_white_width_4 : FD
2148 
    generic map(
2149 
      INIT => '0'
2150 
    )
2151 
    port map (
2152 
      C => pclk_i,
2153 
      D => huffman_ins_v2_Madd_code_white_width_add0000_cy_3_Q,
2154 
      Q => huffman_ins_v2_code_white_width(4)
2155 
    );
2156 
  huffman_ins_v2_code_white_width_3 : FD
2157 
    generic map(
2158 
      INIT => '0'
2159 
    )
2160 
    port map (
2161 
      C => pclk_i,
2162 
      D => huffman_ins_v2_code_white_width_add0000(3),
2163 
      Q => huffman_ins_v2_code_white_width(3)
2164 
    );
2165 
  huffman_ins_v2_code_white_width_2 : FD
2166 
    generic map(
2167 
      INIT => '0'
2168 
    )
2169 
    port map (
2170 
      C => pclk_i,
2171 
      D => huffman_ins_v2_code_white_width_add0000(2),
2172 
      Q => huffman_ins_v2_code_white_width(2)
2173 
    );
2174 
  huffman_ins_v2_code_white_width_1 : FD
2175 
    generic map(
2176 
      INIT => '0'
2177 
    )
2178 
    port map (
2179 
      C => pclk_i,
2180 
      D => huffman_ins_v2_code_white_width_add0000(1),
2181 
      Q => huffman_ins_v2_code_white_width(1)
2182 
    );
2183 
  huffman_ins_v2_code_white_width_0 : FD
2184 
    generic map(
2185 
      INIT => '0'
2186 
    )
2187 
    port map (
2188 
      C => pclk_i,
2189 
      D => huffman_ins_v2_Madd_code_white_width_add0000_lut(0),
2190 
      Q => huffman_ins_v2_code_white_width(0)
2191 
    );
2192 
  huffman_ins_v2_code_black_width_4 : FD
2193 
    generic map(
2194 
      INIT => '0'
2195 
    )
2196 
    port map (
2197 
      C => pclk_i,
2198 
      D => huffman_ins_v2_Madd_code_black_width_add0000_cy_3_Q,
2199 
      Q => huffman_ins_v2_code_black_width(4)
2200 
    );
2201 
  huffman_ins_v2_code_black_width_3 : FD
2202 
    generic map(
2203 
      INIT => '0'
2204 
    )
2205 
    port map (
2206 
      C => pclk_i,
2207 
      D => huffman_ins_v2_code_black_width_add0000(3),
2208 
      Q => huffman_ins_v2_code_black_width(3)
2209 
    );
2210 
  huffman_ins_v2_code_black_width_2 : FD
2211 
    generic map(
2212 
      INIT => '0'
2213 
    )
2214 
    port map (
2215 
      C => pclk_i,
2216 
      D => huffman_ins_v2_code_black_width_add0000(2),
2217 
      Q => huffman_ins_v2_code_black_width(2)
2218 
    );
2219 
  huffman_ins_v2_code_black_width_1 : FD
2220 
    generic map(
2221 
      INIT => '0'
2222 
    )
2223 
    port map (
2224 
      C => pclk_i,
2225 
      D => huffman_ins_v2_code_black_width_add0000(1),
2226 
      Q => huffman_ins_v2_code_black_width(1)
2227 
    );
2228 
  huffman_ins_v2_code_black_width_0 : FD
2229 
    generic map(
2230 
      INIT => '0'
2231 
    )
2232 
    port map (
2233 
      C => pclk_i,
2234 
      D => huffman_ins_v2_Madd_code_black_width_add0000_lut(0),
2235 
      Q => huffman_ins_v2_code_black_width(0)
2236 
    );
2237 
  huffman_ins_v2_horizontal_mode_part_2 : FD
2238 
    generic map(
2239 
      INIT => '0'
2240 
    )
2241 
    port map (
2242 
      C => pclk_i,
2243 
      D => huffman_ins_v2_horizontal_mode_part_1_2064,
2244 
      Q => huffman_ins_v2_horizontal_mode_part_2_2065
2245 
    );
2246 
  huffman_ins_v2_pass_vert_code_width_1_2 : FD
2247 
    generic map(
2248 
      INIT => '0'
2249 
    )
2250 
    port map (
2251 
      C => pclk_i,
2252 
      D => huffman_ins_v2_Mrom_run_length_i_rom00002,
2253 
      Q => huffman_ins_v2_pass_vert_code_width_1_2_Q
2254 
    );
2255 
  huffman_ins_v2_pass_vert_code_1_2 : FD
2256 
    generic map(
2257 
      INIT => '1'
2258 
    )
2259 
    port map (
2260 
      C => pclk_i,
2261 
      D => huffman_ins_v2_Mrom_run_length_i_rom00005,
2262 
      Q => huffman_ins_v2_pass_vert_code_1(2)
2263 
    );
2264 
  huffman_ins_v2_pass_vert_code_1_0 : FD
2265 
    generic map(
2266 
      INIT => '0'
2267 
    )
2268 
    port map (
2269 
      C => pclk_i,
2270 
      D => huffman_ins_v2_Mrom_run_length_i_rom00003,
2271 
      Q => huffman_ins_v2_pass_vert_code_1(0)
2272 
    );
2273 
  huffman_ins_v2_code_white_2 : FD
2274 
    generic map(
2275 
      INIT => '0'
2276 
    )
2277 
    port map (
2278 
      C => pclk_i,
2279 
      D => huffman_ins_v2_code_white_2_mux0000,
2280 
      Q => huffman_ins_v2_code_white(2)
2281 
    );
2282 
  huffman_ins_v2_code_white_1 : FD
2283 
    generic map(
2284 
      INIT => '0'
2285 
    )
2286 
    port map (
2287 
      C => pclk_i,
2288 
      D => huffman_ins_v2_code_white_1_mux0000,
2289 
      Q => huffman_ins_v2_code_white(1)
2290 
    );
2291 
  huffman_ins_v2_code_white_3 : FD
2292 
    generic map(
2293 
      INIT => '0'
2294 
    )
2295 
    port map (
2296 
      C => pclk_i,
2297 
      D => huffman_ins_v2_code_white_3_mux0000,
2298 
      Q => huffman_ins_v2_code_white(3)
2299 
    );
2300 
  huffman_ins_v2_hor_code_width_4 : FD
2301 
    generic map(
2302 
      INIT => '0'
2303 
    )
2304 
    port map (
2305 
      C => pclk_i,
2306 
      D => huffman_ins_v2_hor_code_width_mux0001(4),
2307 
      Q => huffman_ins_v2_hor_code_width(4)
2308 
    );
2309 
  huffman_ins_v2_hor_code_width_3 : FD
2310 
    generic map(
2311 
      INIT => '0'
2312 
    )
2313 
    port map (
2314 
      C => pclk_i,
2315 
      D => huffman_ins_v2_hor_code_width_mux0001(3),
2316 
      Q => huffman_ins_v2_hor_code_width(3)
2317 
    );
2318 
  huffman_ins_v2_hor_code_width_2 : FD
2319 
    generic map(
2320 
      INIT => '0'
2321 
    )
2322 
    port map (
2323 
      C => pclk_i,
2324 
      D => huffman_ins_v2_hor_code_width_mux0001(2),
2325 
      Q => huffman_ins_v2_hor_code_width(2)
2326 
    );
2327 
  huffman_ins_v2_hor_code_width_1 : FD
2328 
    generic map(
2329 
      INIT => '0'
2330 
    )
2331 
    port map (
2332 
      C => pclk_i,
2333 
      D => huffman_ins_v2_hor_code_width_mux0001(1),
2334 
      Q => huffman_ins_v2_hor_code_width(1)
2335 
    );
2336 
  huffman_ins_v2_hor_code_width_0 : FD
2337 
    generic map(
2338 
      INIT => '0'
2339 
    )
2340 
    port map (
2341 
      C => pclk_i,
2342 
      D => huffman_ins_v2_hor_code_width_mux0001(0),
2343 
      Q => huffman_ins_v2_hor_code_width(0)
2344 
    );
2345 
  huffman_ins_v2_code_white_0 : FD
2346 
    generic map(
2347 
      INIT => '0'
2348 
    )
2349 
    port map (
2350 
      C => pclk_i,
2351 
      D => huffman_ins_v2_code_white_0_mux0000,
2352 
      Q => huffman_ins_v2_code_white(0)
2353 
    );
2354 
  huffman_ins_v2_code_black_24 : FD
2355 
    generic map(
2356 
      INIT => '0'
2357 
    )
2358 
    port map (
2359 
      C => pclk_i,
2360 
      D => huffman_ins_v2_code_black_24_mux0000,
2361 
      Q => huffman_ins_v2_code_black(24)
2362 
    );
2363 
  huffman_ins_v2_code_black_19 : FD
2364 
    generic map(
2365 
      INIT => '0'
2366 
    )
2367 
    port map (
2368 
      C => pclk_i,
2369 
      D => huffman_ins_v2_code_black_19_mux0000,
2370 
      Q => huffman_ins_v2_code_black(19)
2371 
    );
2372 
  huffman_ins_v2_code_black_18 : FD
2373 
    generic map(
2374 
      INIT => '0'
2375 
    )
2376 
    port map (
2377 
      C => pclk_i,
2378 
      D => huffman_ins_v2_code_black_18_mux0000,
2379 
      Q => huffman_ins_v2_code_black(18)
2380 
    );
2381 
  huffman_ins_v2_code_black_17 : FD
2382 
    generic map(
2383 
      INIT => '0'
2384 
    )
2385 
    port map (
2386 
      C => pclk_i,
2387 
      D => huffman_ins_v2_code_black_17_mux0000,
2388 
      Q => huffman_ins_v2_code_black(17)
2389 
    );
2390 
  huffman_ins_v2_code_black_21 : FD
2391 
    generic map(
2392 
      INIT => '0'
2393 
    )
2394 
    port map (
2395 
      C => pclk_i,
2396 
      D => huffman_ins_v2_code_black_21_mux0000,
2397 
      Q => huffman_ins_v2_code_black(21)
2398 
    );
2399 
  huffman_ins_v2_code_black_16 : FD
2400 
    generic map(
2401 
      INIT => '0'
2402 
    )
2403 
    port map (
2404 
      C => pclk_i,
2405 
      D => huffman_ins_v2_code_black_16_mux0000,
2406 
      Q => huffman_ins_v2_code_black(16)
2407 
    );
2408 
  huffman_ins_v2_code_black_15 : FD
2409 
    generic map(
2410 
      INIT => '0'
2411 
    )
2412 
    port map (
2413 
      C => pclk_i,
2414 
      D => huffman_ins_v2_code_black_15_mux0000,
2415 
      Q => huffman_ins_v2_code_black(15)
2416 
    );
2417 
  huffman_ins_v2_code_black_14 : FD
2418 
    generic map(
2419 
      INIT => '0'
2420 
    )
2421 
    port map (
2422 
      C => pclk_i,
2423 
      D => huffman_ins_v2_code_black_14_mux0000,
2424 
      Q => huffman_ins_v2_code_black(14)
2425 
    );
2426 
  huffman_ins_v2_horizontal_mode_1 : FD
2427 
    generic map(
2428 
      INIT => '0'
2429 
    )
2430 
    port map (
2431 
      C => pclk_i,
2432 
      D => huffman_ins_v2_horizontal_mode_1_or0000,
2433 
      Q => huffman_ins_v2_horizontal_mode_1_2060
2434 
    );
2435 
  huffman_ins_v2_code_black_13 : FD
2436 
    generic map(
2437 
      INIT => '0'
2438 
    )
2439 
    port map (
2440 
      C => pclk_i,
2441 
      D => huffman_ins_v2_code_black_13_mux0000,
2442 
      Q => huffman_ins_v2_code_black(13)
2443 
    );
2444 
  huffman_ins_v2_code_black_9 : FD
2445 
    generic map(
2446 
      INIT => '0'
2447 
    )
2448 
    port map (
2449 
      C => pclk_i,
2450 
      D => huffman_ins_v2_code_black_9_mux0000,
2451 
      Q => huffman_ins_v2_code_black(9)
2452 
    );
2453 
  huffman_ins_v2_code_black_12 : FD
2454 
    generic map(
2455 
      INIT => '0'
2456 
    )
2457 
    port map (
2458 
      C => pclk_i,
2459 
      D => huffman_ins_v2_code_black_12_mux0000,
2460 
      Q => huffman_ins_v2_code_black(12)
2461 
    );
2462 
  huffman_ins_v2_code_black_11 : FD
2463 
    generic map(
2464 
      INIT => '0'
2465 
    )
2466 
    port map (
2467 
      C => pclk_i,
2468 
      D => huffman_ins_v2_code_black_11_mux0000,
2469 
      Q => huffman_ins_v2_code_black(11)
2470 
    );
2471 
  huffman_ins_v2_code_black_8 : FD
2472 
    generic map(
2473 
      INIT => '0'
2474 
    )
2475 
    port map (
2476 
      C => pclk_i,
2477 
      D => huffman_ins_v2_code_black_8_mux0000,
2478 
      Q => huffman_ins_v2_code_black(8)
2479 
    );
2480 
  huffman_ins_v2_code_black_10 : FD
2481 
    generic map(
2482 
      INIT => '0'
2483 
    )
2484 
    port map (
2485 
      C => pclk_i,
2486 
      D => huffman_ins_v2_code_black_10_mux0000,
2487 
      Q => huffman_ins_v2_code_black(10)
2488 
    );
2489 
  huffman_ins_v2_code_black_6 : FD
2490 
    generic map(
2491 
      INIT => '0'
2492 
    )
2493 
    port map (
2494 
      C => pclk_i,
2495 
      D => huffman_ins_v2_code_black_6_mux0000,
2496 
      Q => huffman_ins_v2_code_black(6)
2497 
    );
2498 
  huffman_ins_v2_code_black_7 : FD
2499 
    generic map(
2500 
      INIT => '0'
2501 
    )
2502 
    port map (
2503 
      C => pclk_i,
2504 
      D => huffman_ins_v2_code_black_7_mux0000,
2505 
      Q => huffman_ins_v2_code_black(7)
2506 
    );
2507 
  huffman_ins_v2_code_black_5 : FD
2508 
    generic map(
2509 
      INIT => '0'
2510 
    )
2511 
    port map (
2512 
      C => pclk_i,
2513 
      D => huffman_ins_v2_code_black_5_mux0000,
2514 
      Q => huffman_ins_v2_code_black(5)
2515 
    );
2516 
  huffman_ins_v2_horizontal_mode_part_1 : FD
2517 
    generic map(
2518 
      INIT => '0'
2519 
    )
2520 
    port map (
2521 
      C => pclk_i,
2522 
      D => huffman_ins_v2_horizontal_mode_1_cmp_eq0001,
2523 
      Q => huffman_ins_v2_horizontal_mode_part_1_2064
2524 
    );
2525 
  huffman_ins_v2_code_black_4 : FD
2526 
    generic map(
2527 
      INIT => '0'
2528 
    )
2529 
    port map (
2530 
      C => pclk_i,
2531 
      D => huffman_ins_v2_code_black_4_mux0000,
2532 
      Q => huffman_ins_v2_code_black(4)
2533 
    );
2534 
  huffman_ins_v2_code_black_3 : FD
2535 
    generic map(
2536 
      INIT => '0'
2537 
    )
2538 
    port map (
2539 
      C => pclk_i,
2540 
      D => huffman_ins_v2_code_black_3_mux0000,
2541 
      Q => huffman_ins_v2_code_black(3)
2542 
    );
2543 
  huffman_ins_v2_code_black_2 : FD
2544 
    generic map(
2545 
      INIT => '0'
2546 
    )
2547 
    port map (
2548 
      C => pclk_i,
2549 
      D => huffman_ins_v2_code_black_2_mux0000,
2550 
      Q => huffman_ins_v2_code_black(2)
2551 
    );
2552 
  huffman_ins_v2_code_black_1 : FD
2553 
    generic map(
2554 
      INIT => '0'
2555 
    )
2556 
    port map (
2557 
      C => pclk_i,
2558 
      D => huffman_ins_v2_code_black_1_mux0000,
2559 
      Q => huffman_ins_v2_code_black(1)
2560 
    );
2561 
  huffman_ins_v2_code_black_0 : FD
2562 
    generic map(
2563 
      INIT => '0'
2564 
    )
2565 
    port map (
2566 
      C => pclk_i,
2567 
      D => huffman_ins_v2_code_black_0_mux0000,
2568 
      Q => huffman_ins_v2_code_black(0)
2569 
    );
2570 
  huffman_ins_v2_code_white_16 : FD
2571 
    generic map(
2572 
      INIT => '0'
2573 
    )
2574 
    port map (
2575 
      C => pclk_i,
2576 
      D => huffman_ins_v2_code_white_16_mux0000,
2577 
      Q => huffman_ins_v2_code_white(16)
2578 
    );
2579 
  fax4_ins_counter_xy_v2_ins_line_valid : FDSE
2580 
    generic map(
2581 
      INIT => '0'
2582 
    )
2583 
    port map (
2584 
      C => pclk_i,
2585 
      CE => fax4_ins_counter_xy_v2_ins_cnt_x_reset_or0000,
2586 
      D => NlwRenamedSig_OI_run_len_code_o(26),
2587 
      S => fax4_ins_counter_xy_v2_ins_line_valid_and0000,
2588 
      Q => fax4_ins_counter_xy_v2_ins_line_valid_1210
2589 
    );
2590 
  fax4_ins_counter_xy_v2_ins_rsync_i_prev : FD
2591 
    generic map(
2592 
      INIT => '1'
2593 
    )
2594 
    port map (
2595 
      C => pclk_i,
2596 
      D => rsync_i,
2597 
      Q => fax4_ins_counter_xy_v2_ins_rsync_i_prev_1212
2598 
    );
2599 
  fax4_ins_counter_xy_v2_ins_cnt_y_reset : FDR
2600 
    generic map(
2601 
      INIT => '1'
2602 
    )
2603 
    port map (
2604 
      C => pclk_i,
2605 
      D => N1,
2606 
      R => fax4_ins_counter_xy_v2_ins_cnt_y_reset_or0000,
2607 
      Q => fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105
2608 
    );
2609 
  fax4_ins_counter_xy_v2_ins_cnt_x_reset : FDRS
2610 
    generic map(
2611 
      INIT => '1'
2612 
    )
2613 
    port map (
2614 
      C => pclk_i,
2615 
      D => NlwRenamedSig_OI_run_len_code_o(26),
2616 
      R => fax4_ins_counter_xy_v2_ins_line_valid_and0000,
2617 
      S => fax4_ins_counter_xy_v2_ins_cnt_x_reset_or0000,
2618 
      Q => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102
2619 
    );
2620 
  fax4_ins_counter_xy_v2_ins_fsync_i_prev : FD
2621 
    generic map(
2622 
      INIT => '1'
2623 
    )
2624 
    port map (
2625 
      C => pclk_i,
2626 
      D => fsync_i,
2627 
      Q => fax4_ins_counter_xy_v2_ins_fsync_i_prev_1209
2628 
    );
2629 
  fax4_ins_counter_xy_v2_ins_frame_valid : FDSE
2630 
    generic map(
2631 
      INIT => '0'
2632 
    )
2633 
    port map (
2634 
      C => pclk_i,
2635 
      CE => fax4_ins_counter_xy_v2_ins_frame_valid_and0001,
2636 
      D => NlwRenamedSig_OI_run_len_code_o(26),
2637 
      S => fax4_ins_counter_xy_v2_ins_frame_valid_and0000,
2638 
      Q => fax4_ins_counter_xy_v2_ins_frame_valid_1206
2639 
    );
2640 
  fax4_ins_counter_xy_v2_ins_cnt_x_overflow_prev : FD
2641 
    generic map(
2642 
      INIT => '0'
2643 
    )
2644 
    port map (
2645 
      C => pclk_i,
2646 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
2647 
      Q => fax4_ins_counter_xy_v2_ins_cnt_x_overflow_prev_1101
2648 
    );
2649 
  fax4_ins_counter_xy_v2_ins_cnt_y_overflow_prev : FD
2650 
    generic map(
2651 
      INIT => '0'
2652 
    )
2653 
    port map (
2654 
      C => pclk_i,
2655 
      D => fax4_ins_counter_xy_v2_ins_counter_y_ins_overflow_o_1204,
2656 
      Q => fax4_ins_counter_xy_v2_ins_cnt_y_overflow_prev_1104
2657 
    );
2658 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_2 : FDCE
2659 
    generic map(
2660 
      INIT => '0'
2661 
    )
2662 
    port map (
2663 
      C => pclk_i,
2664 
      CE => fax4_ins_counter_xy_v2_ins_cnt_x_en,
2665 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102,
2666 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(7),
2667 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2)
2668 
    );
2669 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_0 : FDPE
2670 
    generic map(
2671 
      INIT => '1'
2672 
    )
2673 
    port map (
2674 
      C => pclk_i,
2675 
      CE => fax4_ins_counter_xy_v2_ins_cnt_x_en,
2676 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(9),
2677 
      PRE => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102,
2678 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0)
2679 
    );
2680 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_1 : FDCE
2681 
    generic map(
2682 
      INIT => '0'
2683 
    )
2684 
    port map (
2685 
      C => pclk_i,
2686 
      CE => fax4_ins_counter_xy_v2_ins_cnt_x_en,
2687 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102,
2688 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(8),
2689 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1)
2690 
    );
2691 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_3 : FDCE
2692 
    generic map(
2693 
      INIT => '0'
2694 
    )
2695 
    port map (
2696 
      C => pclk_i,
2697 
      CE => fax4_ins_counter_xy_v2_ins_cnt_x_en,
2698 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102,
2699 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(6),
2700 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3)
2701 
    );
2702 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_4 : FDCE
2703 
    generic map(
2704 
      INIT => '0'
2705 
    )
2706 
    port map (
2707 
      C => pclk_i,
2708 
      CE => fax4_ins_counter_xy_v2_ins_cnt_x_en,
2709 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102,
2710 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(5),
2711 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4)
2712 
    );
2713 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_7 : FDCE
2714 
    generic map(
2715 
      INIT => '0'
2716 
    )
2717 
    port map (
2718 
      C => pclk_i,
2719 
      CE => fax4_ins_counter_xy_v2_ins_cnt_x_en,
2720 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102,
2721 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(2),
2722 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7)
2723 
    );
2724 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_5 : FDCE
2725 
    generic map(
2726 
      INIT => '0'
2727 
    )
2728 
    port map (
2729 
      C => pclk_i,
2730 
      CE => fax4_ins_counter_xy_v2_ins_cnt_x_en,
2731 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102,
2732 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(4),
2733 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5)
2734 
    );
2735 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_6 : FDCE
2736 
    generic map(
2737 
      INIT => '0'
2738 
    )
2739 
    port map (
2740 
      C => pclk_i,
2741 
      CE => fax4_ins_counter_xy_v2_ins_cnt_x_en,
2742 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102,
2743 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(3),
2744 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6)
2745 
    );
2746 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_8 : FDCE
2747 
    generic map(
2748 
      INIT => '0'
2749 
    )
2750 
    port map (
2751 
      C => pclk_i,
2752 
      CE => fax4_ins_counter_xy_v2_ins_cnt_x_en,
2753 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102,
2754 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(1),
2755 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8)
2756 
    );
2757 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_9 : FDCE
2758 
    generic map(
2759 
      INIT => '0'
2760 
    )
2761 
    port map (
2762 
      C => pclk_i,
2763 
      CE => fax4_ins_counter_xy_v2_ins_cnt_x_en,
2764 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102,
2765 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(0),
2766 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9)
2767 
    );
2768 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_9_Q : XORCY
2769 
    port map (
2770 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(8),
2771 
      LI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_9_rt_1125,
2772 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(9)
2773 
    );
2774 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_8_Q : XORCY
2775 
    port map (
2776 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(7),
2777 
      LI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_8_rt_1123,
2778 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(8)
2779 
    );
2780 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_8_Q : MUXCY
2781 
    port map (
2782 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(7),
2783 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
2784 
      S => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_8_rt_1123,
2785 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(8)
2786 
    );
2787 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_7_Q : XORCY
2788 
    port map (
2789 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(6),
2790 
      LI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_7_rt_1121,
2791 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(7)
2792 
    );
2793 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_7_Q : MUXCY
2794 
    port map (
2795 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(6),
2796 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
2797 
      S => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_7_rt_1121,
2798 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(7)
2799 
    );
2800 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_6_Q : XORCY
2801 
    port map (
2802 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(5),
2803 
      LI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_6_rt_1119,
2804 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(6)
2805 
    );
2806 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_6_Q : MUXCY
2807 
    port map (
2808 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(5),
2809 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
2810 
      S => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_6_rt_1119,
2811 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(6)
2812 
    );
2813 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_5_Q : XORCY
2814 
    port map (
2815 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(4),
2816 
      LI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_5_rt_1117,
2817 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(5)
2818 
    );
2819 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_5_Q : MUXCY
2820 
    port map (
2821 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(4),
2822 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
2823 
      S => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_5_rt_1117,
2824 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(5)
2825 
    );
2826 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_4_Q : XORCY
2827 
    port map (
2828 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(3),
2829 
      LI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_4_rt_1115,
2830 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(4)
2831 
    );
2832 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_4_Q : MUXCY
2833 
    port map (
2834 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(3),
2835 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
2836 
      S => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_4_rt_1115,
2837 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(4)
2838 
    );
2839 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_3_Q : XORCY
2840 
    port map (
2841 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(2),
2842 
      LI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_3_rt_1113,
2843 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(3)
2844 
    );
2845 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_3_Q : MUXCY
2846 
    port map (
2847 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(2),
2848 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
2849 
      S => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_3_rt_1113,
2850 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(3)
2851 
    );
2852 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_2_Q : XORCY
2853 
    port map (
2854 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(1),
2855 
      LI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_2_rt_1111,
2856 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(2)
2857 
    );
2858 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_2_Q : MUXCY
2859 
    port map (
2860 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(1),
2861 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
2862 
      S => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_2_rt_1111,
2863 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(2)
2864 
    );
2865 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_1_Q : XORCY
2866 
    port map (
2867 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(0),
2868 
      LI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_1_rt_1109,
2869 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(1)
2870 
    );
2871 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_1_Q : MUXCY
2872 
    port map (
2873 
      CI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(0),
2874 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
2875 
      S => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_1_rt_1109,
2876 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(1)
2877 
    );
2878 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_0_Q : XORCY
2879 
    port map (
2880 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
2881 
      LI => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_lut(0),
2882 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(0)
2883 
    );
2884 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_0_Q : MUXCY
2885 
    port map (
2886 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
2887 
      DI => N1,
2888 
      S => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_lut(0),
2889 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy(0)
2890 
    );
2891 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o : FDC
2892 
    generic map(
2893 
      INIT => '0'
2894 
    )
2895 
    port map (
2896 
      C => pclk_i,
2897 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_x_reset_1102,
2898 
      D => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_mux0002,
2899 
      Q => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157
2900 
    );
2901 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_2 : FDCE
2902 
    generic map(
2903 
      INIT => '0'
2904 
    )
2905 
    port map (
2906 
      C => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
2907 
      CE => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
2908 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105,
2909 
      D => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(6),
2910 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(2)
2911 
    );
2912 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_0 : FDPE
2913 
    generic map(
2914 
      INIT => '1'
2915 
    )
2916 
    port map (
2917 
      C => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
2918 
      CE => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
2919 
      D => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(8),
2920 
      PRE => fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105,
2921 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0)
2922 
    );
2923 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_1 : FDCE
2924 
    generic map(
2925 
      INIT => '0'
2926 
    )
2927 
    port map (
2928 
      C => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
2929 
      CE => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
2930 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105,
2931 
      D => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(7),
2932 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(1)
2933 
    );
2934 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_3 : FDCE
2935 
    generic map(
2936 
      INIT => '0'
2937 
    )
2938 
    port map (
2939 
      C => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
2940 
      CE => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
2941 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105,
2942 
      D => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(5),
2943 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(3)
2944 
    );
2945 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_4 : FDCE
2946 
    generic map(
2947 
      INIT => '0'
2948 
    )
2949 
    port map (
2950 
      C => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
2951 
      CE => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
2952 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105,
2953 
      D => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(4),
2954 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(4)
2955 
    );
2956 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_5 : FDCE
2957 
    generic map(
2958 
      INIT => '0'
2959 
    )
2960 
    port map (
2961 
      C => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
2962 
      CE => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
2963 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105,
2964 
      D => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(3),
2965 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(5)
2966 
    );
2967 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_6 : FDCE
2968 
    generic map(
2969 
      INIT => '0'
2970 
    )
2971 
    port map (
2972 
      C => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
2973 
      CE => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
2974 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105,
2975 
      D => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(2),
2976 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(6)
2977 
    );
2978 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_7 : FDCE
2979 
    generic map(
2980 
      INIT => '0'
2981 
    )
2982 
    port map (
2983 
      C => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
2984 
      CE => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
2985 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105,
2986 
      D => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(1),
2987 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(7)
2988 
    );
2989 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_8 : FDCE
2990 
    generic map(
2991 
      INIT => '0'
2992 
    )
2993 
    port map (
2994 
      C => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
2995 
      CE => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
2996 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105,
2997 
      D => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(0),
2998 
      Q => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(8)
2999 
    );
3000 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_8_Q : XORCY
3001 
    port map (
3002 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(7),
3003 
      LI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_8_rt_1175,
3004 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(8)
3005 
    );
3006 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_7_Q : XORCY
3007 
    port map (
3008 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(6),
3009 
      LI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_7_rt_1173,
3010 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(7)
3011 
    );
3012 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_7_Q : MUXCY
3013 
    port map (
3014 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(6),
3015 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
3016 
      S => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_7_rt_1173,
3017 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(7)
3018 
    );
3019 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_6_Q : XORCY
3020 
    port map (
3021 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(5),
3022 
      LI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_6_rt_1171,
3023 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(6)
3024 
    );
3025 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_6_Q : MUXCY
3026 
    port map (
3027 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(5),
3028 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
3029 
      S => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_6_rt_1171,
3030 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(6)
3031 
    );
3032 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_5_Q : XORCY
3033 
    port map (
3034 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(4),
3035 
      LI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_5_rt_1169,
3036 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(5)
3037 
    );
3038 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_5_Q : MUXCY
3039 
    port map (
3040 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(4),
3041 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
3042 
      S => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_5_rt_1169,
3043 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(5)
3044 
    );
3045 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_4_Q : XORCY
3046 
    port map (
3047 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(3),
3048 
      LI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_4_rt_1167,
3049 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(4)
3050 
    );
3051 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_4_Q : MUXCY
3052 
    port map (
3053 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(3),
3054 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
3055 
      S => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_4_rt_1167,
3056 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(4)
3057 
    );
3058 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_3_Q : XORCY
3059 
    port map (
3060 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(2),
3061 
      LI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_3_rt_1165,
3062 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(3)
3063 
    );
3064 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_3_Q : MUXCY
3065 
    port map (
3066 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(2),
3067 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
3068 
      S => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_3_rt_1165,
3069 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(3)
3070 
    );
3071 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_2_Q : XORCY
3072 
    port map (
3073 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(1),
3074 
      LI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_2_rt_1163,
3075 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(2)
3076 
    );
3077 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_2_Q : MUXCY
3078 
    port map (
3079 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(1),
3080 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
3081 
      S => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_2_rt_1163,
3082 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(2)
3083 
    );
3084 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_1_Q : XORCY
3085 
    port map (
3086 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(0),
3087 
      LI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_1_rt_1161,
3088 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(1)
3089 
    );
3090 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_1_Q : MUXCY
3091 
    port map (
3092 
      CI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(0),
3093 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
3094 
      S => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_1_rt_1161,
3095 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(1)
3096 
    );
3097 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_0_Q : XORCY
3098 
    port map (
3099 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
3100 
      LI => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_lut(0),
3101 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(0)
3102 
    );
3103 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_0_Q : MUXCY
3104 
    port map (
3105 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
3106 
      DI => N1,
3107 
      S => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_lut(0),
3108 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy(0)
3109 
    );
3110 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_overflow_o : FDC
3111 
    generic map(
3112 
      INIT => '0'
3113 
    )
3114 
    port map (
3115 
      C => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
3116 
      CLR => fax4_ins_counter_xy_v2_ins_cnt_y_reset_1105,
3117 
      D => fax4_ins_counter_xy_v2_ins_counter_y_ins_overflow_o_mux0002,
3118 
      Q => fax4_ins_counter_xy_v2_ins_counter_y_ins_overflow_o_1204
3119 
    );
3120 
  fax4_ins_FIFO1_multi_read_ins_to_white3_o : FDPE
3121 
    generic map(
3122 
      INIT => '0'
3123 
    )
3124 
    port map (
3125 
      C => fax4_ins_pclk_not,
3126 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3127 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_to_white,
3128 
      PRE => frame_finished_wire,
3129 
      Q => fax4_ins_FIFO1_multi_read_ins_to_white3_o_443
3130 
    );
3131 
  fax4_ins_FIFO1_multi_read_ins_data1_o_0 : FDE
3132 
    generic map(
3133 
      INIT => '0'
3134 
    )
3135 
    port map (
3136 
      C => fax4_ins_pclk_not,
3137 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3138 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_x(0),
3139 
      Q => fax4_ins_FIFO1_multi_read_ins_data1_o(0)
3140 
    );
3141 
  fax4_ins_FIFO1_multi_read_ins_data1_o_1 : FDE
3142 
    generic map(
3143 
      INIT => '0'
3144 
    )
3145 
    port map (
3146 
      C => fax4_ins_pclk_not,
3147 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3148 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_x(1),
3149 
      Q => fax4_ins_FIFO1_multi_read_ins_data1_o(1)
3150 
    );
3151 
  fax4_ins_FIFO1_multi_read_ins_data1_o_2 : FDE
3152 
    generic map(
3153 
      INIT => '0'
3154 
    )
3155 
    port map (
3156 
      C => fax4_ins_pclk_not,
3157 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3158 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_x(2),
3159 
      Q => fax4_ins_FIFO1_multi_read_ins_data1_o(2)
3160 
    );
3161 
  fax4_ins_FIFO1_multi_read_ins_data1_o_3 : FDE
3162 
    generic map(
3163 
      INIT => '0'
3164 
    )
3165 
    port map (
3166 
      C => fax4_ins_pclk_not,
3167 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3168 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_x(3),
3169 
      Q => fax4_ins_FIFO1_multi_read_ins_data1_o(3)
3170 
    );
3171 
  fax4_ins_FIFO1_multi_read_ins_data1_o_4 : FDE
3172 
    generic map(
3173 
      INIT => '0'
3174 
    )
3175 
    port map (
3176 
      C => fax4_ins_pclk_not,
3177 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3178 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_x(4),
3179 
      Q => fax4_ins_FIFO1_multi_read_ins_data1_o(4)
3180 
    );
3181 
  fax4_ins_FIFO1_multi_read_ins_data1_o_5 : FDE
3182 
    generic map(
3183 
      INIT => '0'
3184 
    )
3185 
    port map (
3186 
      C => fax4_ins_pclk_not,
3187 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3188 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_x(5),
3189 
      Q => fax4_ins_FIFO1_multi_read_ins_data1_o(5)
3190 
    );
3191 
  fax4_ins_FIFO1_multi_read_ins_data1_o_6 : FDE
3192 
    generic map(
3193 
      INIT => '0'
3194 
    )
3195 
    port map (
3196 
      C => fax4_ins_pclk_not,
3197 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3198 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_x(6),
3199 
      Q => fax4_ins_FIFO1_multi_read_ins_data1_o(6)
3200 
    );
3201 
  fax4_ins_FIFO1_multi_read_ins_data1_o_7 : FDE
3202 
    generic map(
3203 
      INIT => '0'
3204 
    )
3205 
    port map (
3206 
      C => fax4_ins_pclk_not,
3207 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3208 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_x(7),
3209 
      Q => fax4_ins_FIFO1_multi_read_ins_data1_o(7)
3210 
    );
3211 
  fax4_ins_FIFO1_multi_read_ins_data1_o_8 : FDE
3212 
    generic map(
3213 
      INIT => '0'
3214 
    )
3215 
    port map (
3216 
      C => fax4_ins_pclk_not,
3217 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3218 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_x(8),
3219 
      Q => fax4_ins_FIFO1_multi_read_ins_data1_o(8)
3220 
    );
3221 
  fax4_ins_FIFO1_multi_read_ins_data1_o_9 : FDE
3222 
    generic map(
3223 
      INIT => '0'
3224 
    )
3225 
    port map (
3226 
      C => fax4_ins_pclk_not,
3227 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3228 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_x(9),
3229 
      Q => fax4_ins_FIFO1_multi_read_ins_data1_o(9)
3230 
    );
3231 
  fax4_ins_FIFO1_multi_read_ins_valid1_o : FDCE
3232 
    generic map(
3233 
      INIT => '0'
3234 
    )
3235 
    port map (
3236 
      C => fax4_ins_pclk_not,
3237 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3238 
      CLR => frame_finished_wire,
3239 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_valid,
3240 
      Q => fax4_ins_FIFO1_multi_read_ins_valid1_o_456
3241 
    );
3242 
  fax4_ins_FIFO1_multi_read_ins_data2_o_0 : FDE
3243 
    generic map(
3244 
      INIT => '0'
3245 
    )
3246 
    port map (
3247 
      C => fax4_ins_pclk_not,
3248 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3249 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_x(0),
3250 
      Q => fax4_ins_FIFO1_multi_read_ins_data2_o(0)
3251 
    );
3252 
  fax4_ins_FIFO1_multi_read_ins_data2_o_1 : FDE
3253 
    generic map(
3254 
      INIT => '0'
3255 
    )
3256 
    port map (
3257 
      C => fax4_ins_pclk_not,
3258 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3259 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_x(1),
3260 
      Q => fax4_ins_FIFO1_multi_read_ins_data2_o(1)
3261 
    );
3262 
  fax4_ins_FIFO1_multi_read_ins_data2_o_2 : FDE
3263 
    generic map(
3264 
      INIT => '0'
3265 
    )
3266 
    port map (
3267 
      C => fax4_ins_pclk_not,
3268 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3269 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_x(2),
3270 
      Q => fax4_ins_FIFO1_multi_read_ins_data2_o(2)
3271 
    );
3272 
  fax4_ins_FIFO1_multi_read_ins_data2_o_3 : FDE
3273 
    generic map(
3274 
      INIT => '0'
3275 
    )
3276 
    port map (
3277 
      C => fax4_ins_pclk_not,
3278 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3279 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_x(3),
3280 
      Q => fax4_ins_FIFO1_multi_read_ins_data2_o(3)
3281 
    );
3282 
  fax4_ins_FIFO1_multi_read_ins_data2_o_4 : FDE
3283 
    generic map(
3284 
      INIT => '0'
3285 
    )
3286 
    port map (
3287 
      C => fax4_ins_pclk_not,
3288 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3289 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_x(4),
3290 
      Q => fax4_ins_FIFO1_multi_read_ins_data2_o(4)
3291 
    );
3292 
  fax4_ins_FIFO1_multi_read_ins_data2_o_5 : FDE
3293 
    generic map(
3294 
      INIT => '0'
3295 
    )
3296 
    port map (
3297 
      C => fax4_ins_pclk_not,
3298 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3299 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_x(5),
3300 
      Q => fax4_ins_FIFO1_multi_read_ins_data2_o(5)
3301 
    );
3302 
  fax4_ins_FIFO1_multi_read_ins_data2_o_6 : FDE
3303 
    generic map(
3304 
      INIT => '0'
3305 
    )
3306 
    port map (
3307 
      C => fax4_ins_pclk_not,
3308 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3309 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_x(6),
3310 
      Q => fax4_ins_FIFO1_multi_read_ins_data2_o(6)
3311 
    );
3312 
  fax4_ins_FIFO1_multi_read_ins_data2_o_7 : FDE
3313 
    generic map(
3314 
      INIT => '0'
3315 
    )
3316 
    port map (
3317 
      C => fax4_ins_pclk_not,
3318 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3319 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_x(7),
3320 
      Q => fax4_ins_FIFO1_multi_read_ins_data2_o(7)
3321 
    );
3322 
  fax4_ins_FIFO1_multi_read_ins_data2_o_8 : FDE
3323 
    generic map(
3324 
      INIT => '0'
3325 
    )
3326 
    port map (
3327 
      C => fax4_ins_pclk_not,
3328 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3329 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_x(8),
3330 
      Q => fax4_ins_FIFO1_multi_read_ins_data2_o(8)
3331 
    );
3332 
  fax4_ins_FIFO1_multi_read_ins_data2_o_9 : FDE
3333 
    generic map(
3334 
      INIT => '0'
3335 
    )
3336 
    port map (
3337 
      C => fax4_ins_pclk_not,
3338 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3339 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_x(9),
3340 
      Q => fax4_ins_FIFO1_multi_read_ins_data2_o(9)
3341 
    );
3342 
  fax4_ins_FIFO1_multi_read_ins_valid2_o : FDCE
3343 
    generic map(
3344 
      INIT => '0'
3345 
    )
3346 
    port map (
3347 
      C => fax4_ins_pclk_not,
3348 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3349 
      CLR => frame_finished_wire,
3350 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_valid,
3351 
      Q => fax4_ins_FIFO1_multi_read_ins_valid2_o_457
3352 
    );
3353 
  fax4_ins_FIFO1_multi_read_ins_data3_o_0 : FDE
3354 
    generic map(
3355 
      INIT => '0'
3356 
    )
3357 
    port map (
3358 
      C => fax4_ins_pclk_not,
3359 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3360 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_x(0),
3361 
      Q => fax4_ins_FIFO1_multi_read_ins_data3_o(0)
3362 
    );
3363 
  fax4_ins_FIFO1_multi_read_ins_data3_o_1 : FDE
3364 
    generic map(
3365 
      INIT => '0'
3366 
    )
3367 
    port map (
3368 
      C => fax4_ins_pclk_not,
3369 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3370 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_x(1),
3371 
      Q => fax4_ins_FIFO1_multi_read_ins_data3_o(1)
3372 
    );
3373 
  fax4_ins_FIFO1_multi_read_ins_data3_o_2 : FDE
3374 
    generic map(
3375 
      INIT => '0'
3376 
    )
3377 
    port map (
3378 
      C => fax4_ins_pclk_not,
3379 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3380 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_x(2),
3381 
      Q => fax4_ins_FIFO1_multi_read_ins_data3_o(2)
3382 
    );
3383 
  fax4_ins_FIFO1_multi_read_ins_data3_o_3 : FDE
3384 
    generic map(
3385 
      INIT => '0'
3386 
    )
3387 
    port map (
3388 
      C => fax4_ins_pclk_not,
3389 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3390 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_x(3),
3391 
      Q => fax4_ins_FIFO1_multi_read_ins_data3_o(3)
3392 
    );
3393 
  fax4_ins_FIFO1_multi_read_ins_data3_o_4 : FDE
3394 
    generic map(
3395 
      INIT => '0'
3396 
    )
3397 
    port map (
3398 
      C => fax4_ins_pclk_not,
3399 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3400 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_x(4),
3401 
      Q => fax4_ins_FIFO1_multi_read_ins_data3_o(4)
3402 
    );
3403 
  fax4_ins_FIFO1_multi_read_ins_data3_o_5 : FDE
3404 
    generic map(
3405 
      INIT => '0'
3406 
    )
3407 
    port map (
3408 
      C => fax4_ins_pclk_not,
3409 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3410 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_x(5),
3411 
      Q => fax4_ins_FIFO1_multi_read_ins_data3_o(5)
3412 
    );
3413 
  fax4_ins_FIFO1_multi_read_ins_data3_o_6 : FDE
3414 
    generic map(
3415 
      INIT => '0'
3416 
    )
3417 
    port map (
3418 
      C => fax4_ins_pclk_not,
3419 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3420 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_x(6),
3421 
      Q => fax4_ins_FIFO1_multi_read_ins_data3_o(6)
3422 
    );
3423 
  fax4_ins_FIFO1_multi_read_ins_data3_o_7 : FDE
3424 
    generic map(
3425 
      INIT => '0'
3426 
    )
3427 
    port map (
3428 
      C => fax4_ins_pclk_not,
3429 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3430 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_x(7),
3431 
      Q => fax4_ins_FIFO1_multi_read_ins_data3_o(7)
3432 
    );
3433 
  fax4_ins_FIFO1_multi_read_ins_data3_o_8 : FDE
3434 
    generic map(
3435 
      INIT => '0'
3436 
    )
3437 
    port map (
3438 
      C => fax4_ins_pclk_not,
3439 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3440 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_x(8),
3441 
      Q => fax4_ins_FIFO1_multi_read_ins_data3_o(8)
3442 
    );
3443 
  fax4_ins_FIFO1_multi_read_ins_data3_o_9 : FDE
3444 
    generic map(
3445 
      INIT => '0'
3446 
    )
3447 
    port map (
3448 
      C => fax4_ins_pclk_not,
3449 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3450 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_x(9),
3451 
      Q => fax4_ins_FIFO1_multi_read_ins_data3_o(9)
3452 
    );
3453 
  fax4_ins_FIFO1_multi_read_ins_valid3_o : FDCE
3454 
    generic map(
3455 
      INIT => '0'
3456 
    )
3457 
    port map (
3458 
      C => fax4_ins_pclk_not,
3459 
      CE => fax4_ins_FIFO1_multi_read_ins_latch3,
3460 
      CLR => frame_finished_wire,
3461 
      D => fax4_ins_FIFO1_multi_read_ins_mux3_valid,
3462 
      Q => fax4_ins_FIFO1_multi_read_ins_valid3_o_458
3463 
    );
3464 
  fax4_ins_FIFO1_multi_read_ins_to_white1_o : FDPE
3465 
    generic map(
3466 
      INIT => '0'
3467 
    )
3468 
    port map (
3469 
      C => fax4_ins_pclk_not,
3470 
      CE => fax4_ins_FIFO1_multi_read_ins_latch1,
3471 
      D => fax4_ins_FIFO1_multi_read_ins_mux1_to_white,
3472 
      PRE => frame_finished_wire,
3473 
      Q => fax4_ins_FIFO1_multi_read_ins_to_white1_o_441
3474 
    );
3475 
  fax4_ins_FIFO1_multi_read_ins_to_white2_o : FDPE
3476 
    generic map(
3477 
      INIT => '0'
3478 
    )
3479 
    port map (
3480 
      C => fax4_ins_pclk_not,
3481 
      CE => fax4_ins_FIFO1_multi_read_ins_latch2,
3482 
      D => fax4_ins_FIFO1_multi_read_ins_mux2_to_white,
3483 
      PRE => frame_finished_wire,
3484 
      Q => fax4_ins_FIFO1_multi_read_ins_to_white2_o_442
3485 
    );
3486 
  fax4_ins_FIFO1_multi_read_ins_read_pos_0 : FDCE
3487 
    generic map(
3488 
      INIT => '0'
3489 
    )
3490 
    port map (
3491 
      C => fax4_ins_pclk_not,
3492 
      CE => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
3493 
      CLR => frame_finished_wire,
3494 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_0,
3495 
      Q => fax4_ins_FIFO1_multi_read_ins_read_pos(0)
3496 
    );
3497 
  fax4_ins_FIFO1_multi_read_ins_read_pos_1 : FDCE
3498 
    generic map(
3499 
      INIT => '0'
3500 
    )
3501 
    port map (
3502 
      C => fax4_ins_pclk_not,
3503 
      CE => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
3504 
      CLR => frame_finished_wire,
3505 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_1,
3506 
      Q => fax4_ins_FIFO1_multi_read_ins_read_pos(1)
3507 
    );
3508 
  fax4_ins_FIFO1_multi_read_ins_read_pos_2 : FDCE
3509 
    generic map(
3510 
      INIT => '0'
3511 
    )
3512 
    port map (
3513 
      C => fax4_ins_pclk_not,
3514 
      CE => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
3515 
      CLR => frame_finished_wire,
3516 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_2,
3517 
      Q => fax4_ins_FIFO1_multi_read_ins_read_pos(2)
3518 
    );
3519 
  fax4_ins_FIFO1_multi_read_ins_read_pos_3 : FDCE
3520 
    generic map(
3521 
      INIT => '0'
3522 
    )
3523 
    port map (
3524 
      C => fax4_ins_pclk_not,
3525 
      CE => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
3526 
      CLR => frame_finished_wire,
3527 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_3,
3528 
      Q => fax4_ins_FIFO1_multi_read_ins_read_pos(3)
3529 
    );
3530 
  fax4_ins_FIFO1_multi_read_ins_read_pos_4 : FDCE
3531 
    generic map(
3532 
      INIT => '0'
3533 
    )
3534 
    port map (
3535 
      C => fax4_ins_pclk_not,
3536 
      CE => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
3537 
      CLR => frame_finished_wire,
3538 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_4,
3539 
      Q => fax4_ins_FIFO1_multi_read_ins_read_pos(4)
3540 
    );
3541 
  fax4_ins_FIFO1_multi_read_ins_read_pos_5 : FDCE
3542 
    generic map(
3543 
      INIT => '0'
3544 
    )
3545 
    port map (
3546 
      C => fax4_ins_pclk_not,
3547 
      CE => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
3548 
      CLR => frame_finished_wire,
3549 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_5,
3550 
      Q => fax4_ins_FIFO1_multi_read_ins_read_pos(5)
3551 
    );
3552 
  fax4_ins_FIFO1_multi_read_ins_read_pos_6 : FDCE
3553 
    generic map(
3554 
      INIT => '0'
3555 
    )
3556 
    port map (
3557 
      C => fax4_ins_pclk_not,
3558 
      CE => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
3559 
      CLR => frame_finished_wire,
3560 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_6,
3561 
      Q => fax4_ins_FIFO1_multi_read_ins_read_pos(6)
3562 
    );
3563 
  fax4_ins_FIFO1_multi_read_ins_read_pos_7 : FDCE
3564 
    generic map(
3565 
      INIT => '0'
3566 
    )
3567 
    port map (
3568 
      C => fax4_ins_pclk_not,
3569 
      CE => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
3570 
      CLR => frame_finished_wire,
3571 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_7,
3572 
      Q => fax4_ins_FIFO1_multi_read_ins_read_pos(7)
3573 
    );
3574 
  fax4_ins_FIFO1_multi_read_ins_read_pos_8 : FDCE
3575 
    generic map(
3576 
      INIT => '0'
3577 
    )
3578 
    port map (
3579 
      C => fax4_ins_pclk_not,
3580 
      CE => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
3581 
      CLR => frame_finished_wire,
3582 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_8,
3583 
      Q => fax4_ins_FIFO1_multi_read_ins_read_pos(8)
3584 
    );
3585 
  fax4_ins_FIFO1_multi_read_ins_read_pos_9 : FDCE
3586 
    generic map(
3587 
      INIT => '0'
3588 
    )
3589 
    port map (
3590 
      C => fax4_ins_pclk_not,
3591 
      CE => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
3592 
      CLR => frame_finished_wire,
3593 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_9,
3594 
      Q => fax4_ins_FIFO1_multi_read_ins_read_pos(9)
3595 
    );
3596 
  fax4_ins_FIFO1_multi_read_ins_write_pos_0 : FDCE
3597 
    generic map(
3598 
      INIT => '0'
3599 
    )
3600 
    port map (
3601 
      C => fax4_ins_pclk_not,
3602 
      CE => fax4_ins_FIFO1_multi_read_ins_wr_459,
3603 
      CLR => frame_finished_wire,
3604 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_0,
3605 
      Q => fax4_ins_FIFO1_multi_read_ins_write_pos(0)
3606 
    );
3607 
  fax4_ins_FIFO1_multi_read_ins_write_pos_1 : FDCE
3608 
    generic map(
3609 
      INIT => '0'
3610 
    )
3611 
    port map (
3612 
      C => fax4_ins_pclk_not,
3613 
      CE => fax4_ins_FIFO1_multi_read_ins_wr_459,
3614 
      CLR => frame_finished_wire,
3615 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_1,
3616 
      Q => fax4_ins_FIFO1_multi_read_ins_write_pos(1)
3617 
    );
3618 
  fax4_ins_FIFO1_multi_read_ins_write_pos_2 : FDCE
3619 
    generic map(
3620 
      INIT => '0'
3621 
    )
3622 
    port map (
3623 
      C => fax4_ins_pclk_not,
3624 
      CE => fax4_ins_FIFO1_multi_read_ins_wr_459,
3625 
      CLR => frame_finished_wire,
3626 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_2,
3627 
      Q => fax4_ins_FIFO1_multi_read_ins_write_pos(2)
3628 
    );
3629 
  fax4_ins_FIFO1_multi_read_ins_write_pos_3 : FDCE
3630 
    generic map(
3631 
      INIT => '0'
3632 
    )
3633 
    port map (
3634 
      C => fax4_ins_pclk_not,
3635 
      CE => fax4_ins_FIFO1_multi_read_ins_wr_459,
3636 
      CLR => frame_finished_wire,
3637 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_3,
3638 
      Q => fax4_ins_FIFO1_multi_read_ins_write_pos(3)
3639 
    );
3640 
  fax4_ins_FIFO1_multi_read_ins_write_pos_4 : FDCE
3641 
    generic map(
3642 
      INIT => '0'
3643 
    )
3644 
    port map (
3645 
      C => fax4_ins_pclk_not,
3646 
      CE => fax4_ins_FIFO1_multi_read_ins_wr_459,
3647 
      CLR => frame_finished_wire,
3648 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_4,
3649 
      Q => fax4_ins_FIFO1_multi_read_ins_write_pos(4)
3650 
    );
3651 
  fax4_ins_FIFO1_multi_read_ins_write_pos_5 : FDCE
3652 
    generic map(
3653 
      INIT => '0'
3654 
    )
3655 
    port map (
3656 
      C => fax4_ins_pclk_not,
3657 
      CE => fax4_ins_FIFO1_multi_read_ins_wr_459,
3658 
      CLR => frame_finished_wire,
3659 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_5,
3660 
      Q => fax4_ins_FIFO1_multi_read_ins_write_pos(5)
3661 
    );
3662 
  fax4_ins_FIFO1_multi_read_ins_write_pos_6 : FDCE
3663 
    generic map(
3664 
      INIT => '0'
3665 
    )
3666 
    port map (
3667 
      C => fax4_ins_pclk_not,
3668 
      CE => fax4_ins_FIFO1_multi_read_ins_wr_459,
3669 
      CLR => frame_finished_wire,
3670 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_6,
3671 
      Q => fax4_ins_FIFO1_multi_read_ins_write_pos(6)
3672 
    );
3673 
  fax4_ins_FIFO1_multi_read_ins_write_pos_7 : FDCE
3674 
    generic map(
3675 
      INIT => '0'
3676 
    )
3677 
    port map (
3678 
      C => fax4_ins_pclk_not,
3679 
      CE => fax4_ins_FIFO1_multi_read_ins_wr_459,
3680 
      CLR => frame_finished_wire,
3681 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_7,
3682 
      Q => fax4_ins_FIFO1_multi_read_ins_write_pos(7)
3683 
    );
3684 
  fax4_ins_FIFO1_multi_read_ins_write_pos_8 : FDCE
3685 
    generic map(
3686 
      INIT => '0'
3687 
    )
3688 
    port map (
3689 
      C => fax4_ins_pclk_not,
3690 
      CE => fax4_ins_FIFO1_multi_read_ins_wr_459,
3691 
      CLR => frame_finished_wire,
3692 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_8,
3693 
      Q => fax4_ins_FIFO1_multi_read_ins_write_pos(8)
3694 
    );
3695 
  fax4_ins_FIFO1_multi_read_ins_write_pos_9 : FDCE
3696 
    generic map(
3697 
      INIT => '0'
3698 
    )
3699 
    port map (
3700 
      C => fax4_ins_pclk_not,
3701 
      CE => fax4_ins_FIFO1_multi_read_ins_wr_459,
3702 
      CLR => frame_finished_wire,
3703 
      D => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_9,
3704 
      Q => fax4_ins_FIFO1_multi_read_ins_write_pos(9)
3705 
    );
3706 
  fax4_ins_FIFO1_multi_read_ins_used_0 : FDCE
3707 
    generic map(
3708 
      INIT => '0'
3709 
    )
3710 
    port map (
3711 
      C => fax4_ins_pclk_not,
3712 
      CE => fax4_ins_FIFO1_multi_read_ins_used_not0002_454,
3713 
      CLR => frame_finished_wire,
3714 
      D => fax4_ins_FIFO1_multi_read_ins_Result_0_2,
3715 
      Q => fax4_ins_FIFO1_multi_read_ins_used(0)
3716 
    );
3717 
  fax4_ins_FIFO1_multi_read_ins_used_1 : FDCE
3718 
    generic map(
3719 
      INIT => '0'
3720 
    )
3721 
    port map (
3722 
      C => fax4_ins_pclk_not,
3723 
      CE => fax4_ins_FIFO1_multi_read_ins_used_not0002_454,
3724 
      CLR => frame_finished_wire,
3725 
      D => fax4_ins_FIFO1_multi_read_ins_Result_1_2,
3726 
      Q => fax4_ins_FIFO1_multi_read_ins_used(1)
3727 
    );
3728 
  fax4_ins_FIFO1_multi_read_ins_used_2 : FDCE
3729 
    generic map(
3730 
      INIT => '0'
3731 
    )
3732 
    port map (
3733 
      C => fax4_ins_pclk_not,
3734 
      CE => fax4_ins_FIFO1_multi_read_ins_used_not0002_454,
3735 
      CLR => frame_finished_wire,
3736 
      D => fax4_ins_FIFO1_multi_read_ins_Result_2_2,
3737 
      Q => fax4_ins_FIFO1_multi_read_ins_used(2)
3738 
    );
3739 
  fax4_ins_FIFO1_multi_read_ins_used_3 : FDCE
3740 
    generic map(
3741 
      INIT => '0'
3742 
    )
3743 
    port map (
3744 
      C => fax4_ins_pclk_not,
3745 
      CE => fax4_ins_FIFO1_multi_read_ins_used_not0002_454,
3746 
      CLR => frame_finished_wire,
3747 
      D => fax4_ins_FIFO1_multi_read_ins_Result_3_2,
3748 
      Q => fax4_ins_FIFO1_multi_read_ins_used(3)
3749 
    );
3750 
  fax4_ins_FIFO1_multi_read_ins_used_4 : FDCE
3751 
    generic map(
3752 
      INIT => '0'
3753 
    )
3754 
    port map (
3755 
      C => fax4_ins_pclk_not,
3756 
      CE => fax4_ins_FIFO1_multi_read_ins_used_not0002_454,
3757 
      CLR => frame_finished_wire,
3758 
      D => fax4_ins_FIFO1_multi_read_ins_Result_4_2,
3759 
      Q => fax4_ins_FIFO1_multi_read_ins_used(4)
3760 
    );
3761 
  fax4_ins_FIFO1_multi_read_ins_used_5 : FDCE
3762 
    generic map(
3763 
      INIT => '0'
3764 
    )
3765 
    port map (
3766 
      C => fax4_ins_pclk_not,
3767 
      CE => fax4_ins_FIFO1_multi_read_ins_used_not0002_454,
3768 
      CLR => frame_finished_wire,
3769 
      D => fax4_ins_FIFO1_multi_read_ins_Result_5_2,
3770 
      Q => fax4_ins_FIFO1_multi_read_ins_used(5)
3771 
    );
3772 
  fax4_ins_FIFO1_multi_read_ins_used_6 : FDCE
3773 
    generic map(
3774 
      INIT => '0'
3775 
    )
3776 
    port map (
3777 
      C => fax4_ins_pclk_not,
3778 
      CE => fax4_ins_FIFO1_multi_read_ins_used_not0002_454,
3779 
      CLR => frame_finished_wire,
3780 
      D => fax4_ins_FIFO1_multi_read_ins_Result_6_2,
3781 
      Q => fax4_ins_FIFO1_multi_read_ins_used(6)
3782 
    );
3783 
  fax4_ins_FIFO1_multi_read_ins_used_7 : FDCE
3784 
    generic map(
3785 
      INIT => '0'
3786 
    )
3787 
    port map (
3788 
      C => fax4_ins_pclk_not,
3789 
      CE => fax4_ins_FIFO1_multi_read_ins_used_not0002_454,
3790 
      CLR => frame_finished_wire,
3791 
      D => fax4_ins_FIFO1_multi_read_ins_Result_7_2,
3792 
      Q => fax4_ins_FIFO1_multi_read_ins_used(7)
3793 
    );
3794 
  fax4_ins_FIFO1_multi_read_ins_used_8 : FDCE
3795 
    generic map(
3796 
      INIT => '0'
3797 
    )
3798 
    port map (
3799 
      C => fax4_ins_pclk_not,
3800 
      CE => fax4_ins_FIFO1_multi_read_ins_used_not0002_454,
3801 
      CLR => frame_finished_wire,
3802 
      D => fax4_ins_FIFO1_multi_read_ins_Result_8_2,
3803 
      Q => fax4_ins_FIFO1_multi_read_ins_used(8)
3804 
    );
3805 
  fax4_ins_FIFO1_multi_read_ins_used_9 : FDCE
3806 
    generic map(
3807 
      INIT => '0'
3808 
    )
3809 
    port map (
3810 
      C => fax4_ins_pclk_not,
3811 
      CE => fax4_ins_FIFO1_multi_read_ins_used_not0002_454,
3812 
      CLR => frame_finished_wire,
3813 
      D => fax4_ins_FIFO1_multi_read_ins_Result_9_2,
3814 
      Q => fax4_ins_FIFO1_multi_read_ins_used(9)
3815 
    );
3816 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy_0_Q : MUXCY
3817 
    port map (
3818 
      CI => fax4_ins_FIFO1_multi_read_ins_used_not0003_inv,
3819 
      DI => fax4_ins_FIFO1_multi_read_ins_used(0),
3820 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(0),
3821 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(0)
3822 
    );
3823 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_xor_0_Q : XORCY
3824 
    port map (
3825 
      CI => fax4_ins_FIFO1_multi_read_ins_used_not0003_inv,
3826 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(0),
3827 
      O => fax4_ins_FIFO1_multi_read_ins_Result_0_2
3828 
    );
3829 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy_1_Q : MUXCY
3830 
    port map (
3831 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(0),
3832 
      DI => fax4_ins_FIFO1_multi_read_ins_used(1),
3833 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(1),
3834 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(1)
3835 
    );
3836 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_xor_1_Q : XORCY
3837 
    port map (
3838 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(0),
3839 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(1),
3840 
      O => fax4_ins_FIFO1_multi_read_ins_Result_1_2
3841 
    );
3842 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy_2_Q : MUXCY
3843 
    port map (
3844 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(1),
3845 
      DI => fax4_ins_FIFO1_multi_read_ins_used(2),
3846 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(2),
3847 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(2)
3848 
    );
3849 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_xor_2_Q : XORCY
3850 
    port map (
3851 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(1),
3852 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(2),
3853 
      O => fax4_ins_FIFO1_multi_read_ins_Result_2_2
3854 
    );
3855 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy_3_Q : MUXCY
3856 
    port map (
3857 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(2),
3858 
      DI => fax4_ins_FIFO1_multi_read_ins_used(3),
3859 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(3),
3860 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(3)
3861 
    );
3862 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_xor_3_Q : XORCY
3863 
    port map (
3864 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(2),
3865 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(3),
3866 
      O => fax4_ins_FIFO1_multi_read_ins_Result_3_2
3867 
    );
3868 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy_4_Q : MUXCY
3869 
    port map (
3870 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(3),
3871 
      DI => fax4_ins_FIFO1_multi_read_ins_used(4),
3872 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(4),
3873 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(4)
3874 
    );
3875 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_xor_4_Q : XORCY
3876 
    port map (
3877 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(3),
3878 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(4),
3879 
      O => fax4_ins_FIFO1_multi_read_ins_Result_4_2
3880 
    );
3881 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy_5_Q : MUXCY
3882 
    port map (
3883 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(4),
3884 
      DI => fax4_ins_FIFO1_multi_read_ins_used(5),
3885 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(5),
3886 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(5)
3887 
    );
3888 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_xor_5_Q : XORCY
3889 
    port map (
3890 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(4),
3891 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(5),
3892 
      O => fax4_ins_FIFO1_multi_read_ins_Result_5_2
3893 
    );
3894 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy_6_Q : MUXCY
3895 
    port map (
3896 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(5),
3897 
      DI => fax4_ins_FIFO1_multi_read_ins_used(6),
3898 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(6),
3899 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(6)
3900 
    );
3901 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_xor_6_Q : XORCY
3902 
    port map (
3903 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(5),
3904 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(6),
3905 
      O => fax4_ins_FIFO1_multi_read_ins_Result_6_2
3906 
    );
3907 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy_7_Q : MUXCY
3908 
    port map (
3909 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(6),
3910 
      DI => fax4_ins_FIFO1_multi_read_ins_used(7),
3911 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(7),
3912 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(7)
3913 
    );
3914 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_xor_7_Q : XORCY
3915 
    port map (
3916 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(6),
3917 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(7),
3918 
      O => fax4_ins_FIFO1_multi_read_ins_Result_7_2
3919 
    );
3920 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy_8_Q : MUXCY
3921 
    port map (
3922 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(7),
3923 
      DI => fax4_ins_FIFO1_multi_read_ins_used(8),
3924 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(8),
3925 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(8)
3926 
    );
3927 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_xor_8_Q : XORCY
3928 
    port map (
3929 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(7),
3930 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(8),
3931 
      O => fax4_ins_FIFO1_multi_read_ins_Result_8_2
3932 
    );
3933 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_xor_9_Q : XORCY
3934 
    port map (
3935 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_cy(8),
3936 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(9),
3937 
      O => fax4_ins_FIFO1_multi_read_ins_Result_9_2
3938 
    );
3939 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_0_Q : MUXCY
3940 
    port map (
3941 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
3942 
      DI => N1,
3943 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_lut(0),
3944 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(0)
3945 
    );
3946 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_0_Q : XORCY
3947 
    port map (
3948 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
3949 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_lut(0),
3950 
      O => fax4_ins_FIFO1_multi_read_ins_Result(0)
3951 
    );
3952 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_1_Q : MUXCY
3953 
    port map (
3954 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(0),
3955 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
3956 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_1_rt_234,
3957 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(1)
3958 
    );
3959 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_1_Q : XORCY
3960 
    port map (
3961 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(0),
3962 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_1_rt_234,
3963 
      O => fax4_ins_FIFO1_multi_read_ins_Result(1)
3964 
    );
3965 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_2_Q : MUXCY
3966 
    port map (
3967 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(1),
3968 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
3969 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_2_rt_236,
3970 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(2)
3971 
    );
3972 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_2_Q : XORCY
3973 
    port map (
3974 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(1),
3975 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_2_rt_236,
3976 
      O => fax4_ins_FIFO1_multi_read_ins_Result(2)
3977 
    );
3978 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_3_Q : MUXCY
3979 
    port map (
3980 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(2),
3981 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
3982 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_3_rt_238,
3983 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(3)
3984 
    );
3985 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_3_Q : XORCY
3986 
    port map (
3987 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(2),
3988 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_3_rt_238,
3989 
      O => fax4_ins_FIFO1_multi_read_ins_Result(3)
3990 
    );
3991 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_4_Q : MUXCY
3992 
    port map (
3993 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(3),
3994 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
3995 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_4_rt_240,
3996 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(4)
3997 
    );
3998 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_4_Q : XORCY
3999 
    port map (
4000 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(3),
4001 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_4_rt_240,
4002 
      O => fax4_ins_FIFO1_multi_read_ins_Result(4)
4003 
    );
4004 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_5_Q : MUXCY
4005 
    port map (
4006 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(4),
4007 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4008 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_5_rt_242,
4009 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(5)
4010 
    );
4011 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_5_Q : XORCY
4012 
    port map (
4013 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(4),
4014 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_5_rt_242,
4015 
      O => fax4_ins_FIFO1_multi_read_ins_Result(5)
4016 
    );
4017 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_6_Q : MUXCY
4018 
    port map (
4019 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(5),
4020 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4021 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_6_rt_244,
4022 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(6)
4023 
    );
4024 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_6_Q : XORCY
4025 
    port map (
4026 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(5),
4027 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_6_rt_244,
4028 
      O => fax4_ins_FIFO1_multi_read_ins_Result(6)
4029 
    );
4030 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_7_Q : MUXCY
4031 
    port map (
4032 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(6),
4033 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4034 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_7_rt_246,
4035 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(7)
4036 
    );
4037 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_7_Q : XORCY
4038 
    port map (
4039 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(6),
4040 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_7_rt_246,
4041 
      O => fax4_ins_FIFO1_multi_read_ins_Result(7)
4042 
    );
4043 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_8_Q : MUXCY
4044 
    port map (
4045 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(7),
4046 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4047 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_8_rt_248,
4048 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(8)
4049 
    );
4050 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_8_Q : XORCY
4051 
    port map (
4052 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(7),
4053 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_8_rt_248,
4054 
      O => fax4_ins_FIFO1_multi_read_ins_Result(8)
4055 
    );
4056 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_9_Q : XORCY
4057 
    port map (
4058 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy(8),
4059 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_9_rt_260,
4060 
      O => fax4_ins_FIFO1_multi_read_ins_Result(9)
4061 
    );
4062 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_0_Q : MUXCY
4063 
    port map (
4064 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
4065 
      DI => N1,
4066 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_lut(0),
4067 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(0)
4068 
    );
4069 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_0_Q : XORCY
4070 
    port map (
4071 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
4072 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_lut(0),
4073 
      O => fax4_ins_FIFO1_multi_read_ins_Result_0_1
4074 
    );
4075 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_1_Q : MUXCY
4076 
    port map (
4077 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(0),
4078 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4079 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_1_rt_282,
4080 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(1)
4081 
    );
4082 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_1_Q : XORCY
4083 
    port map (
4084 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(0),
4085 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_1_rt_282,
4086 
      O => fax4_ins_FIFO1_multi_read_ins_Result_1_1
4087 
    );
4088 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_2_Q : MUXCY
4089 
    port map (
4090 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(1),
4091 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4092 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_2_rt_284,
4093 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(2)
4094 
    );
4095 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_2_Q : XORCY
4096 
    port map (
4097 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(1),
4098 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_2_rt_284,
4099 
      O => fax4_ins_FIFO1_multi_read_ins_Result_2_1
4100 
    );
4101 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_3_Q : MUXCY
4102 
    port map (
4103 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(2),
4104 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4105 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_3_rt_286,
4106 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(3)
4107 
    );
4108 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_3_Q : XORCY
4109 
    port map (
4110 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(2),
4111 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_3_rt_286,
4112 
      O => fax4_ins_FIFO1_multi_read_ins_Result_3_1
4113 
    );
4114 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_4_Q : MUXCY
4115 
    port map (
4116 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(3),
4117 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4118 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_4_rt_288,
4119 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(4)
4120 
    );
4121 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_4_Q : XORCY
4122 
    port map (
4123 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(3),
4124 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_4_rt_288,
4125 
      O => fax4_ins_FIFO1_multi_read_ins_Result_4_1
4126 
    );
4127 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_5_Q : MUXCY
4128 
    port map (
4129 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(4),
4130 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4131 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_5_rt_290,
4132 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(5)
4133 
    );
4134 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_5_Q : XORCY
4135 
    port map (
4136 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(4),
4137 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_5_rt_290,
4138 
      O => fax4_ins_FIFO1_multi_read_ins_Result_5_1
4139 
    );
4140 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_6_Q : MUXCY
4141 
    port map (
4142 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(5),
4143 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4144 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_6_rt_292,
4145 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(6)
4146 
    );
4147 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_6_Q : XORCY
4148 
    port map (
4149 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(5),
4150 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_6_rt_292,
4151 
      O => fax4_ins_FIFO1_multi_read_ins_Result_6_1
4152 
    );
4153 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_7_Q : MUXCY
4154 
    port map (
4155 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(6),
4156 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4157 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_7_rt_294,
4158 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(7)
4159 
    );
4160 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_7_Q : XORCY
4161 
    port map (
4162 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(6),
4163 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_7_rt_294,
4164 
      O => fax4_ins_FIFO1_multi_read_ins_Result_7_1
4165 
    );
4166 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_8_Q : MUXCY
4167 
    port map (
4168 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(7),
4169 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
4170 
      S => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_8_rt_296,
4171 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(8)
4172 
    );
4173 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_8_Q : XORCY
4174 
    port map (
4175 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(7),
4176 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_8_rt_296,
4177 
      O => fax4_ins_FIFO1_multi_read_ins_Result_8_1
4178 
    );
4179 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_9_Q : XORCY
4180 
    port map (
4181 
      CI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy(8),
4182 
      LI => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_9_rt_308,
4183 
      O => fax4_ins_FIFO1_multi_read_ins_Result_9_1
4184 
    );
4185 
  fax4_ins_FIFO2_multi_read_ins_to_white3_o : FDPE
4186 
    generic map(
4187 
      INIT => '0'
4188 
    )
4189 
    port map (
4190 
      C => fax4_ins_pclk_not,
4191 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4192 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_to_white,
4193 
      PRE => frame_finished_wire,
4194 
      Q => fax4_ins_FIFO2_multi_read_ins_to_white3_o_685
4195 
    );
4196 
  fax4_ins_FIFO2_multi_read_ins_data1_o_0 : FDE
4197 
    generic map(
4198 
      INIT => '0'
4199 
    )
4200 
    port map (
4201 
      C => fax4_ins_pclk_not,
4202 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4203 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_x(0),
4204 
      Q => fax4_ins_FIFO2_multi_read_ins_data1_o(0)
4205 
    );
4206 
  fax4_ins_FIFO2_multi_read_ins_data1_o_1 : FDE
4207 
    generic map(
4208 
      INIT => '0'
4209 
    )
4210 
    port map (
4211 
      C => fax4_ins_pclk_not,
4212 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4213 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_x(1),
4214 
      Q => fax4_ins_FIFO2_multi_read_ins_data1_o(1)
4215 
    );
4216 
  fax4_ins_FIFO2_multi_read_ins_data1_o_2 : FDE
4217 
    generic map(
4218 
      INIT => '0'
4219 
    )
4220 
    port map (
4221 
      C => fax4_ins_pclk_not,
4222 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4223 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_x(2),
4224 
      Q => fax4_ins_FIFO2_multi_read_ins_data1_o(2)
4225 
    );
4226 
  fax4_ins_FIFO2_multi_read_ins_data1_o_3 : FDE
4227 
    generic map(
4228 
      INIT => '0'
4229 
    )
4230 
    port map (
4231 
      C => fax4_ins_pclk_not,
4232 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4233 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_x(3),
4234 
      Q => fax4_ins_FIFO2_multi_read_ins_data1_o(3)
4235 
    );
4236 
  fax4_ins_FIFO2_multi_read_ins_data1_o_4 : FDE
4237 
    generic map(
4238 
      INIT => '0'
4239 
    )
4240 
    port map (
4241 
      C => fax4_ins_pclk_not,
4242 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4243 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_x(4),
4244 
      Q => fax4_ins_FIFO2_multi_read_ins_data1_o(4)
4245 
    );
4246 
  fax4_ins_FIFO2_multi_read_ins_data1_o_5 : FDE
4247 
    generic map(
4248 
      INIT => '0'
4249 
    )
4250 
    port map (
4251 
      C => fax4_ins_pclk_not,
4252 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4253 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_x(5),
4254 
      Q => fax4_ins_FIFO2_multi_read_ins_data1_o(5)
4255 
    );
4256 
  fax4_ins_FIFO2_multi_read_ins_data1_o_6 : FDE
4257 
    generic map(
4258 
      INIT => '0'
4259 
    )
4260 
    port map (
4261 
      C => fax4_ins_pclk_not,
4262 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4263 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_x(6),
4264 
      Q => fax4_ins_FIFO2_multi_read_ins_data1_o(6)
4265 
    );
4266 
  fax4_ins_FIFO2_multi_read_ins_data1_o_7 : FDE
4267 
    generic map(
4268 
      INIT => '0'
4269 
    )
4270 
    port map (
4271 
      C => fax4_ins_pclk_not,
4272 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4273 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_x(7),
4274 
      Q => fax4_ins_FIFO2_multi_read_ins_data1_o(7)
4275 
    );
4276 
  fax4_ins_FIFO2_multi_read_ins_data1_o_8 : FDE
4277 
    generic map(
4278 
      INIT => '0'
4279 
    )
4280 
    port map (
4281 
      C => fax4_ins_pclk_not,
4282 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4283 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_x(8),
4284 
      Q => fax4_ins_FIFO2_multi_read_ins_data1_o(8)
4285 
    );
4286 
  fax4_ins_FIFO2_multi_read_ins_data1_o_9 : FDE
4287 
    generic map(
4288 
      INIT => '0'
4289 
    )
4290 
    port map (
4291 
      C => fax4_ins_pclk_not,
4292 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4293 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_x(9),
4294 
      Q => fax4_ins_FIFO2_multi_read_ins_data1_o(9)
4295 
    );
4296 
  fax4_ins_FIFO2_multi_read_ins_valid1_o : FDCE
4297 
    generic map(
4298 
      INIT => '0'
4299 
    )
4300 
    port map (
4301 
      C => fax4_ins_pclk_not,
4302 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4303 
      CLR => frame_finished_wire,
4304 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_valid,
4305 
      Q => fax4_ins_FIFO2_multi_read_ins_valid1_o_698
4306 
    );
4307 
  fax4_ins_FIFO2_multi_read_ins_data2_o_0 : FDE
4308 
    generic map(
4309 
      INIT => '0'
4310 
    )
4311 
    port map (
4312 
      C => fax4_ins_pclk_not,
4313 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4314 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_x(0),
4315 
      Q => fax4_ins_FIFO2_multi_read_ins_data2_o(0)
4316 
    );
4317 
  fax4_ins_FIFO2_multi_read_ins_data2_o_1 : FDE
4318 
    generic map(
4319 
      INIT => '0'
4320 
    )
4321 
    port map (
4322 
      C => fax4_ins_pclk_not,
4323 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4324 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_x(1),
4325 
      Q => fax4_ins_FIFO2_multi_read_ins_data2_o(1)
4326 
    );
4327 
  fax4_ins_FIFO2_multi_read_ins_data2_o_2 : FDE
4328 
    generic map(
4329 
      INIT => '0'
4330 
    )
4331 
    port map (
4332 
      C => fax4_ins_pclk_not,
4333 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4334 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_x(2),
4335 
      Q => fax4_ins_FIFO2_multi_read_ins_data2_o(2)
4336 
    );
4337 
  fax4_ins_FIFO2_multi_read_ins_data2_o_3 : FDE
4338 
    generic map(
4339 
      INIT => '0'
4340 
    )
4341 
    port map (
4342 
      C => fax4_ins_pclk_not,
4343 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4344 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_x(3),
4345 
      Q => fax4_ins_FIFO2_multi_read_ins_data2_o(3)
4346 
    );
4347 
  fax4_ins_FIFO2_multi_read_ins_data2_o_4 : FDE
4348 
    generic map(
4349 
      INIT => '0'
4350 
    )
4351 
    port map (
4352 
      C => fax4_ins_pclk_not,
4353 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4354 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_x(4),
4355 
      Q => fax4_ins_FIFO2_multi_read_ins_data2_o(4)
4356 
    );
4357 
  fax4_ins_FIFO2_multi_read_ins_data2_o_5 : FDE
4358 
    generic map(
4359 
      INIT => '0'
4360 
    )
4361 
    port map (
4362 
      C => fax4_ins_pclk_not,
4363 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4364 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_x(5),
4365 
      Q => fax4_ins_FIFO2_multi_read_ins_data2_o(5)
4366 
    );
4367 
  fax4_ins_FIFO2_multi_read_ins_data2_o_6 : FDE
4368 
    generic map(
4369 
      INIT => '0'
4370 
    )
4371 
    port map (
4372 
      C => fax4_ins_pclk_not,
4373 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4374 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_x(6),
4375 
      Q => fax4_ins_FIFO2_multi_read_ins_data2_o(6)
4376 
    );
4377 
  fax4_ins_FIFO2_multi_read_ins_data2_o_7 : FDE
4378 
    generic map(
4379 
      INIT => '0'
4380 
    )
4381 
    port map (
4382 
      C => fax4_ins_pclk_not,
4383 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4384 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_x(7),
4385 
      Q => fax4_ins_FIFO2_multi_read_ins_data2_o(7)
4386 
    );
4387 
  fax4_ins_FIFO2_multi_read_ins_data2_o_8 : FDE
4388 
    generic map(
4389 
      INIT => '0'
4390 
    )
4391 
    port map (
4392 
      C => fax4_ins_pclk_not,
4393 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4394 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_x(8),
4395 
      Q => fax4_ins_FIFO2_multi_read_ins_data2_o(8)
4396 
    );
4397 
  fax4_ins_FIFO2_multi_read_ins_data2_o_9 : FDE
4398 
    generic map(
4399 
      INIT => '0'
4400 
    )
4401 
    port map (
4402 
      C => fax4_ins_pclk_not,
4403 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4404 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_x(9),
4405 
      Q => fax4_ins_FIFO2_multi_read_ins_data2_o(9)
4406 
    );
4407 
  fax4_ins_FIFO2_multi_read_ins_valid2_o : FDCE
4408 
    generic map(
4409 
      INIT => '0'
4410 
    )
4411 
    port map (
4412 
      C => fax4_ins_pclk_not,
4413 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4414 
      CLR => frame_finished_wire,
4415 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_valid,
4416 
      Q => fax4_ins_FIFO2_multi_read_ins_valid2_o_699
4417 
    );
4418 
  fax4_ins_FIFO2_multi_read_ins_data3_o_0 : FDE
4419 
    generic map(
4420 
      INIT => '0'
4421 
    )
4422 
    port map (
4423 
      C => fax4_ins_pclk_not,
4424 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4425 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_x(0),
4426 
      Q => fax4_ins_FIFO2_multi_read_ins_data3_o(0)
4427 
    );
4428 
  fax4_ins_FIFO2_multi_read_ins_data3_o_1 : FDE
4429 
    generic map(
4430 
      INIT => '0'
4431 
    )
4432 
    port map (
4433 
      C => fax4_ins_pclk_not,
4434 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4435 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_x(1),
4436 
      Q => fax4_ins_FIFO2_multi_read_ins_data3_o(1)
4437 
    );
4438 
  fax4_ins_FIFO2_multi_read_ins_data3_o_2 : FDE
4439 
    generic map(
4440 
      INIT => '0'
4441 
    )
4442 
    port map (
4443 
      C => fax4_ins_pclk_not,
4444 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4445 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_x(2),
4446 
      Q => fax4_ins_FIFO2_multi_read_ins_data3_o(2)
4447 
    );
4448 
  fax4_ins_FIFO2_multi_read_ins_data3_o_3 : FDE
4449 
    generic map(
4450 
      INIT => '0'
4451 
    )
4452 
    port map (
4453 
      C => fax4_ins_pclk_not,
4454 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4455 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_x(3),
4456 
      Q => fax4_ins_FIFO2_multi_read_ins_data3_o(3)
4457 
    );
4458 
  fax4_ins_FIFO2_multi_read_ins_data3_o_4 : FDE
4459 
    generic map(
4460 
      INIT => '0'
4461 
    )
4462 
    port map (
4463 
      C => fax4_ins_pclk_not,
4464 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4465 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_x(4),
4466 
      Q => fax4_ins_FIFO2_multi_read_ins_data3_o(4)
4467 
    );
4468 
  fax4_ins_FIFO2_multi_read_ins_data3_o_5 : FDE
4469 
    generic map(
4470 
      INIT => '0'
4471 
    )
4472 
    port map (
4473 
      C => fax4_ins_pclk_not,
4474 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4475 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_x(5),
4476 
      Q => fax4_ins_FIFO2_multi_read_ins_data3_o(5)
4477 
    );
4478 
  fax4_ins_FIFO2_multi_read_ins_data3_o_6 : FDE
4479 
    generic map(
4480 
      INIT => '0'
4481 
    )
4482 
    port map (
4483 
      C => fax4_ins_pclk_not,
4484 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4485 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_x(6),
4486 
      Q => fax4_ins_FIFO2_multi_read_ins_data3_o(6)
4487 
    );
4488 
  fax4_ins_FIFO2_multi_read_ins_data3_o_7 : FDE
4489 
    generic map(
4490 
      INIT => '0'
4491 
    )
4492 
    port map (
4493 
      C => fax4_ins_pclk_not,
4494 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4495 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_x(7),
4496 
      Q => fax4_ins_FIFO2_multi_read_ins_data3_o(7)
4497 
    );
4498 
  fax4_ins_FIFO2_multi_read_ins_data3_o_8 : FDE
4499 
    generic map(
4500 
      INIT => '0'
4501 
    )
4502 
    port map (
4503 
      C => fax4_ins_pclk_not,
4504 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4505 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_x(8),
4506 
      Q => fax4_ins_FIFO2_multi_read_ins_data3_o(8)
4507 
    );
4508 
  fax4_ins_FIFO2_multi_read_ins_data3_o_9 : FDE
4509 
    generic map(
4510 
      INIT => '0'
4511 
    )
4512 
    port map (
4513 
      C => fax4_ins_pclk_not,
4514 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4515 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_x(9),
4516 
      Q => fax4_ins_FIFO2_multi_read_ins_data3_o(9)
4517 
    );
4518 
  fax4_ins_FIFO2_multi_read_ins_valid3_o : FDCE
4519 
    generic map(
4520 
      INIT => '0'
4521 
    )
4522 
    port map (
4523 
      C => fax4_ins_pclk_not,
4524 
      CE => fax4_ins_FIFO2_multi_read_ins_latch3,
4525 
      CLR => frame_finished_wire,
4526 
      D => fax4_ins_FIFO2_multi_read_ins_mux3_valid,
4527 
      Q => fax4_ins_FIFO2_multi_read_ins_valid3_o_700
4528 
    );
4529 
  fax4_ins_FIFO2_multi_read_ins_to_white1_o : FDPE
4530 
    generic map(
4531 
      INIT => '0'
4532 
    )
4533 
    port map (
4534 
      C => fax4_ins_pclk_not,
4535 
      CE => fax4_ins_FIFO2_multi_read_ins_latch1,
4536 
      D => fax4_ins_FIFO2_multi_read_ins_mux1_to_white,
4537 
      PRE => frame_finished_wire,
4538 
      Q => fax4_ins_FIFO2_multi_read_ins_to_white1_o_683
4539 
    );
4540 
  fax4_ins_FIFO2_multi_read_ins_to_white2_o : FDPE
4541 
    generic map(
4542 
      INIT => '0'
4543 
    )
4544 
    port map (
4545 
      C => fax4_ins_pclk_not,
4546 
      CE => fax4_ins_FIFO2_multi_read_ins_latch2,
4547 
      D => fax4_ins_FIFO2_multi_read_ins_mux2_to_white,
4548 
      PRE => frame_finished_wire,
4549 
      Q => fax4_ins_FIFO2_multi_read_ins_to_white2_o_684
4550 
    );
4551 
  fax4_ins_FIFO2_multi_read_ins_read_pos_0 : FDCE
4552 
    generic map(
4553 
      INIT => '0'
4554 
    )
4555 
    port map (
4556 
      C => fax4_ins_pclk_not,
4557 
      CE => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
4558 
      CLR => frame_finished_wire,
4559 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_0,
4560 
      Q => fax4_ins_FIFO2_multi_read_ins_read_pos(0)
4561 
    );
4562 
  fax4_ins_FIFO2_multi_read_ins_read_pos_1 : FDCE
4563 
    generic map(
4564 
      INIT => '0'
4565 
    )
4566 
    port map (
4567 
      C => fax4_ins_pclk_not,
4568 
      CE => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
4569 
      CLR => frame_finished_wire,
4570 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_1,
4571 
      Q => fax4_ins_FIFO2_multi_read_ins_read_pos(1)
4572 
    );
4573 
  fax4_ins_FIFO2_multi_read_ins_read_pos_2 : FDCE
4574 
    generic map(
4575 
      INIT => '0'
4576 
    )
4577 
    port map (
4578 
      C => fax4_ins_pclk_not,
4579 
      CE => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
4580 
      CLR => frame_finished_wire,
4581 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_2,
4582 
      Q => fax4_ins_FIFO2_multi_read_ins_read_pos(2)
4583 
    );
4584 
  fax4_ins_FIFO2_multi_read_ins_read_pos_3 : FDCE
4585 
    generic map(
4586 
      INIT => '0'
4587 
    )
4588 
    port map (
4589 
      C => fax4_ins_pclk_not,
4590 
      CE => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
4591 
      CLR => frame_finished_wire,
4592 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_3,
4593 
      Q => fax4_ins_FIFO2_multi_read_ins_read_pos(3)
4594 
    );
4595 
  fax4_ins_FIFO2_multi_read_ins_read_pos_4 : FDCE
4596 
    generic map(
4597 
      INIT => '0'
4598 
    )
4599 
    port map (
4600 
      C => fax4_ins_pclk_not,
4601 
      CE => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
4602 
      CLR => frame_finished_wire,
4603 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_4,
4604 
      Q => fax4_ins_FIFO2_multi_read_ins_read_pos(4)
4605 
    );
4606 
  fax4_ins_FIFO2_multi_read_ins_read_pos_5 : FDCE
4607 
    generic map(
4608 
      INIT => '0'
4609 
    )
4610 
    port map (
4611 
      C => fax4_ins_pclk_not,
4612 
      CE => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
4613 
      CLR => frame_finished_wire,
4614 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_5,
4615 
      Q => fax4_ins_FIFO2_multi_read_ins_read_pos(5)
4616 
    );
4617 
  fax4_ins_FIFO2_multi_read_ins_read_pos_6 : FDCE
4618 
    generic map(
4619 
      INIT => '0'
4620 
    )
4621 
    port map (
4622 
      C => fax4_ins_pclk_not,
4623 
      CE => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
4624 
      CLR => frame_finished_wire,
4625 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_6,
4626 
      Q => fax4_ins_FIFO2_multi_read_ins_read_pos(6)
4627 
    );
4628 
  fax4_ins_FIFO2_multi_read_ins_read_pos_7 : FDCE
4629 
    generic map(
4630 
      INIT => '0'
4631 
    )
4632 
    port map (
4633 
      C => fax4_ins_pclk_not,
4634 
      CE => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
4635 
      CLR => frame_finished_wire,
4636 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_7,
4637 
      Q => fax4_ins_FIFO2_multi_read_ins_read_pos(7)
4638 
    );
4639 
  fax4_ins_FIFO2_multi_read_ins_read_pos_8 : FDCE
4640 
    generic map(
4641 
      INIT => '0'
4642 
    )
4643 
    port map (
4644 
      C => fax4_ins_pclk_not,
4645 
      CE => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
4646 
      CLR => frame_finished_wire,
4647 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_8,
4648 
      Q => fax4_ins_FIFO2_multi_read_ins_read_pos(8)
4649 
    );
4650 
  fax4_ins_FIFO2_multi_read_ins_read_pos_9 : FDCE
4651 
    generic map(
4652 
      INIT => '0'
4653 
    )
4654 
    port map (
4655 
      C => fax4_ins_pclk_not,
4656 
      CE => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
4657 
      CLR => frame_finished_wire,
4658 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_9,
4659 
      Q => fax4_ins_FIFO2_multi_read_ins_read_pos(9)
4660 
    );
4661 
  fax4_ins_FIFO2_multi_read_ins_write_pos_0 : FDCE
4662 
    generic map(
4663 
      INIT => '0'
4664 
    )
4665 
    port map (
4666 
      C => fax4_ins_pclk_not,
4667 
      CE => fax4_ins_FIFO2_multi_read_ins_wr,
4668 
      CLR => frame_finished_wire,
4669 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_0,
4670 
      Q => fax4_ins_FIFO2_multi_read_ins_write_pos(0)
4671 
    );
4672 
  fax4_ins_FIFO2_multi_read_ins_write_pos_1 : FDCE
4673 
    generic map(
4674 
      INIT => '0'
4675 
    )
4676 
    port map (
4677 
      C => fax4_ins_pclk_not,
4678 
      CE => fax4_ins_FIFO2_multi_read_ins_wr,
4679 
      CLR => frame_finished_wire,
4680 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_1,
4681 
      Q => fax4_ins_FIFO2_multi_read_ins_write_pos(1)
4682 
    );
4683 
  fax4_ins_FIFO2_multi_read_ins_write_pos_2 : FDCE
4684 
    generic map(
4685 
      INIT => '0'
4686 
    )
4687 
    port map (
4688 
      C => fax4_ins_pclk_not,
4689 
      CE => fax4_ins_FIFO2_multi_read_ins_wr,
4690 
      CLR => frame_finished_wire,
4691 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_2,
4692 
      Q => fax4_ins_FIFO2_multi_read_ins_write_pos(2)
4693 
    );
4694 
  fax4_ins_FIFO2_multi_read_ins_write_pos_3 : FDCE
4695 
    generic map(
4696 
      INIT => '0'
4697 
    )
4698 
    port map (
4699 
      C => fax4_ins_pclk_not,
4700 
      CE => fax4_ins_FIFO2_multi_read_ins_wr,
4701 
      CLR => frame_finished_wire,
4702 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_3,
4703 
      Q => fax4_ins_FIFO2_multi_read_ins_write_pos(3)
4704 
    );
4705 
  fax4_ins_FIFO2_multi_read_ins_write_pos_4 : FDCE
4706 
    generic map(
4707 
      INIT => '0'
4708 
    )
4709 
    port map (
4710 
      C => fax4_ins_pclk_not,
4711 
      CE => fax4_ins_FIFO2_multi_read_ins_wr,
4712 
      CLR => frame_finished_wire,
4713 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_4,
4714 
      Q => fax4_ins_FIFO2_multi_read_ins_write_pos(4)
4715 
    );
4716 
  fax4_ins_FIFO2_multi_read_ins_write_pos_5 : FDCE
4717 
    generic map(
4718 
      INIT => '0'
4719 
    )
4720 
    port map (
4721 
      C => fax4_ins_pclk_not,
4722 
      CE => fax4_ins_FIFO2_multi_read_ins_wr,
4723 
      CLR => frame_finished_wire,
4724 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_5,
4725 
      Q => fax4_ins_FIFO2_multi_read_ins_write_pos(5)
4726 
    );
4727 
  fax4_ins_FIFO2_multi_read_ins_write_pos_6 : FDCE
4728 
    generic map(
4729 
      INIT => '0'
4730 
    )
4731 
    port map (
4732 
      C => fax4_ins_pclk_not,
4733 
      CE => fax4_ins_FIFO2_multi_read_ins_wr,
4734 
      CLR => frame_finished_wire,
4735 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_6,
4736 
      Q => fax4_ins_FIFO2_multi_read_ins_write_pos(6)
4737 
    );
4738 
  fax4_ins_FIFO2_multi_read_ins_write_pos_7 : FDCE
4739 
    generic map(
4740 
      INIT => '0'
4741 
    )
4742 
    port map (
4743 
      C => fax4_ins_pclk_not,
4744 
      CE => fax4_ins_FIFO2_multi_read_ins_wr,
4745 
      CLR => frame_finished_wire,
4746 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_7,
4747 
      Q => fax4_ins_FIFO2_multi_read_ins_write_pos(7)
4748 
    );
4749 
  fax4_ins_FIFO2_multi_read_ins_write_pos_8 : FDCE
4750 
    generic map(
4751 
      INIT => '0'
4752 
    )
4753 
    port map (
4754 
      C => fax4_ins_pclk_not,
4755 
      CE => fax4_ins_FIFO2_multi_read_ins_wr,
4756 
      CLR => frame_finished_wire,
4757 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_8,
4758 
      Q => fax4_ins_FIFO2_multi_read_ins_write_pos(8)
4759 
    );
4760 
  fax4_ins_FIFO2_multi_read_ins_write_pos_9 : FDCE
4761 
    generic map(
4762 
      INIT => '0'
4763 
    )
4764 
    port map (
4765 
      C => fax4_ins_pclk_not,
4766 
      CE => fax4_ins_FIFO2_multi_read_ins_wr,
4767 
      CLR => frame_finished_wire,
4768 
      D => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_9,
4769 
      Q => fax4_ins_FIFO2_multi_read_ins_write_pos(9)
4770 
    );
4771 
  fax4_ins_FIFO2_multi_read_ins_used_0 : FDCE
4772 
    generic map(
4773 
      INIT => '0'
4774 
    )
4775 
    port map (
4776 
      C => fax4_ins_pclk_not,
4777 
      CE => fax4_ins_FIFO2_multi_read_ins_used_not0002_696,
4778 
      CLR => frame_finished_wire,
4779 
      D => fax4_ins_FIFO2_multi_read_ins_Result_0_2,
4780 
      Q => fax4_ins_FIFO2_multi_read_ins_used(0)
4781 
    );
4782 
  fax4_ins_FIFO2_multi_read_ins_used_1 : FDCE
4783 
    generic map(
4784 
      INIT => '0'
4785 
    )
4786 
    port map (
4787 
      C => fax4_ins_pclk_not,
4788 
      CE => fax4_ins_FIFO2_multi_read_ins_used_not0002_696,
4789 
      CLR => frame_finished_wire,
4790 
      D => fax4_ins_FIFO2_multi_read_ins_Result_1_2,
4791 
      Q => fax4_ins_FIFO2_multi_read_ins_used(1)
4792 
    );
4793 
  fax4_ins_FIFO2_multi_read_ins_used_2 : FDCE
4794 
    generic map(
4795 
      INIT => '0'
4796 
    )
4797 
    port map (
4798 
      C => fax4_ins_pclk_not,
4799 
      CE => fax4_ins_FIFO2_multi_read_ins_used_not0002_696,
4800 
      CLR => frame_finished_wire,
4801 
      D => fax4_ins_FIFO2_multi_read_ins_Result_2_2,
4802 
      Q => fax4_ins_FIFO2_multi_read_ins_used(2)
4803 
    );
4804 
  fax4_ins_FIFO2_multi_read_ins_used_3 : FDCE
4805 
    generic map(
4806 
      INIT => '0'
4807 
    )
4808 
    port map (
4809 
      C => fax4_ins_pclk_not,
4810 
      CE => fax4_ins_FIFO2_multi_read_ins_used_not0002_696,
4811 
      CLR => frame_finished_wire,
4812 
      D => fax4_ins_FIFO2_multi_read_ins_Result_3_2,
4813 
      Q => fax4_ins_FIFO2_multi_read_ins_used(3)
4814 
    );
4815 
  fax4_ins_FIFO2_multi_read_ins_used_4 : FDCE
4816 
    generic map(
4817 
      INIT => '0'
4818 
    )
4819 
    port map (
4820 
      C => fax4_ins_pclk_not,
4821 
      CE => fax4_ins_FIFO2_multi_read_ins_used_not0002_696,
4822 
      CLR => frame_finished_wire,
4823 
      D => fax4_ins_FIFO2_multi_read_ins_Result_4_2,
4824 
      Q => fax4_ins_FIFO2_multi_read_ins_used(4)
4825 
    );
4826 
  fax4_ins_FIFO2_multi_read_ins_used_5 : FDCE
4827 
    generic map(
4828 
      INIT => '0'
4829 
    )
4830 
    port map (
4831 
      C => fax4_ins_pclk_not,
4832 
      CE => fax4_ins_FIFO2_multi_read_ins_used_not0002_696,
4833 
      CLR => frame_finished_wire,
4834 
      D => fax4_ins_FIFO2_multi_read_ins_Result_5_2,
4835 
      Q => fax4_ins_FIFO2_multi_read_ins_used(5)
4836 
    );
4837 
  fax4_ins_FIFO2_multi_read_ins_used_6 : FDCE
4838 
    generic map(
4839 
      INIT => '0'
4840 
    )
4841 
    port map (
4842 
      C => fax4_ins_pclk_not,
4843 
      CE => fax4_ins_FIFO2_multi_read_ins_used_not0002_696,
4844 
      CLR => frame_finished_wire,
4845 
      D => fax4_ins_FIFO2_multi_read_ins_Result_6_2,
4846 
      Q => fax4_ins_FIFO2_multi_read_ins_used(6)
4847 
    );
4848 
  fax4_ins_FIFO2_multi_read_ins_used_7 : FDCE
4849 
    generic map(
4850 
      INIT => '0'
4851 
    )
4852 
    port map (
4853 
      C => fax4_ins_pclk_not,
4854 
      CE => fax4_ins_FIFO2_multi_read_ins_used_not0002_696,
4855 
      CLR => frame_finished_wire,
4856 
      D => fax4_ins_FIFO2_multi_read_ins_Result_7_2,
4857 
      Q => fax4_ins_FIFO2_multi_read_ins_used(7)
4858 
    );
4859 
  fax4_ins_FIFO2_multi_read_ins_used_8 : FDCE
4860 
    generic map(
4861 
      INIT => '0'
4862 
    )
4863 
    port map (
4864 
      C => fax4_ins_pclk_not,
4865 
      CE => fax4_ins_FIFO2_multi_read_ins_used_not0002_696,
4866 
      CLR => frame_finished_wire,
4867 
      D => fax4_ins_FIFO2_multi_read_ins_Result_8_2,
4868 
      Q => fax4_ins_FIFO2_multi_read_ins_used(8)
4869 
    );
4870 
  fax4_ins_FIFO2_multi_read_ins_used_9 : FDCE
4871 
    generic map(
4872 
      INIT => '0'
4873 
    )
4874 
    port map (
4875 
      C => fax4_ins_pclk_not,
4876 
      CE => fax4_ins_FIFO2_multi_read_ins_used_not0002_696,
4877 
      CLR => frame_finished_wire,
4878 
      D => fax4_ins_FIFO2_multi_read_ins_Result_9_2,
4879 
      Q => fax4_ins_FIFO2_multi_read_ins_used(9)
4880 
    );
4881 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy_0_Q : MUXCY
4882 
    port map (
4883 
      CI => fax4_ins_FIFO2_multi_read_ins_used_not0003_inv,
4884 
      DI => fax4_ins_FIFO2_multi_read_ins_used(0),
4885 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(0),
4886 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(0)
4887 
    );
4888 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_xor_0_Q : XORCY
4889 
    port map (
4890 
      CI => fax4_ins_FIFO2_multi_read_ins_used_not0003_inv,
4891 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(0),
4892 
      O => fax4_ins_FIFO2_multi_read_ins_Result_0_2
4893 
    );
4894 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy_1_Q : MUXCY
4895 
    port map (
4896 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(0),
4897 
      DI => fax4_ins_FIFO2_multi_read_ins_used(1),
4898 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(1),
4899 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(1)
4900 
    );
4901 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_xor_1_Q : XORCY
4902 
    port map (
4903 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(0),
4904 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(1),
4905 
      O => fax4_ins_FIFO2_multi_read_ins_Result_1_2
4906 
    );
4907 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy_2_Q : MUXCY
4908 
    port map (
4909 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(1),
4910 
      DI => fax4_ins_FIFO2_multi_read_ins_used(2),
4911 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(2),
4912 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(2)
4913 
    );
4914 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_xor_2_Q : XORCY
4915 
    port map (
4916 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(1),
4917 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(2),
4918 
      O => fax4_ins_FIFO2_multi_read_ins_Result_2_2
4919 
    );
4920 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy_3_Q : MUXCY
4921 
    port map (
4922 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(2),
4923 
      DI => fax4_ins_FIFO2_multi_read_ins_used(3),
4924 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(3),
4925 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(3)
4926 
    );
4927 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_xor_3_Q : XORCY
4928 
    port map (
4929 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(2),
4930 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(3),
4931 
      O => fax4_ins_FIFO2_multi_read_ins_Result_3_2
4932 
    );
4933 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy_4_Q : MUXCY
4934 
    port map (
4935 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(3),
4936 
      DI => fax4_ins_FIFO2_multi_read_ins_used(4),
4937 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(4),
4938 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(4)
4939 
    );
4940 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_xor_4_Q : XORCY
4941 
    port map (
4942 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(3),
4943 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(4),
4944 
      O => fax4_ins_FIFO2_multi_read_ins_Result_4_2
4945 
    );
4946 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy_5_Q : MUXCY
4947 
    port map (
4948 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(4),
4949 
      DI => fax4_ins_FIFO2_multi_read_ins_used(5),
4950 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(5),
4951 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(5)
4952 
    );
4953 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_xor_5_Q : XORCY
4954 
    port map (
4955 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(4),
4956 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(5),
4957 
      O => fax4_ins_FIFO2_multi_read_ins_Result_5_2
4958 
    );
4959 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy_6_Q : MUXCY
4960 
    port map (
4961 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(5),
4962 
      DI => fax4_ins_FIFO2_multi_read_ins_used(6),
4963 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(6),
4964 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(6)
4965 
    );
4966 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_xor_6_Q : XORCY
4967 
    port map (
4968 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(5),
4969 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(6),
4970 
      O => fax4_ins_FIFO2_multi_read_ins_Result_6_2
4971 
    );
4972 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy_7_Q : MUXCY
4973 
    port map (
4974 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(6),
4975 
      DI => fax4_ins_FIFO2_multi_read_ins_used(7),
4976 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(7),
4977 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(7)
4978 
    );
4979 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_xor_7_Q : XORCY
4980 
    port map (
4981 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(6),
4982 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(7),
4983 
      O => fax4_ins_FIFO2_multi_read_ins_Result_7_2
4984 
    );
4985 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy_8_Q : MUXCY
4986 
    port map (
4987 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(7),
4988 
      DI => fax4_ins_FIFO2_multi_read_ins_used(8),
4989 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(8),
4990 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(8)
4991 
    );
4992 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_xor_8_Q : XORCY
4993 
    port map (
4994 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(7),
4995 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(8),
4996 
      O => fax4_ins_FIFO2_multi_read_ins_Result_8_2
4997 
    );
4998 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_xor_9_Q : XORCY
4999 
    port map (
5000 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_cy(8),
5001 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(9),
5002 
      O => fax4_ins_FIFO2_multi_read_ins_Result_9_2
5003 
    );
5004 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_0_Q : MUXCY
5005 
    port map (
5006 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
5007 
      DI => N1,
5008 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_lut(0),
5009 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(0)
5010 
    );
5011 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_0_Q : XORCY
5012 
    port map (
5013 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
5014 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_lut(0),
5015 
      O => fax4_ins_FIFO2_multi_read_ins_Result(0)
5016 
    );
5017 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_1_Q : MUXCY
5018 
    port map (
5019 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(0),
5020 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5021 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_1_rt_475,
5022 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(1)
5023 
    );
5024 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_1_Q : XORCY
5025 
    port map (
5026 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(0),
5027 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_1_rt_475,
5028 
      O => fax4_ins_FIFO2_multi_read_ins_Result(1)
5029 
    );
5030 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_2_Q : MUXCY
5031 
    port map (
5032 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(1),
5033 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5034 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_2_rt_477,
5035 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(2)
5036 
    );
5037 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_2_Q : XORCY
5038 
    port map (
5039 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(1),
5040 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_2_rt_477,
5041 
      O => fax4_ins_FIFO2_multi_read_ins_Result(2)
5042 
    );
5043 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_3_Q : MUXCY
5044 
    port map (
5045 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(2),
5046 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5047 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_3_rt_479,
5048 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(3)
5049 
    );
5050 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_3_Q : XORCY
5051 
    port map (
5052 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(2),
5053 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_3_rt_479,
5054 
      O => fax4_ins_FIFO2_multi_read_ins_Result(3)
5055 
    );
5056 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_4_Q : MUXCY
5057 
    port map (
5058 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(3),
5059 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5060 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_4_rt_481,
5061 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(4)
5062 
    );
5063 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_4_Q : XORCY
5064 
    port map (
5065 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(3),
5066 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_4_rt_481,
5067 
      O => fax4_ins_FIFO2_multi_read_ins_Result(4)
5068 
    );
5069 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_5_Q : MUXCY
5070 
    port map (
5071 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(4),
5072 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5073 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_5_rt_483,
5074 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(5)
5075 
    );
5076 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_5_Q : XORCY
5077 
    port map (
5078 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(4),
5079 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_5_rt_483,
5080 
      O => fax4_ins_FIFO2_multi_read_ins_Result(5)
5081 
    );
5082 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_6_Q : MUXCY
5083 
    port map (
5084 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(5),
5085 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5086 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_6_rt_485,
5087 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(6)
5088 
    );
5089 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_6_Q : XORCY
5090 
    port map (
5091 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(5),
5092 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_6_rt_485,
5093 
      O => fax4_ins_FIFO2_multi_read_ins_Result(6)
5094 
    );
5095 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_7_Q : MUXCY
5096 
    port map (
5097 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(6),
5098 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5099 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_7_rt_487,
5100 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(7)
5101 
    );
5102 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_7_Q : XORCY
5103 
    port map (
5104 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(6),
5105 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_7_rt_487,
5106 
      O => fax4_ins_FIFO2_multi_read_ins_Result(7)
5107 
    );
5108 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_8_Q : MUXCY
5109 
    port map (
5110 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(7),
5111 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5112 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_8_rt_489,
5113 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(8)
5114 
    );
5115 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_8_Q : XORCY
5116 
    port map (
5117 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(7),
5118 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_8_rt_489,
5119 
      O => fax4_ins_FIFO2_multi_read_ins_Result(8)
5120 
    );
5121 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_9_Q : XORCY
5122 
    port map (
5123 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy(8),
5124 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_9_rt_501,
5125 
      O => fax4_ins_FIFO2_multi_read_ins_Result(9)
5126 
    );
5127 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_0_Q : MUXCY
5128 
    port map (
5129 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
5130 
      DI => N1,
5131 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_lut(0),
5132 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(0)
5133 
    );
5134 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_0_Q : XORCY
5135 
    port map (
5136 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
5137 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_lut(0),
5138 
      O => fax4_ins_FIFO2_multi_read_ins_Result_0_1
5139 
    );
5140 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_1_Q : MUXCY
5141 
    port map (
5142 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(0),
5143 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5144 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_1_rt_523,
5145 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(1)
5146 
    );
5147 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_1_Q : XORCY
5148 
    port map (
5149 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(0),
5150 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_1_rt_523,
5151 
      O => fax4_ins_FIFO2_multi_read_ins_Result_1_1
5152 
    );
5153 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_2_Q : MUXCY
5154 
    port map (
5155 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(1),
5156 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5157 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_2_rt_525,
5158 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(2)
5159 
    );
5160 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_2_Q : XORCY
5161 
    port map (
5162 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(1),
5163 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_2_rt_525,
5164 
      O => fax4_ins_FIFO2_multi_read_ins_Result_2_1
5165 
    );
5166 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_3_Q : MUXCY
5167 
    port map (
5168 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(2),
5169 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5170 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_3_rt_527,
5171 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(3)
5172 
    );
5173 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_3_Q : XORCY
5174 
    port map (
5175 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(2),
5176 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_3_rt_527,
5177 
      O => fax4_ins_FIFO2_multi_read_ins_Result_3_1
5178 
    );
5179 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_4_Q : MUXCY
5180 
    port map (
5181 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(3),
5182 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5183 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_4_rt_529,
5184 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(4)
5185 
    );
5186 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_4_Q : XORCY
5187 
    port map (
5188 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(3),
5189 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_4_rt_529,
5190 
      O => fax4_ins_FIFO2_multi_read_ins_Result_4_1
5191 
    );
5192 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_5_Q : MUXCY
5193 
    port map (
5194 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(4),
5195 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5196 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_5_rt_531,
5197 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(5)
5198 
    );
5199 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_5_Q : XORCY
5200 
    port map (
5201 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(4),
5202 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_5_rt_531,
5203 
      O => fax4_ins_FIFO2_multi_read_ins_Result_5_1
5204 
    );
5205 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_6_Q : MUXCY
5206 
    port map (
5207 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(5),
5208 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5209 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_6_rt_533,
5210 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(6)
5211 
    );
5212 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_6_Q : XORCY
5213 
    port map (
5214 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(5),
5215 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_6_rt_533,
5216 
      O => fax4_ins_FIFO2_multi_read_ins_Result_6_1
5217 
    );
5218 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_7_Q : MUXCY
5219 
    port map (
5220 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(6),
5221 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5222 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_7_rt_535,
5223 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(7)
5224 
    );
5225 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_7_Q : XORCY
5226 
    port map (
5227 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(6),
5228 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_7_rt_535,
5229 
      O => fax4_ins_FIFO2_multi_read_ins_Result_7_1
5230 
    );
5231 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_8_Q : MUXCY
5232 
    port map (
5233 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(7),
5234 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5235 
      S => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_8_rt_537,
5236 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(8)
5237 
    );
5238 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_8_Q : XORCY
5239 
    port map (
5240 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(7),
5241 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_8_rt_537,
5242 
      O => fax4_ins_FIFO2_multi_read_ins_Result_8_1
5243 
    );
5244 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_9_Q : XORCY
5245 
    port map (
5246 
      CI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy(8),
5247 
      LI => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_9_rt_549,
5248 
      O => fax4_ins_FIFO2_multi_read_ins_Result_9_1
5249 
    );
5250 
  fax4_ins_state_FSM_FFd10 : FD
5251 
    generic map(
5252 
      INIT => '0'
5253 
    )
5254 
    port map (
5255 
      C => pclk_i,
5256 
      D => fax4_ins_state_FSM_FFd10_In_1324,
5257 
      Q => fax4_ins_state_FSM_FFd10_1323
5258 
    );
5259 
  fax4_ins_state_FSM_FFd5 : FD
5260 
    generic map(
5261 
      INIT => '0'
5262 
    )
5263 
    port map (
5264 
      C => pclk_i,
5265 
      D => fax4_ins_state_FSM_FFd5_In,
5266 
      Q => fax4_ins_state_FSM_FFd5_1333
5267 
    );
5268 
  fax4_ins_state_FSM_FFd6 : FD
5269 
    generic map(
5270 
      INIT => '0'
5271 
    )
5272 
    port map (
5273 
      C => pclk_i,
5274 
      D => fax4_ins_state_FSM_FFd6_In_1337,
5275 
      Q => fax4_ins_state_FSM_FFd6_1336
5276 
    );
5277 
  fax4_ins_state_FSM_FFd2 : FD
5278 
    generic map(
5279 
      INIT => '0'
5280 
    )
5281 
    port map (
5282 
      C => pclk_i,
5283 
      D => fax4_ins_state_FSM_FFd2_In_1328,
5284 
      Q => fax4_ins_state_FSM_FFd2_1327
5285 
    );
5286 
  fax4_ins_state_FSM_FFd3 : FD
5287 
    generic map(
5288 
      INIT => '0'
5289 
    )
5290 
    port map (
5291 
      C => pclk_i,
5292 
      D => fax4_ins_state_FSM_FFd3_In,
5293 
      Q => fax4_ins_state_FSM_FFd3_1329
5294 
    );
5295 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy_9_Q : MUXCY
5296 
    port map (
5297 
      CI => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(8),
5298 
      DI => fax4_ins_fifo_out1_x(9),
5299 
      S => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(9),
5300 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(9)
5301 
    );
5302 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut_9_Q : LUT2
5303 
    generic map(
5304 
      INIT => X"9"
5305 
    )
5306 
    port map (
5307 
      I0 => fax4_ins_fifo_out1_x(9),
5308 
      I1 => fax4_ins_fifo_rd_addsub0000(9),
5309 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(9)
5310 
    );
5311 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy_8_Q : MUXCY
5312 
    port map (
5313 
      CI => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(7),
5314 
      DI => fax4_ins_fifo_out1_x(8),
5315 
      S => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(8),
5316 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(8)
5317 
    );
5318 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut_8_Q : LUT2
5319 
    generic map(
5320 
      INIT => X"9"
5321 
    )
5322 
    port map (
5323 
      I0 => fax4_ins_fifo_out1_x(8),
5324 
      I1 => fax4_ins_fifo_rd_addsub0000(8),
5325 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(8)
5326 
    );
5327 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy_7_Q : MUXCY
5328 
    port map (
5329 
      CI => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(6),
5330 
      DI => fax4_ins_fifo_out1_x(7),
5331 
      S => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(7),
5332 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(7)
5333 
    );
5334 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut_7_Q : LUT2
5335 
    generic map(
5336 
      INIT => X"9"
5337 
    )
5338 
    port map (
5339 
      I0 => fax4_ins_fifo_out1_x(7),
5340 
      I1 => fax4_ins_fifo_rd_addsub0000(7),
5341 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(7)
5342 
    );
5343 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy_6_Q : MUXCY
5344 
    port map (
5345 
      CI => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(5),
5346 
      DI => fax4_ins_fifo_out1_x(6),
5347 
      S => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(6),
5348 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(6)
5349 
    );
5350 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut_6_Q : LUT2
5351 
    generic map(
5352 
      INIT => X"9"
5353 
    )
5354 
    port map (
5355 
      I0 => fax4_ins_fifo_out1_x(6),
5356 
      I1 => fax4_ins_fifo_rd_addsub0000(6),
5357 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(6)
5358 
    );
5359 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy_5_Q : MUXCY
5360 
    port map (
5361 
      CI => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(4),
5362 
      DI => fax4_ins_fifo_out1_x(5),
5363 
      S => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(5),
5364 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(5)
5365 
    );
5366 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut_5_Q : LUT2
5367 
    generic map(
5368 
      INIT => X"9"
5369 
    )
5370 
    port map (
5371 
      I0 => fax4_ins_fifo_out1_x(5),
5372 
      I1 => fax4_ins_fifo_rd_addsub0000(5),
5373 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(5)
5374 
    );
5375 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy_4_Q : MUXCY
5376 
    port map (
5377 
      CI => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(3),
5378 
      DI => fax4_ins_fifo_out1_x(4),
5379 
      S => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(4),
5380 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(4)
5381 
    );
5382 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut_4_Q : LUT2
5383 
    generic map(
5384 
      INIT => X"9"
5385 
    )
5386 
    port map (
5387 
      I0 => fax4_ins_fifo_out1_x(4),
5388 
      I1 => fax4_ins_fifo_rd_addsub0000(4),
5389 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(4)
5390 
    );
5391 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy_3_Q : MUXCY
5392 
    port map (
5393 
      CI => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(2),
5394 
      DI => fax4_ins_fifo_out1_x(3),
5395 
      S => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(3),
5396 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(3)
5397 
    );
5398 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut_3_Q : LUT2
5399 
    generic map(
5400 
      INIT => X"9"
5401 
    )
5402 
    port map (
5403 
      I0 => fax4_ins_fifo_out1_x(3),
5404 
      I1 => fax4_ins_fifo_rd_addsub0000(3),
5405 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(3)
5406 
    );
5407 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy_2_Q : MUXCY
5408 
    port map (
5409 
      CI => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(1),
5410 
      DI => fax4_ins_fifo_out1_x(2),
5411 
      S => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(2),
5412 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(2)
5413 
    );
5414 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut_2_Q : LUT2
5415 
    generic map(
5416 
      INIT => X"9"
5417 
    )
5418 
    port map (
5419 
      I0 => fax4_ins_fifo_out1_x(2),
5420 
      I1 => fax4_ins_fifo_rd_addsub0000(2),
5421 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(2)
5422 
    );
5423 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy_1_Q : MUXCY
5424 
    port map (
5425 
      CI => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(0),
5426 
      DI => fax4_ins_fifo_out1_x(1),
5427 
      S => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(1),
5428 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(1)
5429 
    );
5430 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut_1_Q : LUT2
5431 
    generic map(
5432 
      INIT => X"9"
5433 
    )
5434 
    port map (
5435 
      I0 => fax4_ins_fifo_out1_x(1),
5436 
      I1 => fax4_ins_fifo_rd_addsub0000(1),
5437 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(1)
5438 
    );
5439 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy_0_Q : MUXCY
5440 
    port map (
5441 
      CI => N1,
5442 
      DI => fax4_ins_fifo_out1_x(0),
5443 
      S => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(0),
5444 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(0)
5445 
    );
5446 
  fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut_0_Q : LUT2
5447 
    generic map(
5448 
      INIT => X"9"
5449 
    )
5450 
    port map (
5451 
      I0 => fax4_ins_fifo_out1_x(0),
5452 
      I1 => fax4_ins_fifo_rd_addsub0000(0),
5453 
      O => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_lut(0)
5454 
    );
5455 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy_9_Q : MUXCY
5456 
    port map (
5457 
      CI => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(8),
5458 
      DI => fax4_ins_b2(9),
5459 
      S => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(9),
5460 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(9)
5461 
    );
5462 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut_9_Q : LUT2
5463 
    generic map(
5464 
      INIT => X"9"
5465 
    )
5466 
    port map (
5467 
      I0 => fax4_ins_b2(9),
5468 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
5469 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(9)
5470 
    );
5471 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy_8_Q : MUXCY
5472 
    port map (
5473 
      CI => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(7),
5474 
      DI => fax4_ins_b2(8),
5475 
      S => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(8),
5476 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(8)
5477 
    );
5478 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut_8_Q : LUT2
5479 
    generic map(
5480 
      INIT => X"9"
5481 
    )
5482 
    port map (
5483 
      I0 => fax4_ins_b2(8),
5484 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
5485 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(8)
5486 
    );
5487 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy_7_Q : MUXCY
5488 
    port map (
5489 
      CI => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(6),
5490 
      DI => fax4_ins_b2(7),
5491 
      S => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(7),
5492 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(7)
5493 
    );
5494 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut_7_Q : LUT2
5495 
    generic map(
5496 
      INIT => X"9"
5497 
    )
5498 
    port map (
5499 
      I0 => fax4_ins_b2(7),
5500 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
5501 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(7)
5502 
    );
5503 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy_6_Q : MUXCY
5504 
    port map (
5505 
      CI => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(5),
5506 
      DI => fax4_ins_b2(6),
5507 
      S => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(6),
5508 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(6)
5509 
    );
5510 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut_6_Q : LUT2
5511 
    generic map(
5512 
      INIT => X"9"
5513 
    )
5514 
    port map (
5515 
      I0 => fax4_ins_b2(6),
5516 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
5517 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(6)
5518 
    );
5519 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy_5_Q : MUXCY
5520 
    port map (
5521 
      CI => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(4),
5522 
      DI => fax4_ins_b2(5),
5523 
      S => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(5),
5524 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(5)
5525 
    );
5526 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut_5_Q : LUT2
5527 
    generic map(
5528 
      INIT => X"9"
5529 
    )
5530 
    port map (
5531 
      I0 => fax4_ins_b2(5),
5532 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
5533 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(5)
5534 
    );
5535 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy_4_Q : MUXCY
5536 
    port map (
5537 
      CI => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(3),
5538 
      DI => fax4_ins_b2(4),
5539 
      S => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(4),
5540 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(4)
5541 
    );
5542 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut_4_Q : LUT2
5543 
    generic map(
5544 
      INIT => X"9"
5545 
    )
5546 
    port map (
5547 
      I0 => fax4_ins_b2(4),
5548 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
5549 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(4)
5550 
    );
5551 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy_3_Q : MUXCY
5552 
    port map (
5553 
      CI => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(2),
5554 
      DI => fax4_ins_b2(3),
5555 
      S => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(3),
5556 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(3)
5557 
    );
5558 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut_3_Q : LUT2
5559 
    generic map(
5560 
      INIT => X"9"
5561 
    )
5562 
    port map (
5563 
      I0 => fax4_ins_b2(3),
5564 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
5565 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(3)
5566 
    );
5567 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy_2_Q : MUXCY
5568 
    port map (
5569 
      CI => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(1),
5570 
      DI => fax4_ins_b2(2),
5571 
      S => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(2),
5572 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(2)
5573 
    );
5574 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut_2_Q : LUT2
5575 
    generic map(
5576 
      INIT => X"9"
5577 
    )
5578 
    port map (
5579 
      I0 => fax4_ins_b2(2),
5580 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
5581 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(2)
5582 
    );
5583 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy_1_Q : MUXCY
5584 
    port map (
5585 
      CI => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(0),
5586 
      DI => fax4_ins_b2(1),
5587 
      S => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(1),
5588 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(1)
5589 
    );
5590 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut_1_Q : LUT2
5591 
    generic map(
5592 
      INIT => X"9"
5593 
    )
5594 
    port map (
5595 
      I0 => fax4_ins_b2(1),
5596 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
5597 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(1)
5598 
    );
5599 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy_0_Q : MUXCY
5600 
    port map (
5601 
      CI => N1,
5602 
      DI => fax4_ins_b2(0),
5603 
      S => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(0),
5604 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(0)
5605 
    );
5606 
  fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut_0_Q : LUT2
5607 
    generic map(
5608 
      INIT => X"9"
5609 
    )
5610 
    port map (
5611 
      I0 => fax4_ins_b2(0),
5612 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
5613 
      O => fax4_ins_Mcompar_pass_mode_cmp_lt0000_lut(0)
5614 
    );
5615 
  fax4_ins_Madd_fifo_rd_addsub0000_xor_9_Q : XORCY
5616 
    port map (
5617 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(8),
5618 
      LI => fax4_ins_Madd_fifo_rd_addsub0000_xor_9_rt_749,
5619 
      O => fax4_ins_fifo_rd_addsub0000(9)
5620 
    );
5621 
  fax4_ins_Madd_fifo_rd_addsub0000_xor_8_Q : XORCY
5622 
    port map (
5623 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(7),
5624 
      LI => fax4_ins_Madd_fifo_rd_addsub0000_cy_8_rt_747,
5625 
      O => fax4_ins_fifo_rd_addsub0000(8)
5626 
    );
5627 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_8_Q : MUXCY
5628 
    port map (
5629 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(7),
5630 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5631 
      S => fax4_ins_Madd_fifo_rd_addsub0000_cy_8_rt_747,
5632 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy(8)
5633 
    );
5634 
  fax4_ins_Madd_fifo_rd_addsub0000_xor_7_Q : XORCY
5635 
    port map (
5636 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(6),
5637 
      LI => fax4_ins_Madd_fifo_rd_addsub0000_cy_7_rt_745,
5638 
      O => fax4_ins_fifo_rd_addsub0000(7)
5639 
    );
5640 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_7_Q : MUXCY
5641 
    port map (
5642 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(6),
5643 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5644 
      S => fax4_ins_Madd_fifo_rd_addsub0000_cy_7_rt_745,
5645 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy(7)
5646 
    );
5647 
  fax4_ins_Madd_fifo_rd_addsub0000_xor_6_Q : XORCY
5648 
    port map (
5649 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(5),
5650 
      LI => fax4_ins_Madd_fifo_rd_addsub0000_cy_6_rt_743,
5651 
      O => fax4_ins_fifo_rd_addsub0000(6)
5652 
    );
5653 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_6_Q : MUXCY
5654 
    port map (
5655 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(5),
5656 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5657 
      S => fax4_ins_Madd_fifo_rd_addsub0000_cy_6_rt_743,
5658 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy(6)
5659 
    );
5660 
  fax4_ins_Madd_fifo_rd_addsub0000_xor_5_Q : XORCY
5661 
    port map (
5662 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(4),
5663 
      LI => fax4_ins_Madd_fifo_rd_addsub0000_cy_5_rt_741,
5664 
      O => fax4_ins_fifo_rd_addsub0000(5)
5665 
    );
5666 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_5_Q : MUXCY
5667 
    port map (
5668 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(4),
5669 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5670 
      S => fax4_ins_Madd_fifo_rd_addsub0000_cy_5_rt_741,
5671 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy(5)
5672 
    );
5673 
  fax4_ins_Madd_fifo_rd_addsub0000_xor_4_Q : XORCY
5674 
    port map (
5675 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(3),
5676 
      LI => fax4_ins_Madd_fifo_rd_addsub0000_cy_4_rt_739,
5677 
      O => fax4_ins_fifo_rd_addsub0000(4)
5678 
    );
5679 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_4_Q : MUXCY
5680 
    port map (
5681 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(3),
5682 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5683 
      S => fax4_ins_Madd_fifo_rd_addsub0000_cy_4_rt_739,
5684 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy(4)
5685 
    );
5686 
  fax4_ins_Madd_fifo_rd_addsub0000_xor_3_Q : XORCY
5687 
    port map (
5688 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(2),
5689 
      LI => fax4_ins_Madd_fifo_rd_addsub0000_cy_3_rt_737,
5690 
      O => fax4_ins_fifo_rd_addsub0000(3)
5691 
    );
5692 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_3_Q : MUXCY
5693 
    port map (
5694 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(2),
5695 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5696 
      S => fax4_ins_Madd_fifo_rd_addsub0000_cy_3_rt_737,
5697 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy(3)
5698 
    );
5699 
  fax4_ins_Madd_fifo_rd_addsub0000_xor_2_Q : XORCY
5700 
    port map (
5701 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(1),
5702 
      LI => fax4_ins_Madd_fifo_rd_addsub0000_cy_2_rt_735,
5703 
      O => fax4_ins_fifo_rd_addsub0000(2)
5704 
    );
5705 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_2_Q : MUXCY
5706 
    port map (
5707 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(1),
5708 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5709 
      S => fax4_ins_Madd_fifo_rd_addsub0000_cy_2_rt_735,
5710 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy(2)
5711 
    );
5712 
  fax4_ins_Madd_fifo_rd_addsub0000_xor_1_Q : XORCY
5713 
    port map (
5714 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(0),
5715 
      LI => fax4_ins_Madd_fifo_rd_addsub0000_cy_1_rt_733,
5716 
      O => fax4_ins_fifo_rd_addsub0000(1)
5717 
    );
5718 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_1_Q : MUXCY
5719 
    port map (
5720 
      CI => fax4_ins_Madd_fifo_rd_addsub0000_cy(0),
5721 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
5722 
      S => fax4_ins_Madd_fifo_rd_addsub0000_cy_1_rt_733,
5723 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy(1)
5724 
    );
5725 
  fax4_ins_Madd_fifo_rd_addsub0000_xor_0_Q : XORCY
5726 
    port map (
5727 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
5728 
      LI => fax4_ins_Madd_fifo_rd_addsub0000_lut(0),
5729 
      O => fax4_ins_fifo_rd_addsub0000(0)
5730 
    );
5731 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_0_Q : MUXCY
5732 
    port map (
5733 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
5734 
      DI => N1,
5735 
      S => fax4_ins_Madd_fifo_rd_addsub0000_lut(0),
5736 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy(0)
5737 
    );
5738 
  fax4_ins_Msub_a1b1_addsub0000_xor_10_Q : XORCY
5739 
    port map (
5740 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(9),
5741 
      LI => N1,
5742 
      O => fax4_ins_a1b1_addsub0000(10)
5743 
    );
5744 
  fax4_ins_Msub_a1b1_addsub0000_xor_9_Q : XORCY
5745 
    port map (
5746 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(8),
5747 
      LI => fax4_ins_Msub_a1b1_addsub0000_lut(9),
5748 
      O => fax4_ins_a1b1_addsub0000(9)
5749 
    );
5750 
  fax4_ins_Msub_a1b1_addsub0000_cy_9_Q : MUXCY
5751 
    port map (
5752 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(8),
5753 
      DI => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
5754 
      S => fax4_ins_Msub_a1b1_addsub0000_lut(9),
5755 
      O => fax4_ins_Msub_a1b1_addsub0000_cy(9)
5756 
    );
5757 
  fax4_ins_Msub_a1b1_addsub0000_lut_9_Q : LUT2
5758 
    generic map(
5759 
      INIT => X"9"
5760 
    )
5761 
    port map (
5762 
      I0 => fax4_ins_b1(9),
5763 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
5764 
      O => fax4_ins_Msub_a1b1_addsub0000_lut(9)
5765 
    );
5766 
  fax4_ins_Msub_a1b1_addsub0000_xor_8_Q : XORCY
5767 
    port map (
5768 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(7),
5769 
      LI => fax4_ins_Msub_a1b1_addsub0000_lut(8),
5770 
      O => fax4_ins_a1b1_addsub0000(8)
5771 
    );
5772 
  fax4_ins_Msub_a1b1_addsub0000_cy_8_Q : MUXCY
5773 
    port map (
5774 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(7),
5775 
      DI => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
5776 
      S => fax4_ins_Msub_a1b1_addsub0000_lut(8),
5777 
      O => fax4_ins_Msub_a1b1_addsub0000_cy(8)
5778 
    );
5779 
  fax4_ins_Msub_a1b1_addsub0000_lut_8_Q : LUT2
5780 
    generic map(
5781 
      INIT => X"9"
5782 
    )
5783 
    port map (
5784 
      I0 => fax4_ins_b1(8),
5785 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
5786 
      O => fax4_ins_Msub_a1b1_addsub0000_lut(8)
5787 
    );
5788 
  fax4_ins_Msub_a1b1_addsub0000_xor_7_Q : XORCY
5789 
    port map (
5790 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(6),
5791 
      LI => fax4_ins_Msub_a1b1_addsub0000_lut(7),
5792 
      O => fax4_ins_a1b1_addsub0000(7)
5793 
    );
5794 
  fax4_ins_Msub_a1b1_addsub0000_cy_7_Q : MUXCY
5795 
    port map (
5796 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(6),
5797 
      DI => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
5798 
      S => fax4_ins_Msub_a1b1_addsub0000_lut(7),
5799 
      O => fax4_ins_Msub_a1b1_addsub0000_cy(7)
5800 
    );
5801 
  fax4_ins_Msub_a1b1_addsub0000_lut_7_Q : LUT2
5802 
    generic map(
5803 
      INIT => X"9"
5804 
    )
5805 
    port map (
5806 
      I0 => fax4_ins_b1(7),
5807 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
5808 
      O => fax4_ins_Msub_a1b1_addsub0000_lut(7)
5809 
    );
5810 
  fax4_ins_Msub_a1b1_addsub0000_xor_6_Q : XORCY
5811 
    port map (
5812 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(5),
5813 
      LI => fax4_ins_Msub_a1b1_addsub0000_lut(6),
5814 
      O => fax4_ins_a1b1_addsub0000(6)
5815 
    );
5816 
  fax4_ins_Msub_a1b1_addsub0000_cy_6_Q : MUXCY
5817 
    port map (
5818 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(5),
5819 
      DI => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
5820 
      S => fax4_ins_Msub_a1b1_addsub0000_lut(6),
5821 
      O => fax4_ins_Msub_a1b1_addsub0000_cy(6)
5822 
    );
5823 
  fax4_ins_Msub_a1b1_addsub0000_lut_6_Q : LUT2
5824 
    generic map(
5825 
      INIT => X"9"
5826 
    )
5827 
    port map (
5828 
      I0 => fax4_ins_b1(6),
5829 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
5830 
      O => fax4_ins_Msub_a1b1_addsub0000_lut(6)
5831 
    );
5832 
  fax4_ins_Msub_a1b1_addsub0000_xor_5_Q : XORCY
5833 
    port map (
5834 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(4),
5835 
      LI => fax4_ins_Msub_a1b1_addsub0000_lut(5),
5836 
      O => fax4_ins_a1b1_addsub0000(5)
5837 
    );
5838 
  fax4_ins_Msub_a1b1_addsub0000_cy_5_Q : MUXCY
5839 
    port map (
5840 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(4),
5841 
      DI => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
5842 
      S => fax4_ins_Msub_a1b1_addsub0000_lut(5),
5843 
      O => fax4_ins_Msub_a1b1_addsub0000_cy(5)
5844 
    );
5845 
  fax4_ins_Msub_a1b1_addsub0000_lut_5_Q : LUT2
5846 
    generic map(
5847 
      INIT => X"9"
5848 
    )
5849 
    port map (
5850 
      I0 => fax4_ins_b1(5),
5851 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
5852 
      O => fax4_ins_Msub_a1b1_addsub0000_lut(5)
5853 
    );
5854 
  fax4_ins_Msub_a1b1_addsub0000_xor_4_Q : XORCY
5855 
    port map (
5856 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(3),
5857 
      LI => fax4_ins_Msub_a1b1_addsub0000_lut(4),
5858 
      O => fax4_ins_a1b1_addsub0000(4)
5859 
    );
5860 
  fax4_ins_Msub_a1b1_addsub0000_cy_4_Q : MUXCY
5861 
    port map (
5862 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(3),
5863 
      DI => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
5864 
      S => fax4_ins_Msub_a1b1_addsub0000_lut(4),
5865 
      O => fax4_ins_Msub_a1b1_addsub0000_cy(4)
5866 
    );
5867 
  fax4_ins_Msub_a1b1_addsub0000_lut_4_Q : LUT2
5868 
    generic map(
5869 
      INIT => X"9"
5870 
    )
5871 
    port map (
5872 
      I0 => fax4_ins_b1(4),
5873 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
5874 
      O => fax4_ins_Msub_a1b1_addsub0000_lut(4)
5875 
    );
5876 
  fax4_ins_Msub_a1b1_addsub0000_xor_3_Q : XORCY
5877 
    port map (
5878 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(2),
5879 
      LI => fax4_ins_Msub_a1b1_addsub0000_lut(3),
5880 
      O => fax4_ins_a1b1_addsub0000(3)
5881 
    );
5882 
  fax4_ins_Msub_a1b1_addsub0000_cy_3_Q : MUXCY
5883 
    port map (
5884 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(2),
5885 
      DI => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
5886 
      S => fax4_ins_Msub_a1b1_addsub0000_lut(3),
5887 
      O => fax4_ins_Msub_a1b1_addsub0000_cy(3)
5888 
    );
5889 
  fax4_ins_Msub_a1b1_addsub0000_lut_3_Q : LUT2
5890 
    generic map(
5891 
      INIT => X"9"
5892 
    )
5893 
    port map (
5894 
      I0 => fax4_ins_b1(3),
5895 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
5896 
      O => fax4_ins_Msub_a1b1_addsub0000_lut(3)
5897 
    );
5898 
  fax4_ins_Msub_a1b1_addsub0000_xor_2_Q : XORCY
5899 
    port map (
5900 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(1),
5901 
      LI => fax4_ins_Msub_a1b1_addsub0000_lut(2),
5902 
      O => fax4_ins_a1b1_addsub0000(2)
5903 
    );
5904 
  fax4_ins_Msub_a1b1_addsub0000_cy_2_Q : MUXCY
5905 
    port map (
5906 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(1),
5907 
      DI => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
5908 
      S => fax4_ins_Msub_a1b1_addsub0000_lut(2),
5909 
      O => fax4_ins_Msub_a1b1_addsub0000_cy(2)
5910 
    );
5911 
  fax4_ins_Msub_a1b1_addsub0000_lut_2_Q : LUT2
5912 
    generic map(
5913 
      INIT => X"9"
5914 
    )
5915 
    port map (
5916 
      I0 => fax4_ins_b1(2),
5917 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
5918 
      O => fax4_ins_Msub_a1b1_addsub0000_lut(2)
5919 
    );
5920 
  fax4_ins_Msub_a1b1_addsub0000_xor_1_Q : XORCY
5921 
    port map (
5922 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(0),
5923 
      LI => fax4_ins_Msub_a1b1_addsub0000_lut(1),
5924 
      O => fax4_ins_a1b1_addsub0000(1)
5925 
    );
5926 
  fax4_ins_Msub_a1b1_addsub0000_cy_1_Q : MUXCY
5927 
    port map (
5928 
      CI => fax4_ins_Msub_a1b1_addsub0000_cy(0),
5929 
      DI => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
5930 
      S => fax4_ins_Msub_a1b1_addsub0000_lut(1),
5931 
      O => fax4_ins_Msub_a1b1_addsub0000_cy(1)
5932 
    );
5933 
  fax4_ins_Msub_a1b1_addsub0000_lut_1_Q : LUT2
5934 
    generic map(
5935 
      INIT => X"9"
5936 
    )
5937 
    port map (
5938 
      I0 => fax4_ins_b1(1),
5939 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
5940 
      O => fax4_ins_Msub_a1b1_addsub0000_lut(1)
5941 
    );
5942 
  fax4_ins_Msub_a1b1_addsub0000_xor_0_Q : XORCY
5943 
    port map (
5944 
      CI => N1,
5945 
      LI => fax4_ins_Msub_a1b1_addsub0000_lut(0),
5946 
      O => fax4_ins_a1b1_addsub0000(0)
5947 
    );
5948 
  fax4_ins_Msub_a1b1_addsub0000_cy_0_Q : MUXCY
5949 
    port map (
5950 
      CI => N1,
5951 
      DI => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
5952 
      S => fax4_ins_Msub_a1b1_addsub0000_lut(0),
5953 
      O => fax4_ins_Msub_a1b1_addsub0000_cy(0)
5954 
    );
5955 
  fax4_ins_Msub_a1b1_addsub0000_lut_0_Q : LUT2
5956 
    generic map(
5957 
      INIT => X"9"
5958 
    )
5959 
    port map (
5960 
      I0 => fax4_ins_b1(0),
5961 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
5962 
      O => fax4_ins_Msub_a1b1_addsub0000_lut(0)
5963 
    );
5964 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy_9_Q : MUXCY
5965 
    port map (
5966 
      CI => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(8),
5967 
      DI => fax4_ins_a0(9),
5968 
      S => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(9),
5969 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(9)
5970 
    );
5971 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy_8_Q : MUXCY
5972 
    port map (
5973 
      CI => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(7),
5974 
      DI => fax4_ins_a0(8),
5975 
      S => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(8),
5976 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(8)
5977 
    );
5978 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy_7_Q : MUXCY
5979 
    port map (
5980 
      CI => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(6),
5981 
      DI => fax4_ins_a0(7),
5982 
      S => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(7),
5983 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(7)
5984 
    );
5985 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy_6_Q : MUXCY
5986 
    port map (
5987 
      CI => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(5),
5988 
      DI => fax4_ins_a0(6),
5989 
      S => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(6),
5990 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(6)
5991 
    );
5992 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy_5_Q : MUXCY
5993 
    port map (
5994 
      CI => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(4),
5995 
      DI => fax4_ins_a0(5),
5996 
      S => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(5),
5997 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(5)
5998 
    );
5999 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy_4_Q : MUXCY
6000 
    port map (
6001 
      CI => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(3),
6002 
      DI => fax4_ins_a0(4),
6003 
      S => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(4),
6004 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(4)
6005 
    );
6006 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy_3_Q : MUXCY
6007 
    port map (
6008 
      CI => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(2),
6009 
      DI => fax4_ins_a0(3),
6010 
      S => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(3),
6011 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(3)
6012 
    );
6013 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy_2_Q : MUXCY
6014 
    port map (
6015 
      CI => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(1),
6016 
      DI => fax4_ins_a0(2),
6017 
      S => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(2),
6018 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(2)
6019 
    );
6020 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy_1_Q : MUXCY
6021 
    port map (
6022 
      CI => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(0),
6023 
      DI => fax4_ins_a0(1),
6024 
      S => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(1),
6025 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(1)
6026 
    );
6027 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy_0_Q : MUXCY
6028 
    port map (
6029 
      CI => N1,
6030 
      DI => fax4_ins_a0(0),
6031 
      S => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(0),
6032 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(0)
6033 
    );
6034 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy_9_Q : MUXCY
6035 
    port map (
6036 
      CI => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(8),
6037 
      DI => fax4_ins_a0(9),
6038 
      S => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(9),
6039 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(9)
6040 
    );
6041 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy_8_Q : MUXCY
6042 
    port map (
6043 
      CI => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(7),
6044 
      DI => fax4_ins_a0(8),
6045 
      S => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(8),
6046 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(8)
6047 
    );
6048 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy_7_Q : MUXCY
6049 
    port map (
6050 
      CI => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(6),
6051 
      DI => fax4_ins_a0(7),
6052 
      S => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(7),
6053 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(7)
6054 
    );
6055 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy_6_Q : MUXCY
6056 
    port map (
6057 
      CI => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(5),
6058 
      DI => fax4_ins_a0(6),
6059 
      S => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(6),
6060 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(6)
6061 
    );
6062 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy_5_Q : MUXCY
6063 
    port map (
6064 
      CI => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(4),
6065 
      DI => fax4_ins_a0(5),
6066 
      S => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(5),
6067 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(5)
6068 
    );
6069 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy_4_Q : MUXCY
6070 
    port map (
6071 
      CI => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(3),
6072 
      DI => fax4_ins_a0(4),
6073 
      S => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(4),
6074 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(4)
6075 
    );
6076 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy_3_Q : MUXCY
6077 
    port map (
6078 
      CI => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(2),
6079 
      DI => fax4_ins_a0(3),
6080 
      S => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(3),
6081 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(3)
6082 
    );
6083 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy_2_Q : MUXCY
6084 
    port map (
6085 
      CI => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(1),
6086 
      DI => fax4_ins_a0(2),
6087 
      S => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(2),
6088 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(2)
6089 
    );
6090 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy_1_Q : MUXCY
6091 
    port map (
6092 
      CI => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(0),
6093 
      DI => fax4_ins_a0(1),
6094 
      S => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(1),
6095 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(1)
6096 
    );
6097 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy_0_Q : MUXCY
6098 
    port map (
6099 
      CI => N1,
6100 
      DI => fax4_ins_a0(0),
6101 
      S => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(0),
6102 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(0)
6103 
    );
6104 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut_0_Q : LUT2
6105 
    generic map(
6106 
      INIT => X"9"
6107 
    )
6108 
    port map (
6109 
      I0 => fax4_ins_a0(0),
6110 
      I1 => fax4_ins_fifo_out1_x(0),
6111 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(0)
6112 
    );
6113 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy_9_Q : MUXCY
6114 
    port map (
6115 
      CI => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(8),
6116 
      DI => fax4_ins_a0(9),
6117 
      S => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(9),
6118 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(9)
6119 
    );
6120 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut_9_Q : LUT2
6121 
    generic map(
6122 
      INIT => X"9"
6123 
    )
6124 
    port map (
6125 
      I0 => fax4_ins_fifo_out_prev1_x(9),
6126 
      I1 => fax4_ins_a0(9),
6127 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(9)
6128 
    );
6129 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy_8_Q : MUXCY
6130 
    port map (
6131 
      CI => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(7),
6132 
      DI => fax4_ins_a0(8),
6133 
      S => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(8),
6134 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(8)
6135 
    );
6136 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut_8_Q : LUT2
6137 
    generic map(
6138 
      INIT => X"9"
6139 
    )
6140 
    port map (
6141 
      I0 => fax4_ins_fifo_out_prev1_x(8),
6142 
      I1 => fax4_ins_a0(8),
6143 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(8)
6144 
    );
6145 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy_7_Q : MUXCY
6146 
    port map (
6147 
      CI => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(6),
6148 
      DI => fax4_ins_a0(7),
6149 
      S => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(7),
6150 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(7)
6151 
    );
6152 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut_7_Q : LUT2
6153 
    generic map(
6154 
      INIT => X"9"
6155 
    )
6156 
    port map (
6157 
      I0 => fax4_ins_fifo_out_prev1_x(7),
6158 
      I1 => fax4_ins_a0(7),
6159 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(7)
6160 
    );
6161 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy_6_Q : MUXCY
6162 
    port map (
6163 
      CI => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(5),
6164 
      DI => fax4_ins_a0(6),
6165 
      S => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(6),
6166 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(6)
6167 
    );
6168 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut_6_Q : LUT2
6169 
    generic map(
6170 
      INIT => X"9"
6171 
    )
6172 
    port map (
6173 
      I0 => fax4_ins_fifo_out_prev1_x(6),
6174 
      I1 => fax4_ins_a0(6),
6175 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(6)
6176 
    );
6177 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy_5_Q : MUXCY
6178 
    port map (
6179 
      CI => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(4),
6180 
      DI => fax4_ins_a0(5),
6181 
      S => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(5),
6182 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(5)
6183 
    );
6184 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut_5_Q : LUT2
6185 
    generic map(
6186 
      INIT => X"9"
6187 
    )
6188 
    port map (
6189 
      I0 => fax4_ins_fifo_out_prev1_x(5),
6190 
      I1 => fax4_ins_a0(5),
6191 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(5)
6192 
    );
6193 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy_4_Q : MUXCY
6194 
    port map (
6195 
      CI => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(3),
6196 
      DI => fax4_ins_a0(4),
6197 
      S => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(4),
6198 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(4)
6199 
    );
6200 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut_4_Q : LUT2
6201 
    generic map(
6202 
      INIT => X"9"
6203 
    )
6204 
    port map (
6205 
      I0 => fax4_ins_fifo_out_prev1_x(4),
6206 
      I1 => fax4_ins_a0(4),
6207 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(4)
6208 
    );
6209 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy_3_Q : MUXCY
6210 
    port map (
6211 
      CI => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(2),
6212 
      DI => fax4_ins_a0(3),
6213 
      S => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(3),
6214 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(3)
6215 
    );
6216 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut_3_Q : LUT2
6217 
    generic map(
6218 
      INIT => X"9"
6219 
    )
6220 
    port map (
6221 
      I0 => fax4_ins_fifo_out_prev1_x(3),
6222 
      I1 => fax4_ins_a0(3),
6223 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(3)
6224 
    );
6225 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy_2_Q : MUXCY
6226 
    port map (
6227 
      CI => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(1),
6228 
      DI => fax4_ins_a0(2),
6229 
      S => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(2),
6230 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(2)
6231 
    );
6232 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut_2_Q : LUT2
6233 
    generic map(
6234 
      INIT => X"9"
6235 
    )
6236 
    port map (
6237 
      I0 => fax4_ins_fifo_out_prev1_x(2),
6238 
      I1 => fax4_ins_a0(2),
6239 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(2)
6240 
    );
6241 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy_1_Q : MUXCY
6242 
    port map (
6243 
      CI => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(0),
6244 
      DI => fax4_ins_a0(1),
6245 
      S => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(1),
6246 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(1)
6247 
    );
6248 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut_1_Q : LUT2
6249 
    generic map(
6250 
      INIT => X"9"
6251 
    )
6252 
    port map (
6253 
      I0 => fax4_ins_fifo_out_prev1_x(1),
6254 
      I1 => fax4_ins_a0(1),
6255 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(1)
6256 
    );
6257 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy_0_Q : MUXCY
6258 
    port map (
6259 
      CI => N1,
6260 
      DI => fax4_ins_a0(0),
6261 
      S => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(0),
6262 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(0)
6263 
    );
6264 
  fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut_0_Q : LUT2
6265 
    generic map(
6266 
      INIT => X"9"
6267 
    )
6268 
    port map (
6269 
      I0 => fax4_ins_fifo_out_prev1_x(0),
6270 
      I1 => fax4_ins_a0(0),
6271 
      O => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_lut(0)
6272 
    );
6273 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy_9_Q : MUXCY
6274 
    port map (
6275 
      CI => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(8),
6276 
      DI => fax4_ins_a0(9),
6277 
      S => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(9),
6278 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(9)
6279 
    );
6280 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut_9_Q : LUT2
6281 
    generic map(
6282 
      INIT => X"9"
6283 
    )
6284 
    port map (
6285 
      I0 => fax4_ins_fifo_out_prev2_x(9),
6286 
      I1 => fax4_ins_a0(9),
6287 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(9)
6288 
    );
6289 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy_8_Q : MUXCY
6290 
    port map (
6291 
      CI => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(7),
6292 
      DI => fax4_ins_a0(8),
6293 
      S => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(8),
6294 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(8)
6295 
    );
6296 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut_8_Q : LUT2
6297 
    generic map(
6298 
      INIT => X"9"
6299 
    )
6300 
    port map (
6301 
      I0 => fax4_ins_fifo_out_prev2_x(8),
6302 
      I1 => fax4_ins_a0(8),
6303 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(8)
6304 
    );
6305 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy_7_Q : MUXCY
6306 
    port map (
6307 
      CI => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(6),
6308 
      DI => fax4_ins_a0(7),
6309 
      S => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(7),
6310 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(7)
6311 
    );
6312 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut_7_Q : LUT2
6313 
    generic map(
6314 
      INIT => X"9"
6315 
    )
6316 
    port map (
6317 
      I0 => fax4_ins_fifo_out_prev2_x(7),
6318 
      I1 => fax4_ins_a0(7),
6319 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(7)
6320 
    );
6321 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy_6_Q : MUXCY
6322 
    port map (
6323 
      CI => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(5),
6324 
      DI => fax4_ins_a0(6),
6325 
      S => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(6),
6326 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(6)
6327 
    );
6328 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut_6_Q : LUT2
6329 
    generic map(
6330 
      INIT => X"9"
6331 
    )
6332 
    port map (
6333 
      I0 => fax4_ins_fifo_out_prev2_x(6),
6334 
      I1 => fax4_ins_a0(6),
6335 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(6)
6336 
    );
6337 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy_5_Q : MUXCY
6338 
    port map (
6339 
      CI => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(4),
6340 
      DI => fax4_ins_a0(5),
6341 
      S => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(5),
6342 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(5)
6343 
    );
6344 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut_5_Q : LUT2
6345 
    generic map(
6346 
      INIT => X"9"
6347 
    )
6348 
    port map (
6349 
      I0 => fax4_ins_fifo_out_prev2_x(5),
6350 
      I1 => fax4_ins_a0(5),
6351 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(5)
6352 
    );
6353 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy_4_Q : MUXCY
6354 
    port map (
6355 
      CI => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(3),
6356 
      DI => fax4_ins_a0(4),
6357 
      S => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(4),
6358 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(4)
6359 
    );
6360 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut_4_Q : LUT2
6361 
    generic map(
6362 
      INIT => X"9"
6363 
    )
6364 
    port map (
6365 
      I0 => fax4_ins_fifo_out_prev2_x(4),
6366 
      I1 => fax4_ins_a0(4),
6367 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(4)
6368 
    );
6369 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy_3_Q : MUXCY
6370 
    port map (
6371 
      CI => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(2),
6372 
      DI => fax4_ins_a0(3),
6373 
      S => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(3),
6374 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(3)
6375 
    );
6376 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut_3_Q : LUT2
6377 
    generic map(
6378 
      INIT => X"9"
6379 
    )
6380 
    port map (
6381 
      I0 => fax4_ins_fifo_out_prev2_x(3),
6382 
      I1 => fax4_ins_a0(3),
6383 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(3)
6384 
    );
6385 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy_2_Q : MUXCY
6386 
    port map (
6387 
      CI => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(1),
6388 
      DI => fax4_ins_a0(2),
6389 
      S => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(2),
6390 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(2)
6391 
    );
6392 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut_2_Q : LUT2
6393 
    generic map(
6394 
      INIT => X"9"
6395 
    )
6396 
    port map (
6397 
      I0 => fax4_ins_fifo_out_prev2_x(2),
6398 
      I1 => fax4_ins_a0(2),
6399 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(2)
6400 
    );
6401 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy_1_Q : MUXCY
6402 
    port map (
6403 
      CI => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(0),
6404 
      DI => fax4_ins_a0(1),
6405 
      S => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(1),
6406 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(1)
6407 
    );
6408 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut_1_Q : LUT2
6409 
    generic map(
6410 
      INIT => X"9"
6411 
    )
6412 
    port map (
6413 
      I0 => fax4_ins_fifo_out_prev2_x(1),
6414 
      I1 => fax4_ins_a0(1),
6415 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(1)
6416 
    );
6417 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy_0_Q : MUXCY
6418 
    port map (
6419 
      CI => N1,
6420 
      DI => fax4_ins_a0(0),
6421 
      S => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(0),
6422 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(0)
6423 
    );
6424 
  fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut_0_Q : LUT2
6425 
    generic map(
6426 
      INIT => X"9"
6427 
    )
6428 
    port map (
6429 
      I0 => fax4_ins_fifo_out_prev2_x(0),
6430 
      I1 => fax4_ins_a0(0),
6431 
      O => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_lut(0)
6432 
    );
6433 
  fax4_ins_Madd_a1b1_addsub0001_xor_10_Q : XORCY
6434 
    port map (
6435 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(9),
6436 
      LI => N1,
6437 
      O => fax4_ins_a1b1_addsub0001(10)
6438 
    );
6439 
  fax4_ins_Madd_a1b1_addsub0001_xor_9_Q : XORCY
6440 
    port map (
6441 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(8),
6442 
      LI => fax4_ins_Madd_a1b1_addsub0001_cy_9_rt_730,
6443 
      O => fax4_ins_a1b1_addsub0001(9)
6444 
    );
6445 
  fax4_ins_Madd_a1b1_addsub0001_cy_9_Q : MUXCY
6446 
    port map (
6447 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(8),
6448 
      DI => N1,
6449 
      S => fax4_ins_Madd_a1b1_addsub0001_cy_9_rt_730,
6450 
      O => fax4_ins_Madd_a1b1_addsub0001_cy(9)
6451 
    );
6452 
  fax4_ins_Madd_a1b1_addsub0001_xor_8_Q : XORCY
6453 
    port map (
6454 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(7),
6455 
      LI => fax4_ins_a1b1_not0000_8_Q,
6456 
      O => fax4_ins_a1b1_addsub0001(8)
6457 
    );
6458 
  fax4_ins_Madd_a1b1_addsub0001_cy_8_Q : MUXCY
6459 
    port map (
6460 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(7),
6461 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6462 
      S => fax4_ins_a1b1_not0000_8_Q,
6463 
      O => fax4_ins_Madd_a1b1_addsub0001_cy(8)
6464 
    );
6465 
  fax4_ins_Madd_a1b1_addsub0001_xor_7_Q : XORCY
6466 
    port map (
6467 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(6),
6468 
      LI => fax4_ins_Madd_a1b1_addsub0001_cy_7_rt_727,
6469 
      O => fax4_ins_a1b1_addsub0001(7)
6470 
    );
6471 
  fax4_ins_Madd_a1b1_addsub0001_cy_7_Q : MUXCY
6472 
    port map (
6473 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(6),
6474 
      DI => N1,
6475 
      S => fax4_ins_Madd_a1b1_addsub0001_cy_7_rt_727,
6476 
      O => fax4_ins_Madd_a1b1_addsub0001_cy(7)
6477 
    );
6478 
  fax4_ins_Madd_a1b1_addsub0001_xor_6_Q : XORCY
6479 
    port map (
6480 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(5),
6481 
      LI => fax4_ins_Madd_a1b1_addsub0001_cy_6_rt_725,
6482 
      O => fax4_ins_a1b1_addsub0001(6)
6483 
    );
6484 
  fax4_ins_Madd_a1b1_addsub0001_cy_6_Q : MUXCY
6485 
    port map (
6486 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(5),
6487 
      DI => N1,
6488 
      S => fax4_ins_Madd_a1b1_addsub0001_cy_6_rt_725,
6489 
      O => fax4_ins_Madd_a1b1_addsub0001_cy(6)
6490 
    );
6491 
  fax4_ins_Madd_a1b1_addsub0001_xor_5_Q : XORCY
6492 
    port map (
6493 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(4),
6494 
      LI => fax4_ins_Madd_a1b1_addsub0001_cy_5_rt_723,
6495 
      O => fax4_ins_a1b1_addsub0001(5)
6496 
    );
6497 
  fax4_ins_Madd_a1b1_addsub0001_cy_5_Q : MUXCY
6498 
    port map (
6499 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(4),
6500 
      DI => N1,
6501 
      S => fax4_ins_Madd_a1b1_addsub0001_cy_5_rt_723,
6502 
      O => fax4_ins_Madd_a1b1_addsub0001_cy(5)
6503 
    );
6504 
  fax4_ins_Madd_a1b1_addsub0001_xor_4_Q : XORCY
6505 
    port map (
6506 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(3),
6507 
      LI => fax4_ins_Madd_a1b1_addsub0001_cy_4_rt_721,
6508 
      O => fax4_ins_a1b1_addsub0001(4)
6509 
    );
6510 
  fax4_ins_Madd_a1b1_addsub0001_cy_4_Q : MUXCY
6511 
    port map (
6512 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(3),
6513 
      DI => N1,
6514 
      S => fax4_ins_Madd_a1b1_addsub0001_cy_4_rt_721,
6515 
      O => fax4_ins_Madd_a1b1_addsub0001_cy(4)
6516 
    );
6517 
  fax4_ins_Madd_a1b1_addsub0001_xor_3_Q : XORCY
6518 
    port map (
6519 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(2),
6520 
      LI => fax4_ins_a1b1_not0000_3_Q,
6521 
      O => fax4_ins_a1b1_addsub0001(3)
6522 
    );
6523 
  fax4_ins_Madd_a1b1_addsub0001_cy_3_Q : MUXCY
6524 
    port map (
6525 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(2),
6526 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6527 
      S => fax4_ins_a1b1_not0000_3_Q,
6528 
      O => fax4_ins_Madd_a1b1_addsub0001_cy(3)
6529 
    );
6530 
  fax4_ins_Madd_a1b1_addsub0001_xor_2_Q : XORCY
6531 
    port map (
6532 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(1),
6533 
      LI => fax4_ins_a1b1_not0000_2_Q,
6534 
      O => fax4_ins_a1b1_addsub0001(2)
6535 
    );
6536 
  fax4_ins_Madd_a1b1_addsub0001_cy_2_Q : MUXCY
6537 
    port map (
6538 
      CI => fax4_ins_Madd_a1b1_addsub0001_cy(1),
6539 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6540 
      S => fax4_ins_a1b1_not0000_2_Q,
6541 
      O => fax4_ins_Madd_a1b1_addsub0001_cy(2)
6542 
    );
6543 
  fax4_ins_Madd_a1b1_addsub0001_xor_1_Q : XORCY
6544 
    port map (
6545 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
6546 
      LI => fax4_ins_Madd_a1b1_addsub0001_cy_1_rt_717,
6547 
      O => fax4_ins_a1b1_addsub0001(1)
6548 
    );
6549 
  fax4_ins_Madd_a1b1_addsub0001_cy_1_Q : MUXCY
6550 
    port map (
6551 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
6552 
      DI => N1,
6553 
      S => fax4_ins_Madd_a1b1_addsub0001_cy_1_rt_717,
6554 
      O => fax4_ins_Madd_a1b1_addsub0001_cy(1)
6555 
    );
6556 
  fax4_ins_Madd_vertical_mode_addsub0000_xor_10_Q : XORCY
6557 
    port map (
6558 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(9),
6559 
      LI => fax4_ins_Madd_vertical_mode_not0000(10),
6560 
      O => fax4_ins_vertical_mode_addsub0000(10)
6561 
    );
6562 
  fax4_ins_Madd_vertical_mode_addsub0000_xor_9_Q : XORCY
6563 
    port map (
6564 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(8),
6565 
      LI => fax4_ins_Madd_vertical_mode_not0000(9),
6566 
      O => fax4_ins_vertical_mode_addsub0000(9)
6567 
    );
6568 
  fax4_ins_Madd_vertical_mode_addsub0000_cy_9_Q : MUXCY
6569 
    port map (
6570 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(8),
6571 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6572 
      S => fax4_ins_Madd_vertical_mode_not0000(9),
6573 
      O => fax4_ins_Madd_vertical_mode_addsub0000_cy(9)
6574 
    );
6575 
  fax4_ins_Madd_vertical_mode_addsub0000_xor_8_Q : XORCY
6576 
    port map (
6577 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(7),
6578 
      LI => fax4_ins_Madd_vertical_mode_not0000(8),
6579 
      O => fax4_ins_vertical_mode_addsub0000(8)
6580 
    );
6581 
  fax4_ins_Madd_vertical_mode_addsub0000_cy_8_Q : MUXCY
6582 
    port map (
6583 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(7),
6584 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6585 
      S => fax4_ins_Madd_vertical_mode_not0000(8),
6586 
      O => fax4_ins_Madd_vertical_mode_addsub0000_cy(8)
6587 
    );
6588 
  fax4_ins_Madd_vertical_mode_addsub0000_xor_7_Q : XORCY
6589 
    port map (
6590 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(6),
6591 
      LI => fax4_ins_Madd_vertical_mode_not0000(7),
6592 
      O => fax4_ins_vertical_mode_addsub0000(7)
6593 
    );
6594 
  fax4_ins_Madd_vertical_mode_addsub0000_cy_7_Q : MUXCY
6595 
    port map (
6596 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(6),
6597 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6598 
      S => fax4_ins_Madd_vertical_mode_not0000(7),
6599 
      O => fax4_ins_Madd_vertical_mode_addsub0000_cy(7)
6600 
    );
6601 
  fax4_ins_Madd_vertical_mode_addsub0000_xor_6_Q : XORCY
6602 
    port map (
6603 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(5),
6604 
      LI => fax4_ins_Madd_vertical_mode_not0000(6),
6605 
      O => fax4_ins_vertical_mode_addsub0000(6)
6606 
    );
6607 
  fax4_ins_Madd_vertical_mode_addsub0000_cy_6_Q : MUXCY
6608 
    port map (
6609 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(5),
6610 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6611 
      S => fax4_ins_Madd_vertical_mode_not0000(6),
6612 
      O => fax4_ins_Madd_vertical_mode_addsub0000_cy(6)
6613 
    );
6614 
  fax4_ins_Madd_vertical_mode_addsub0000_xor_5_Q : XORCY
6615 
    port map (
6616 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(4),
6617 
      LI => fax4_ins_Madd_vertical_mode_not0000(5),
6618 
      O => fax4_ins_vertical_mode_addsub0000(5)
6619 
    );
6620 
  fax4_ins_Madd_vertical_mode_addsub0000_cy_5_Q : MUXCY
6621 
    port map (
6622 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(4),
6623 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6624 
      S => fax4_ins_Madd_vertical_mode_not0000(5),
6625 
      O => fax4_ins_Madd_vertical_mode_addsub0000_cy(5)
6626 
    );
6627 
  fax4_ins_Madd_vertical_mode_addsub0000_xor_4_Q : XORCY
6628 
    port map (
6629 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(3),
6630 
      LI => fax4_ins_Madd_vertical_mode_not0000(4),
6631 
      O => fax4_ins_vertical_mode_addsub0000(4)
6632 
    );
6633 
  fax4_ins_Madd_vertical_mode_addsub0000_cy_4_Q : MUXCY
6634 
    port map (
6635 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(3),
6636 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6637 
      S => fax4_ins_Madd_vertical_mode_not0000(4),
6638 
      O => fax4_ins_Madd_vertical_mode_addsub0000_cy(4)
6639 
    );
6640 
  fax4_ins_Madd_vertical_mode_addsub0000_xor_3_Q : XORCY
6641 
    port map (
6642 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(2),
6643 
      LI => fax4_ins_Madd_vertical_mode_not0000(3),
6644 
      O => fax4_ins_vertical_mode_addsub0000(3)
6645 
    );
6646 
  fax4_ins_Madd_vertical_mode_addsub0000_cy_3_Q : MUXCY
6647 
    port map (
6648 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(2),
6649 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6650 
      S => fax4_ins_Madd_vertical_mode_not0000(3),
6651 
      O => fax4_ins_Madd_vertical_mode_addsub0000_cy(3)
6652 
    );
6653 
  fax4_ins_Madd_vertical_mode_addsub0000_xor_2_Q : XORCY
6654 
    port map (
6655 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(1),
6656 
      LI => fax4_ins_Madd_vertical_mode_not0000(2),
6657 
      O => fax4_ins_vertical_mode_addsub0000(2)
6658 
    );
6659 
  fax4_ins_Madd_vertical_mode_addsub0000_cy_2_Q : MUXCY
6660 
    port map (
6661 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(1),
6662 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6663 
      S => fax4_ins_Madd_vertical_mode_not0000(2),
6664 
      O => fax4_ins_Madd_vertical_mode_addsub0000_cy(2)
6665 
    );
6666 
  fax4_ins_Madd_vertical_mode_addsub0000_cy_1_Q : MUXCY
6667 
    port map (
6668 
      CI => fax4_ins_Madd_vertical_mode_addsub0000_cy(0),
6669 
      DI => NlwRenamedSig_OI_run_len_code_o(26),
6670 
      S => fax4_ins_Madd_vertical_mode_not0000(1),
6671 
      O => fax4_ins_Madd_vertical_mode_addsub0000_cy(1)
6672 
    );
6673 
  fax4_ins_Madd_vertical_mode_addsub0000_cy_0_Q : MUXCY
6674 
    port map (
6675 
      CI => NlwRenamedSig_OI_run_len_code_o(26),
6676 
      DI => N1,
6677 
      S => fax4_ins_a1b1(0),
6678 
      O => fax4_ins_Madd_vertical_mode_addsub0000_cy(0)
6679 
    );
6680 
  fax4_ins_pix_prev : FDP
6681 
    generic map(
6682 
      INIT => '1'
6683 
    )
6684 
    port map (
6685 
      C => pclk_i,
6686 
      D => fax4_ins_to_white_mux0000,
6687 
      PRE => fax4_ins_pix_change_detector_reset,
6688 
      Q => fax4_ins_pix_prev_1321
6689 
    );
6690 
  fax4_ins_to_white : FDE
6691 
    generic map(
6692 
      INIT => '1'
6693 
    )
6694 
    port map (
6695 
      C => pclk_i,
6696 
      CE => fax4_ins_pix_change_detector_reset_inv,
6697 
      D => fax4_ins_to_white_mux0000,
6698 
      Q => fax4_ins_to_white_1349
6699 
    );
6700 
  fax4_ins_EOL_prev_prev : FD
6701 
    generic map(
6702 
      INIT => '0'
6703 
    )
6704 
    port map (
6705 
      C => pclk_i,
6706 
      D => fax4_ins_EOL_prev_230,
6707 
      Q => fax4_ins_EOL_prev_prev_231
6708 
    );
6709 
  fax4_ins_fifo_out_prev2_x_9 : FDE_1
6710 
    generic map(
6711 
      INIT => '0'
6712 
    )
6713 
    port map (
6714 
      C => pclk_i,
6715 
      CE => fax4_ins_fifo_rd,
6716 
      D => fax4_ins_fifo_out_prev1_x(9),
6717 
      Q => fax4_ins_fifo_out_prev2_x(9)
6718 
    );
6719 
  fax4_ins_fifo_out_prev2_x_8 : FDE_1
6720 
    generic map(
6721 
      INIT => '0'
6722 
    )
6723 
    port map (
6724 
      C => pclk_i,
6725 
      CE => fax4_ins_fifo_rd,
6726 
      D => fax4_ins_fifo_out_prev1_x(8),
6727 
      Q => fax4_ins_fifo_out_prev2_x(8)
6728 
    );
6729 
  fax4_ins_fifo_out_prev2_x_7 : FDE_1
6730 
    generic map(
6731 
      INIT => '0'
6732 
    )
6733 
    port map (
6734 
      C => pclk_i,
6735 
      CE => fax4_ins_fifo_rd,
6736 
      D => fax4_ins_fifo_out_prev1_x(7),
6737 
      Q => fax4_ins_fifo_out_prev2_x(7)
6738 
    );
6739 
  fax4_ins_fifo_out_prev2_x_6 : FDE_1
6740 
    generic map(
6741 
      INIT => '0'
6742 
    )
6743 
    port map (
6744 
      C => pclk_i,
6745 
      CE => fax4_ins_fifo_rd,
6746 
      D => fax4_ins_fifo_out_prev1_x(6),
6747 
      Q => fax4_ins_fifo_out_prev2_x(6)
6748 
    );
6749 
  fax4_ins_fifo_out_prev2_x_5 : FDE_1
6750 
    generic map(
6751 
      INIT => '0'
6752 
    )
6753 
    port map (
6754 
      C => pclk_i,
6755 
      CE => fax4_ins_fifo_rd,
6756 
      D => fax4_ins_fifo_out_prev1_x(5),
6757 
      Q => fax4_ins_fifo_out_prev2_x(5)
6758 
    );
6759 
  fax4_ins_fifo_out_prev2_x_4 : FDE_1
6760 
    generic map(
6761 
      INIT => '0'
6762 
    )
6763 
    port map (
6764 
      C => pclk_i,
6765 
      CE => fax4_ins_fifo_rd,
6766 
      D => fax4_ins_fifo_out_prev1_x(4),
6767 
      Q => fax4_ins_fifo_out_prev2_x(4)
6768 
    );
6769 
  fax4_ins_fifo_out_prev2_x_3 : FDE_1
6770 
    generic map(
6771 
      INIT => '0'
6772 
    )
6773 
    port map (
6774 
      C => pclk_i,
6775 
      CE => fax4_ins_fifo_rd,
6776 
      D => fax4_ins_fifo_out_prev1_x(3),
6777 
      Q => fax4_ins_fifo_out_prev2_x(3)
6778 
    );
6779 
  fax4_ins_fifo_out_prev2_x_2 : FDE_1
6780 
    generic map(
6781 
      INIT => '0'
6782 
    )
6783 
    port map (
6784 
      C => pclk_i,
6785 
      CE => fax4_ins_fifo_rd,
6786 
      D => fax4_ins_fifo_out_prev1_x(2),
6787 
      Q => fax4_ins_fifo_out_prev2_x(2)
6788 
    );
6789 
  fax4_ins_fifo_out_prev2_x_1 : FDE_1
6790 
    generic map(
6791 
      INIT => '0'
6792 
    )
6793 
    port map (
6794 
      C => pclk_i,
6795 
      CE => fax4_ins_fifo_rd,
6796 
      D => fax4_ins_fifo_out_prev1_x(1),
6797 
      Q => fax4_ins_fifo_out_prev2_x(1)
6798 
    );
6799 
  fax4_ins_fifo_out_prev2_x_0 : FDE_1
6800 
    generic map(
6801 
      INIT => '0'
6802 
    )
6803 
    port map (
6804 
      C => pclk_i,
6805 
      CE => fax4_ins_fifo_rd,
6806 
      D => fax4_ins_fifo_out_prev1_x(0),
6807 
      Q => fax4_ins_fifo_out_prev2_x(0)
6808 
    );
6809 
  fax4_ins_fifo_out_prev2_to_white : FDE_1
6810 
    generic map(
6811 
      INIT => '0'
6812 
    )
6813 
    port map (
6814 
      C => pclk_i,
6815 
      CE => fax4_ins_fifo_rd,
6816 
      D => fax4_ins_fifo_out_prev1_to_white_1239,
6817 
      Q => fax4_ins_fifo_out_prev2_to_white_1252
6818 
    );
6819 
  fax4_ins_fifo_sel_prev : FDE_1
6820 
    generic map(
6821 
      INIT => '0'
6822 
    )
6823 
    port map (
6824 
      C => pclk_i,
6825 
      CE => fax4_ins_fifo_rd,
6826 
      D => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
6827 
      Q => fax4_ins_fifo_sel_prev_1279
6828 
    );
6829 
  fax4_ins_a0_value_o : FDE_1
6830 
    generic map(
6831 
      INIT => '0'
6832 
    )
6833 
    port map (
6834 
      C => pclk_i,
6835 
      CE => fax4_ins_load_a0,
6836 
      D => fax4_ins_a0_to_white_946,
6837 
      Q => fax4_ins_a0_value_o_950
6838 
    );
6839 
  fax4_ins_EOL_prev : FD
6840 
    generic map(
6841 
      INIT => '0'
6842 
    )
6843 
    port map (
6844 
      C => pclk_i,
6845 
      D => fax4_ins_EOL,
6846 
      Q => fax4_ins_EOL_prev_230
6847 
    );
6848 
  fax4_ins_a0_o_9 : FDE_1
6849 
    generic map(
6850 
      INIT => '0'
6851 
    )
6852 
    port map (
6853 
      C => pclk_i,
6854 
      CE => fax4_ins_load_a0,
6855 
      D => fax4_ins_a0(9),
6856 
      Q => fax4_ins_a0_o(9)
6857 
    );
6858 
  fax4_ins_a0_o_8 : FDE_1
6859 
    generic map(
6860 
      INIT => '0'
6861 
    )
6862 
    port map (
6863 
      C => pclk_i,
6864 
      CE => fax4_ins_load_a0,
6865 
      D => fax4_ins_a0(8),
6866 
      Q => fax4_ins_a0_o(8)
6867 
    );
6868 
  fax4_ins_a0_o_7 : FDE_1
6869 
    generic map(
6870 
      INIT => '0'
6871 
    )
6872 
    port map (
6873 
      C => pclk_i,
6874 
      CE => fax4_ins_load_a0,
6875 
      D => fax4_ins_a0(7),
6876 
      Q => fax4_ins_a0_o(7)
6877 
    );
6878 
  fax4_ins_a0_o_6 : FDE_1
6879 
    generic map(
6880 
      INIT => '0'
6881 
    )
6882 
    port map (
6883 
      C => pclk_i,
6884 
      CE => fax4_ins_load_a0,
6885 
      D => fax4_ins_a0(6),
6886 
      Q => fax4_ins_a0_o(6)
6887 
    );
6888 
  fax4_ins_a0_o_5 : FDE_1
6889 
    generic map(
6890 
      INIT => '0'
6891 
    )
6892 
    port map (
6893 
      C => pclk_i,
6894 
      CE => fax4_ins_load_a0,
6895 
      D => fax4_ins_a0(5),
6896 
      Q => fax4_ins_a0_o(5)
6897 
    );
6898 
  fax4_ins_a0_o_4 : FDE_1
6899 
    generic map(
6900 
      INIT => '0'
6901 
    )
6902 
    port map (
6903 
      C => pclk_i,
6904 
      CE => fax4_ins_load_a0,
6905 
      D => fax4_ins_a0(4),
6906 
      Q => fax4_ins_a0_o(4)
6907 
    );
6908 
  fax4_ins_a0_o_3 : FDE_1
6909 
    generic map(
6910 
      INIT => '0'
6911 
    )
6912 
    port map (
6913 
      C => pclk_i,
6914 
      CE => fax4_ins_load_a0,
6915 
      D => fax4_ins_a0(3),
6916 
      Q => fax4_ins_a0_o(3)
6917 
    );
6918 
  fax4_ins_a0_o_2 : FDE_1
6919 
    generic map(
6920 
      INIT => '0'
6921 
    )
6922 
    port map (
6923 
      C => pclk_i,
6924 
      CE => fax4_ins_load_a0,
6925 
      D => fax4_ins_a0(2),
6926 
      Q => fax4_ins_a0_o(2)
6927 
    );
6928 
  fax4_ins_a0_o_1 : FDE_1
6929 
    generic map(
6930 
      INIT => '0'
6931 
    )
6932 
    port map (
6933 
      C => pclk_i,
6934 
      CE => fax4_ins_load_a0,
6935 
      D => fax4_ins_a0(1),
6936 
      Q => fax4_ins_a0_o(1)
6937 
    );
6938 
  fax4_ins_a0_o_0 : FDE_1
6939 
    generic map(
6940 
      INIT => '0'
6941 
    )
6942 
    port map (
6943 
      C => pclk_i,
6944 
      CE => fax4_ins_load_a0,
6945 
      D => fax4_ins_a0(0),
6946 
      Q => fax4_ins_a0_o(0)
6947 
    );
6948 
  fax4_ins_fifo_out_prev1_valid : FDE_1
6949 
    generic map(
6950 
      INIT => '0'
6951 
    )
6952 
    port map (
6953 
      C => pclk_i,
6954 
      CE => fax4_ins_fifo_rd,
6955 
      D => fax4_ins_fifo_out_prev1_valid_mux0001,
6956 
      Q => fax4_ins_fifo_out_prev1_valid_1240
6957 
    );
6958 
  fax4_ins_fifo_out_prev2_valid : FDE_1
6959 
    generic map(
6960 
      INIT => '0'
6961 
    )
6962 
    port map (
6963 
      C => pclk_i,
6964 
      CE => fax4_ins_fifo_rd,
6965 
      D => fax4_ins_fifo_out_prev2_valid_mux0001,
6966 
      Q => fax4_ins_fifo_out_prev2_valid_1253
6967 
    );
6968 
  fax4_ins_fifo_out_prev1_x_9 : FDE_1
6969 
    generic map(
6970 
      INIT => '0'
6971 
    )
6972 
    port map (
6973 
      C => pclk_i,
6974 
      CE => fax4_ins_fifo_rd,
6975 
      D => fax4_ins_fifo_out1_x(9),
6976 
      Q => fax4_ins_fifo_out_prev1_x(9)
6977 
    );
6978 
  fax4_ins_fifo_out_prev1_x_8 : FDE_1
6979 
    generic map(
6980 
      INIT => '0'
6981 
    )
6982 
    port map (
6983 
      C => pclk_i,
6984 
      CE => fax4_ins_fifo_rd,
6985 
      D => fax4_ins_fifo_out1_x(8),
6986 
      Q => fax4_ins_fifo_out_prev1_x(8)
6987 
    );
6988 
  fax4_ins_fifo_out_prev1_x_7 : FDE_1
6989 
    generic map(
6990 
      INIT => '0'
6991 
    )
6992 
    port map (
6993 
      C => pclk_i,
6994 
      CE => fax4_ins_fifo_rd,
6995 
      D => fax4_ins_fifo_out1_x(7),
6996 
      Q => fax4_ins_fifo_out_prev1_x(7)
6997 
    );
6998 
  fax4_ins_fifo_out_prev1_x_6 : FDE_1
6999 
    generic map(
7000 
      INIT => '0'
7001 
    )
7002 
    port map (
7003 
      C => pclk_i,
7004 
      CE => fax4_ins_fifo_rd,
7005 
      D => fax4_ins_fifo_out1_x(6),
7006 
      Q => fax4_ins_fifo_out_prev1_x(6)
7007 
    );
7008 
  fax4_ins_fifo_out_prev1_x_5 : FDE_1
7009 
    generic map(
7010 
      INIT => '0'
7011 
    )
7012 
    port map (
7013 
      C => pclk_i,
7014 
      CE => fax4_ins_fifo_rd,
7015 
      D => fax4_ins_fifo_out1_x(5),
7016 
      Q => fax4_ins_fifo_out_prev1_x(5)
7017 
    );
7018 
  fax4_ins_fifo_out_prev1_x_4 : FDE_1
7019 
    generic map(
7020 
      INIT => '0'
7021 
    )
7022 
    port map (
7023 
      C => pclk_i,
7024 
      CE => fax4_ins_fifo_rd,
7025 
      D => fax4_ins_fifo_out1_x(4),
7026 
      Q => fax4_ins_fifo_out_prev1_x(4)
7027 
    );
7028 
  fax4_ins_fifo_out_prev1_x_3 : FDE_1
7029 
    generic map(
7030 
      INIT => '0'
7031 
    )
7032 
    port map (
7033 
      C => pclk_i,
7034 
      CE => fax4_ins_fifo_rd,
7035 
      D => fax4_ins_fifo_out1_x(3),
7036 
      Q => fax4_ins_fifo_out_prev1_x(3)
7037 
    );
7038 
  fax4_ins_fifo_out_prev1_x_2 : FDE_1
7039 
    generic map(
7040 
      INIT => '0'
7041 
    )
7042 
    port map (
7043 
      C => pclk_i,
7044 
      CE => fax4_ins_fifo_rd,
7045 
      D => fax4_ins_fifo_out1_x(2),
7046 
      Q => fax4_ins_fifo_out_prev1_x(2)
7047 
    );
7048 
  fax4_ins_fifo_out_prev1_x_1 : FDE_1
7049 
    generic map(
7050 
      INIT => '0'
7051 
    )
7052 
    port map (
7053 
      C => pclk_i,
7054 
      CE => fax4_ins_fifo_rd,
7055 
      D => fax4_ins_fifo_out1_x(1),
7056 
      Q => fax4_ins_fifo_out_prev1_x(1)
7057 
    );
7058 
  fax4_ins_fifo_out_prev1_x_0 : FDE_1
7059 
    generic map(
7060 
      INIT => '0'
7061 
    )
7062 
    port map (
7063 
      C => pclk_i,
7064 
      CE => fax4_ins_fifo_rd,
7065 
      D => fax4_ins_fifo_out1_x(0),
7066 
      Q => fax4_ins_fifo_out_prev1_x(0)
7067 
    );
7068 
  fax4_ins_b2_9 : FDE
7069 
    generic map(
7070 
      INIT => '0'
7071 
    )
7072 
    port map (
7073 
      C => pclk_i,
7074 
      CE => fax4_ins_load_mux_b_1285,
7075 
      D => fax4_ins_b2_mux0004(9),
7076 
      Q => fax4_ins_b2(9)
7077 
    );
7078 
  fax4_ins_b2_8 : FDE
7079 
    generic map(
7080 
      INIT => '0'
7081 
    )
7082 
    port map (
7083 
      C => pclk_i,
7084 
      CE => fax4_ins_load_mux_b_1285,
7085 
      D => fax4_ins_b2_mux0004(8),
7086 
      Q => fax4_ins_b2(8)
7087 
    );
7088 
  fax4_ins_b2_7 : FDE
7089 
    generic map(
7090 
      INIT => '0'
7091 
    )
7092 
    port map (
7093 
      C => pclk_i,
7094 
      CE => fax4_ins_load_mux_b_1285,
7095 
      D => fax4_ins_b2_mux0004(7),
7096 
      Q => fax4_ins_b2(7)
7097 
    );
7098 
  fax4_ins_b2_6 : FDE
7099 
    generic map(
7100 
      INIT => '0'
7101 
    )
7102 
    port map (
7103 
      C => pclk_i,
7104 
      CE => fax4_ins_load_mux_b_1285,
7105 
      D => fax4_ins_b2_mux0004(6),
7106 
      Q => fax4_ins_b2(6)
7107 
    );
7108 
  fax4_ins_b2_5 : FDE
7109 
    generic map(
7110 
      INIT => '0'
7111 
    )
7112 
    port map (
7113 
      C => pclk_i,
7114 
      CE => fax4_ins_load_mux_b_1285,
7115 
      D => fax4_ins_b2_mux0004(5),
7116 
      Q => fax4_ins_b2(5)
7117 
    );
7118 
  fax4_ins_b2_4 : FDE
7119 
    generic map(
7120 
      INIT => '0'
7121 
    )
7122 
    port map (
7123 
      C => pclk_i,
7124 
      CE => fax4_ins_load_mux_b_1285,
7125 
      D => fax4_ins_b2_mux0004(4),
7126 
      Q => fax4_ins_b2(4)
7127 
    );
7128 
  fax4_ins_b2_3 : FDE
7129 
    generic map(
7130 
      INIT => '0'
7131 
    )
7132 
    port map (
7133 
      C => pclk_i,
7134 
      CE => fax4_ins_load_mux_b_1285,
7135 
      D => fax4_ins_b2_mux0004(3),
7136 
      Q => fax4_ins_b2(3)
7137 
    );
7138 
  fax4_ins_b2_2 : FDE
7139 
    generic map(
7140 
      INIT => '0'
7141 
    )
7142 
    port map (
7143 
      C => pclk_i,
7144 
      CE => fax4_ins_load_mux_b_1285,
7145 
      D => fax4_ins_b2_mux0004(2),
7146 
      Q => fax4_ins_b2(2)
7147 
    );
7148 
  fax4_ins_b2_1 : FDE
7149 
    generic map(
7150 
      INIT => '0'
7151 
    )
7152 
    port map (
7153 
      C => pclk_i,
7154 
      CE => fax4_ins_load_mux_b_1285,
7155 
      D => fax4_ins_b2_mux0004(1),
7156 
      Q => fax4_ins_b2(1)
7157 
    );
7158 
  fax4_ins_b2_0 : FDE
7159 
    generic map(
7160 
      INIT => '0'
7161 
    )
7162 
    port map (
7163 
      C => pclk_i,
7164 
      CE => fax4_ins_load_mux_b_1285,
7165 
      D => fax4_ins_b2_mux0004(0),
7166 
      Q => fax4_ins_b2(0)
7167 
    );
7168 
  fax4_ins_a0_9 : FDE_1
7169 
    generic map(
7170 
      INIT => '0'
7171 
    )
7172 
    port map (
7173 
      C => pclk_i,
7174 
      CE => fax4_ins_load_mux_a0_1284,
7175 
      D => fax4_ins_a0_mux0000(0),
7176 
      Q => fax4_ins_a0(9)
7177 
    );
7178 
  fax4_ins_a0_8 : FDE_1
7179 
    generic map(
7180 
      INIT => '0'
7181 
    )
7182 
    port map (
7183 
      C => pclk_i,
7184 
      CE => fax4_ins_load_mux_a0_1284,
7185 
      D => fax4_ins_a0_mux0000(1),
7186 
      Q => fax4_ins_a0(8)
7187 
    );
7188 
  fax4_ins_a0_7 : FDE_1
7189 
    generic map(
7190 
      INIT => '0'
7191 
    )
7192 
    port map (
7193 
      C => pclk_i,
7194 
      CE => fax4_ins_load_mux_a0_1284,
7195 
      D => fax4_ins_a0_mux0000(2),
7196 
      Q => fax4_ins_a0(7)
7197 
    );
7198 
  fax4_ins_a0_6 : FDE_1
7199 
    generic map(
7200 
      INIT => '0'
7201 
    )
7202 
    port map (
7203 
      C => pclk_i,
7204 
      CE => fax4_ins_load_mux_a0_1284,
7205 
      D => fax4_ins_a0_mux0000(3),
7206 
      Q => fax4_ins_a0(6)
7207 
    );
7208 
  fax4_ins_a0_5 : FDE_1
7209 
    generic map(
7210 
      INIT => '0'
7211 
    )
7212 
    port map (
7213 
      C => pclk_i,
7214 
      CE => fax4_ins_load_mux_a0_1284,
7215 
      D => fax4_ins_a0_mux0000(4),
7216 
      Q => fax4_ins_a0(5)
7217 
    );
7218 
  fax4_ins_a0_4 : FDE_1
7219 
    generic map(
7220 
      INIT => '0'
7221 
    )
7222 
    port map (
7223 
      C => pclk_i,
7224 
      CE => fax4_ins_load_mux_a0_1284,
7225 
      D => fax4_ins_a0_mux0000(5),
7226 
      Q => fax4_ins_a0(4)
7227 
    );
7228 
  fax4_ins_a0_3 : FDE_1
7229 
    generic map(
7230 
      INIT => '0'
7231 
    )
7232 
    port map (
7233 
      C => pclk_i,
7234 
      CE => fax4_ins_load_mux_a0_1284,
7235 
      D => fax4_ins_a0_mux0000(6),
7236 
      Q => fax4_ins_a0(3)
7237 
    );
7238 
  fax4_ins_a0_2 : FDE_1
7239 
    generic map(
7240 
      INIT => '0'
7241 
    )
7242 
    port map (
7243 
      C => pclk_i,
7244 
      CE => fax4_ins_load_mux_a0_1284,
7245 
      D => fax4_ins_a0_mux0000(7),
7246 
      Q => fax4_ins_a0(2)
7247 
    );
7248 
  fax4_ins_a0_1 : FDE_1
7249 
    generic map(
7250 
      INIT => '0'
7251 
    )
7252 
    port map (
7253 
      C => pclk_i,
7254 
      CE => fax4_ins_load_mux_a0_1284,
7255 
      D => fax4_ins_a0_mux0000(8),
7256 
      Q => fax4_ins_a0(1)
7257 
    );
7258 
  fax4_ins_a0_0 : FDE_1
7259 
    generic map(
7260 
      INIT => '0'
7261 
    )
7262 
    port map (
7263 
      C => pclk_i,
7264 
      CE => fax4_ins_load_mux_a0_1284,
7265 
      D => fax4_ins_a0_mux0000(9),
7266 
      Q => fax4_ins_a0(0)
7267 
    );
7268 
  fax4_ins_b1_9 : FDE
7269 
    generic map(
7270 
      INIT => '0'
7271 
    )
7272 
    port map (
7273 
      C => pclk_i,
7274 
      CE => fax4_ins_load_mux_b_1285,
7275 
      D => fax4_ins_b1_mux0004(9),
7276 
      Q => fax4_ins_b1(9)
7277 
    );
7278 
  fax4_ins_b1_8 : FDE
7279 
    generic map(
7280 
      INIT => '0'
7281 
    )
7282 
    port map (
7283 
      C => pclk_i,
7284 
      CE => fax4_ins_load_mux_b_1285,
7285 
      D => fax4_ins_b1_mux0004(8),
7286 
      Q => fax4_ins_b1(8)
7287 
    );
7288 
  fax4_ins_b1_7 : FDE
7289 
    generic map(
7290 
      INIT => '0'
7291 
    )
7292 
    port map (
7293 
      C => pclk_i,
7294 
      CE => fax4_ins_load_mux_b_1285,
7295 
      D => fax4_ins_b1_mux0004(7),
7296 
      Q => fax4_ins_b1(7)
7297 
    );
7298 
  fax4_ins_b1_6 : FDE
7299 
    generic map(
7300 
      INIT => '0'
7301 
    )
7302 
    port map (
7303 
      C => pclk_i,
7304 
      CE => fax4_ins_load_mux_b_1285,
7305 
      D => fax4_ins_b1_mux0004(6),
7306 
      Q => fax4_ins_b1(6)
7307 
    );
7308 
  fax4_ins_b1_5 : FDE
7309 
    generic map(
7310 
      INIT => '0'
7311 
    )
7312 
    port map (
7313 
      C => pclk_i,
7314 
      CE => fax4_ins_load_mux_b_1285,
7315 
      D => fax4_ins_b1_mux0004(5),
7316 
      Q => fax4_ins_b1(5)
7317 
    );
7318 
  fax4_ins_b1_4 : FDE
7319 
    generic map(
7320 
      INIT => '0'
7321 
    )
7322 
    port map (
7323 
      C => pclk_i,
7324 
      CE => fax4_ins_load_mux_b_1285,
7325 
      D => fax4_ins_b1_mux0004(4),
7326 
      Q => fax4_ins_b1(4)
7327 
    );
7328 
  fax4_ins_b1_3 : FDE
7329 
    generic map(
7330 
      INIT => '0'
7331 
    )
7332 
    port map (
7333 
      C => pclk_i,
7334 
      CE => fax4_ins_load_mux_b_1285,
7335 
      D => fax4_ins_b1_mux0004(3),
7336 
      Q => fax4_ins_b1(3)
7337 
    );
7338 
  fax4_ins_b1_2 : FDE
7339 
    generic map(
7340 
      INIT => '0'
7341 
    )
7342 
    port map (
7343 
      C => pclk_i,
7344 
      CE => fax4_ins_load_mux_b_1285,
7345 
      D => fax4_ins_b1_mux0004(2),
7346 
      Q => fax4_ins_b1(2)
7347 
    );
7348 
  fax4_ins_b1_1 : FDE
7349 
    generic map(
7350 
      INIT => '0'
7351 
    )
7352 
    port map (
7353 
      C => pclk_i,
7354 
      CE => fax4_ins_load_mux_b_1285,
7355 
      D => fax4_ins_b1_mux0004(1),
7356 
      Q => fax4_ins_b1(1)
7357 
    );
7358 
  fax4_ins_b1_0 : FDE
7359 
    generic map(
7360 
      INIT => '0'
7361 
    )
7362 
    port map (
7363 
      C => pclk_i,
7364 
      CE => fax4_ins_load_mux_b_1285,
7365 
      D => fax4_ins_b1_mux0004(0),
7366 
      Q => fax4_ins_b1(0)
7367 
    );
7368 
  fax4_ins_a0_to_white : FDE_1
7369 
    generic map(
7370 
      INIT => '0'
7371 
    )
7372 
    port map (
7373 
      C => pclk_i,
7374 
      CE => fax4_ins_load_mux_a0_1284,
7375 
      D => fax4_ins_a0_to_white_mux0000,
7376 
      Q => fax4_ins_a0_to_white_946
7377 
    );
7378 
  fax4_ins_a2_o_9 : FDE_1
7379 
    generic map(
7380 
      INIT => '0'
7381 
    )
7382 
    port map (
7383 
      C => pclk_i,
7384 
      CE => fax4_ins_load_a2,
7385 
      D => fax4_ins_a1_o_mux0000(0),
7386 
      Q => fax4_ins_a2_o(9)
7387 
    );
7388 
  fax4_ins_a2_o_8 : FDE_1
7389 
    generic map(
7390 
      INIT => '0'
7391 
    )
7392 
    port map (
7393 
      C => pclk_i,
7394 
      CE => fax4_ins_load_a2,
7395 
      D => fax4_ins_a1_o_mux0000(1),
7396 
      Q => fax4_ins_a2_o(8)
7397 
    );
7398 
  fax4_ins_a2_o_7 : FDE_1
7399 
    generic map(
7400 
      INIT => '0'
7401 
    )
7402 
    port map (
7403 
      C => pclk_i,
7404 
      CE => fax4_ins_load_a2,
7405 
      D => fax4_ins_a1_o_mux0000(2),
7406 
      Q => fax4_ins_a2_o(7)
7407 
    );
7408 
  fax4_ins_a2_o_6 : FDE_1
7409 
    generic map(
7410 
      INIT => '0'
7411 
    )
7412 
    port map (
7413 
      C => pclk_i,
7414 
      CE => fax4_ins_load_a2,
7415 
      D => fax4_ins_a1_o_mux0000(3),
7416 
      Q => fax4_ins_a2_o(6)
7417 
    );
7418 
  fax4_ins_a2_o_5 : FDE_1
7419 
    generic map(
7420 
      INIT => '0'
7421 
    )
7422 
    port map (
7423 
      C => pclk_i,
7424 
      CE => fax4_ins_load_a2,
7425 
      D => fax4_ins_a1_o_mux0000(4),
7426 
      Q => fax4_ins_a2_o(5)
7427 
    );
7428 
  fax4_ins_a2_o_4 : FDE_1
7429 
    generic map(
7430 
      INIT => '0'
7431 
    )
7432 
    port map (
7433 
      C => pclk_i,
7434 
      CE => fax4_ins_load_a2,
7435 
      D => fax4_ins_a1_o_mux0000(5),
7436 
      Q => fax4_ins_a2_o(4)
7437 
    );
7438 
  fax4_ins_a2_o_3 : FDE_1
7439 
    generic map(
7440 
      INIT => '0'
7441 
    )
7442 
    port map (
7443 
      C => pclk_i,
7444 
      CE => fax4_ins_load_a2,
7445 
      D => fax4_ins_a1_o_mux0000(6),
7446 
      Q => fax4_ins_a2_o(3)
7447 
    );
7448 
  fax4_ins_a2_o_2 : FDE_1
7449 
    generic map(
7450 
      INIT => '0'
7451 
    )
7452 
    port map (
7453 
      C => pclk_i,
7454 
      CE => fax4_ins_load_a2,
7455 
      D => fax4_ins_a1_o_mux0000(7),
7456 
      Q => fax4_ins_a2_o(2)
7457 
    );
7458 
  fax4_ins_a2_o_1 : FDE_1
7459 
    generic map(
7460 
      INIT => '0'
7461 
    )
7462 
    port map (
7463 
      C => pclk_i,
7464 
      CE => fax4_ins_load_a2,
7465 
      D => fax4_ins_a1_o_mux0000(8),
7466 
      Q => fax4_ins_a2_o(1)
7467 
    );
7468 
  fax4_ins_a2_o_0 : FDE_1
7469 
    generic map(
7470 
      INIT => '0'
7471 
    )
7472 
    port map (
7473 
      C => pclk_i,
7474 
      CE => fax4_ins_load_a2,
7475 
      D => fax4_ins_a1_o_mux0000(9),
7476 
      Q => fax4_ins_a2_o(0)
7477 
    );
7478 
  fax4_ins_a1_o_9 : FDE_1
7479 
    generic map(
7480 
      INIT => '0'
7481 
    )
7482 
    port map (
7483 
      C => pclk_i,
7484 
      CE => fax4_ins_load_a0,
7485 
      D => fax4_ins_a1_o_mux0000(0),
7486 
      Q => fax4_ins_a1_o(9)
7487 
    );
7488 
  fax4_ins_a1_o_8 : FDE_1
7489 
    generic map(
7490 
      INIT => '0'
7491 
    )
7492 
    port map (
7493 
      C => pclk_i,
7494 
      CE => fax4_ins_load_a0,
7495 
      D => fax4_ins_a1_o_mux0000(1),
7496 
      Q => fax4_ins_a1_o(8)
7497 
    );
7498 
  fax4_ins_a1_o_7 : FDE_1
7499 
    generic map(
7500 
      INIT => '0'
7501 
    )
7502 
    port map (
7503 
      C => pclk_i,
7504 
      CE => fax4_ins_load_a0,
7505 
      D => fax4_ins_a1_o_mux0000(2),
7506 
      Q => fax4_ins_a1_o(7)
7507 
    );
7508 
  fax4_ins_a1_o_6 : FDE_1
7509 
    generic map(
7510 
      INIT => '0'
7511 
    )
7512 
    port map (
7513 
      C => pclk_i,
7514 
      CE => fax4_ins_load_a0,
7515 
      D => fax4_ins_a1_o_mux0000(3),
7516 
      Q => fax4_ins_a1_o(6)
7517 
    );
7518 
  fax4_ins_a1_o_5 : FDE_1
7519 
    generic map(
7520 
      INIT => '0'
7521 
    )
7522 
    port map (
7523 
      C => pclk_i,
7524 
      CE => fax4_ins_load_a0,
7525 
      D => fax4_ins_a1_o_mux0000(4),
7526 
      Q => fax4_ins_a1_o(5)
7527 
    );
7528 
  fax4_ins_a1_o_4 : FDE_1
7529 
    generic map(
7530 
      INIT => '0'
7531 
    )
7532 
    port map (
7533 
      C => pclk_i,
7534 
      CE => fax4_ins_load_a0,
7535 
      D => fax4_ins_a1_o_mux0000(5),
7536 
      Q => fax4_ins_a1_o(4)
7537 
    );
7538 
  fax4_ins_a1_o_3 : FDE_1
7539 
    generic map(
7540 
      INIT => '0'
7541 
    )
7542 
    port map (
7543 
      C => pclk_i,
7544 
      CE => fax4_ins_load_a0,
7545 
      D => fax4_ins_a1_o_mux0000(6),
7546 
      Q => fax4_ins_a1_o(3)
7547 
    );
7548 
  fax4_ins_a1_o_2 : FDE_1
7549 
    generic map(
7550 
      INIT => '0'
7551 
    )
7552 
    port map (
7553 
      C => pclk_i,
7554 
      CE => fax4_ins_load_a0,
7555 
      D => fax4_ins_a1_o_mux0000(7),
7556 
      Q => fax4_ins_a1_o(2)
7557 
    );
7558 
  fax4_ins_a1_o_1 : FDE_1
7559 
    generic map(
7560 
      INIT => '0'
7561 
    )
7562 
    port map (
7563 
      C => pclk_i,
7564 
      CE => fax4_ins_load_a0,
7565 
      D => fax4_ins_a1_o_mux0000(8),
7566 
      Q => fax4_ins_a1_o(1)
7567 
    );
7568 
  fax4_ins_a1_o_0 : FDE_1
7569 
    generic map(
7570 
      INIT => '0'
7571 
    )
7572 
    port map (
7573 
      C => pclk_i,
7574 
      CE => fax4_ins_load_a0,
7575 
      D => fax4_ins_a1_o_mux0000(9),
7576 
      Q => fax4_ins_a1_o(0)
7577 
    );
7578 
  fax4_ins_b2_to_white : FDE
7579 
    generic map(
7580 
      INIT => '0'
7581 
    )
7582 
    port map (
7583 
      C => pclk_i,
7584 
      CE => fax4_ins_load_mux_b_1285,
7585 
      D => fax4_ins_b2_to_white_mux0004,
7586 
      Q => fax4_ins_b2_to_white_1094
7587 
    );
7588 
  fax4_ins_fifo_out_prev1_to_white : FDE_1
7589 
    generic map(
7590 
      INIT => '0'
7591 
    )
7592 
    port map (
7593 
      C => pclk_i,
7594 
      CE => fax4_ins_fifo_rd,
7595 
      D => fax4_ins_fifo_out1_to_white,
7596 
      Q => fax4_ins_fifo_out_prev1_to_white_1239
7597 
    );
7598 
  fax4_ins_pix_changed : FDC
7599 
    generic map(
7600 
      INIT => '0'
7601 
    )
7602 
    port map (
7603 
      C => pclk_i,
7604 
      CLR => fax4_ins_pix_change_detector_reset,
7605 
      D => fax4_ins_pix_changed_mux0001,
7606 
      Q => fax4_ins_pix_changed_1319
7607 
    );
7608 
  fax4_ins_to_white_mux00001 : LUT2
7609 
    generic map(
7610 
      INIT => X"D"
7611 
    )
7612 
    port map (
7613 
      I0 => rsync_i,
7614 
      I1 => pix_i,
7615 
      O => fax4_ins_to_white_mux0000
7616 
    );
7617 
  huffman_ins_v2_run_len_code_width_o_4_1 : LUT2
7618 
    generic map(
7619 
      INIT => X"8"
7620 
    )
7621 
    port map (
7622 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7623 
      I1 => huffman_ins_v2_hor_code_width(4),
7624 
      O => run_len_code_width_o(4)
7625 
    );
7626 
  huffman_ins_v2_run_len_code_width_o_3_1 : LUT2
7627 
    generic map(
7628 
      INIT => X"8"
7629 
    )
7630 
    port map (
7631 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7632 
      I1 => huffman_ins_v2_hor_code_width(3),
7633 
      O => run_len_code_width_o(3)
7634 
    );
7635 
  huffman_ins_v2_run_len_code_o_9_1 : LUT2
7636 
    generic map(
7637 
      INIT => X"8"
7638 
    )
7639 
    port map (
7640 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7641 
      I1 => huffman_ins_v2_hor_code(9),
7642 
      O => run_len_code_o(9)
7643 
    );
7644 
  huffman_ins_v2_run_len_code_o_8_1 : LUT2
7645 
    generic map(
7646 
      INIT => X"8"
7647 
    )
7648 
    port map (
7649 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7650 
      I1 => huffman_ins_v2_hor_code(8),
7651 
      O => run_len_code_o(8)
7652 
    );
7653 
  huffman_ins_v2_run_len_code_o_7_1 : LUT2
7654 
    generic map(
7655 
      INIT => X"8"
7656 
    )
7657 
    port map (
7658 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7659 
      I1 => huffman_ins_v2_hor_code(7),
7660 
      O => run_len_code_o(7)
7661 
    );
7662 
  huffman_ins_v2_run_len_code_o_25_1 : LUT2
7663 
    generic map(
7664 
      INIT => X"8"
7665 
    )
7666 
    port map (
7667 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7668 
      I1 => huffman_ins_v2_hor_code(25),
7669 
      O => run_len_code_o(25)
7670 
    );
7671 
  huffman_ins_v2_run_len_code_o_24_1 : LUT2
7672 
    generic map(
7673 
      INIT => X"8"
7674 
    )
7675 
    port map (
7676 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7677 
      I1 => huffman_ins_v2_hor_code(24),
7678 
      O => run_len_code_o(24)
7679 
    );
7680 
  huffman_ins_v2_run_len_code_o_23_1 : LUT2
7681 
    generic map(
7682 
      INIT => X"8"
7683 
    )
7684 
    port map (
7685 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7686 
      I1 => huffman_ins_v2_hor_code(23),
7687 
      O => run_len_code_o(23)
7688 
    );
7689 
  huffman_ins_v2_run_len_code_o_22_1 : LUT2
7690 
    generic map(
7691 
      INIT => X"8"
7692 
    )
7693 
    port map (
7694 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7695 
      I1 => huffman_ins_v2_hor_code(22),
7696 
      O => run_len_code_o(22)
7697 
    );
7698 
  huffman_ins_v2_run_len_code_o_21_1 : LUT2
7699 
    generic map(
7700 
      INIT => X"8"
7701 
    )
7702 
    port map (
7703 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7704 
      I1 => huffman_ins_v2_hor_code(21),
7705 
      O => run_len_code_o(21)
7706 
    );
7707 
  huffman_ins_v2_run_len_code_o_20_1 : LUT2
7708 
    generic map(
7709 
      INIT => X"8"
7710 
    )
7711 
    port map (
7712 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7713 
      I1 => huffman_ins_v2_hor_code(20),
7714 
      O => run_len_code_o(20)
7715 
    );
7716 
  huffman_ins_v2_run_len_code_o_19_1 : LUT2
7717 
    generic map(
7718 
      INIT => X"8"
7719 
    )
7720 
    port map (
7721 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7722 
      I1 => huffman_ins_v2_hor_code(19),
7723 
      O => run_len_code_o(19)
7724 
    );
7725 
  huffman_ins_v2_run_len_code_o_18_1 : LUT2
7726 
    generic map(
7727 
      INIT => X"8"
7728 
    )
7729 
    port map (
7730 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7731 
      I1 => huffman_ins_v2_hor_code(18),
7732 
      O => run_len_code_o(18)
7733 
    );
7734 
  huffman_ins_v2_run_len_code_o_17_1 : LUT2
7735 
    generic map(
7736 
      INIT => X"8"
7737 
    )
7738 
    port map (
7739 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7740 
      I1 => huffman_ins_v2_hor_code(17),
7741 
      O => run_len_code_o(17)
7742 
    );
7743 
  huffman_ins_v2_run_len_code_o_16_1 : LUT2
7744 
    generic map(
7745 
      INIT => X"8"
7746 
    )
7747 
    port map (
7748 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7749 
      I1 => huffman_ins_v2_hor_code(16),
7750 
      O => run_len_code_o(16)
7751 
    );
7752 
  huffman_ins_v2_run_len_code_o_15_1 : LUT2
7753 
    generic map(
7754 
      INIT => X"8"
7755 
    )
7756 
    port map (
7757 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7758 
      I1 => huffman_ins_v2_hor_code(15),
7759 
      O => run_len_code_o(15)
7760 
    );
7761 
  huffman_ins_v2_run_len_code_o_14_1 : LUT2
7762 
    generic map(
7763 
      INIT => X"8"
7764 
    )
7765 
    port map (
7766 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7767 
      I1 => huffman_ins_v2_hor_code(14),
7768 
      O => run_len_code_o(14)
7769 
    );
7770 
  huffman_ins_v2_run_len_code_o_13_1 : LUT2
7771 
    generic map(
7772 
      INIT => X"8"
7773 
    )
7774 
    port map (
7775 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7776 
      I1 => huffman_ins_v2_hor_code(13),
7777 
      O => run_len_code_o(13)
7778 
    );
7779 
  huffman_ins_v2_run_len_code_o_12_1 : LUT2
7780 
    generic map(
7781 
      INIT => X"8"
7782 
    )
7783 
    port map (
7784 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7785 
      I1 => huffman_ins_v2_hor_code(12),
7786 
      O => run_len_code_o(12)
7787 
    );
7788 
  huffman_ins_v2_run_len_code_o_11_1 : LUT2
7789 
    generic map(
7790 
      INIT => X"8"
7791 
    )
7792 
    port map (
7793 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7794 
      I1 => huffman_ins_v2_hor_code(11),
7795 
      O => run_len_code_o(11)
7796 
    );
7797 
  huffman_ins_v2_run_len_code_o_10_1 : LUT2
7798 
    generic map(
7799 
      INIT => X"8"
7800 
    )
7801 
    port map (
7802 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7803 
      I1 => huffman_ins_v2_hor_code(10),
7804 
      O => run_len_code_o(10)
7805 
    );
7806 
  huffman_ins_v2_run_len_code_width_o_2_1 : LUT3
7807 
    generic map(
7808 
      INIT => X"E4"
7809 
    )
7810 
    port map (
7811 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7812 
      I1 => huffman_ins_v2_pass_vert_code_width_3_2_Q,
7813 
      I2 => huffman_ins_v2_hor_code_width(2),
7814 
      O => run_len_code_width_o(2)
7815 
    );
7816 
  huffman_ins_v2_run_len_code_width_o_1_1 : LUT3
7817 
    generic map(
7818 
      INIT => X"E4"
7819 
    )
7820 
    port map (
7821 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7822 
      I1 => huffman_ins_v2_pass_vert_code_3(1),
7823 
      I2 => huffman_ins_v2_hor_code_width(1),
7824 
      O => run_len_code_width_o(1)
7825 
    );
7826 
  huffman_ins_v2_run_len_code_width_o_0_1 : LUT3
7827 
    generic map(
7828 
      INIT => X"E4"
7829 
    )
7830 
    port map (
7831 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7832 
      I1 => huffman_ins_v2_pass_vert_code_width_3_0_Q,
7833 
      I2 => huffman_ins_v2_hor_code_width(0),
7834 
      O => run_len_code_width_o(0)
7835 
    );
7836 
  huffman_ins_v2_run_len_code_o_6_1 : LUT3
7837 
    generic map(
7838 
      INIT => X"E4"
7839 
    )
7840 
    port map (
7841 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7842 
      I1 => huffman_ins_v2_pass_vert_code_3(2),
7843 
      I2 => huffman_ins_v2_hor_code(6),
7844 
      O => run_len_code_o(6)
7845 
    );
7846 
  huffman_ins_v2_run_len_code_o_5_1 : LUT3
7847 
    generic map(
7848 
      INIT => X"E4"
7849 
    )
7850 
    port map (
7851 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7852 
      I1 => huffman_ins_v2_pass_vert_code_3(2),
7853 
      I2 => huffman_ins_v2_hor_code(5),
7854 
      O => run_len_code_o(5)
7855 
    );
7856 
  huffman_ins_v2_run_len_code_o_4_1 : LUT3
7857 
    generic map(
7858 
      INIT => X"E4"
7859 
    )
7860 
    port map (
7861 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7862 
      I1 => huffman_ins_v2_pass_vert_code_3(2),
7863 
      I2 => huffman_ins_v2_hor_code(4),
7864 
      O => run_len_code_o(4)
7865 
    );
7866 
  huffman_ins_v2_run_len_code_o_3_1 : LUT3
7867 
    generic map(
7868 
      INIT => X"E4"
7869 
    )
7870 
    port map (
7871 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7872 
      I1 => huffman_ins_v2_pass_vert_code_3(2),
7873 
      I2 => huffman_ins_v2_hor_code(3),
7874 
      O => run_len_code_o(3)
7875 
    );
7876 
  huffman_ins_v2_run_len_code_o_2_1 : LUT3
7877 
    generic map(
7878 
      INIT => X"E4"
7879 
    )
7880 
    port map (
7881 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7882 
      I1 => huffman_ins_v2_pass_vert_code_3(2),
7883 
      I2 => huffman_ins_v2_hor_code(2),
7884 
      O => run_len_code_o(2)
7885 
    );
7886 
  huffman_ins_v2_run_len_code_o_1_1 : LUT3
7887 
    generic map(
7888 
      INIT => X"E4"
7889 
    )
7890 
    port map (
7891 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7892 
      I1 => huffman_ins_v2_pass_vert_code_3(1),
7893 
      I2 => huffman_ins_v2_hor_code(1),
7894 
      O => run_len_code_o(1)
7895 
    );
7896 
  huffman_ins_v2_run_len_code_o_0_1 : LUT3
7897 
    generic map(
7898 
      INIT => X"E4"
7899 
    )
7900 
    port map (
7901 
      I0 => huffman_ins_v2_horizontal_mode_3_2063,
7902 
      I1 => huffman_ins_v2_pass_vert_code_3(0),
7903 
      I2 => huffman_ins_v2_hor_code(0),
7904 
      O => run_len_code_o(0)
7905 
    );
7906 
  fax4_ins_pix_changed_mux00011 : LUT3
7907 
    generic map(
7908 
      INIT => X"28"
7909 
    )
7910 
    port map (
7911 
      I0 => rsync_i,
7912 
      I1 => pix_i,
7913 
      I2 => fax4_ins_pix_prev_1321,
7914 
      O => fax4_ins_pix_changed_mux0001
7915 
    );
7916 
  fax4_ins_fifo_out_prev2_valid_mux00011 : LUT3
7917 
    generic map(
7918 
      INIT => X"82"
7919 
    )
7920 
    port map (
7921 
      I0 => fax4_ins_fifo_out_prev1_valid_1240,
7922 
      I1 => fax4_ins_fifo_sel_prev_1279,
7923 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
7924 
      O => fax4_ins_fifo_out_prev2_valid_mux0001
7925 
    );
7926 
  fax4_ins_fifo_out_prev1_valid_mux00011 : LUT4
7927 
    generic map(
7928 
      INIT => X"9810"
7929 
    )
7930 
    port map (
7931 
      I0 => fax4_ins_fifo_sel_prev_1279,
7932 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
7933 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid1_o_698,
7934 
      I3 => fax4_ins_FIFO1_multi_read_ins_valid1_o_456,
7935 
      O => fax4_ins_fifo_out_prev1_valid_mux0001
7936 
    );
7937 
  fax4_ins_counter_xy_v2_ins_frame_valid_and00011 : LUT2
7938 
    generic map(
7939 
      INIT => X"2"
7940 
    )
7941 
    port map (
7942 
      I0 => fax4_ins_counter_xy_v2_ins_counter_y_ins_overflow_o_1204,
7943 
      I1 => fax4_ins_counter_xy_v2_ins_cnt_y_overflow_prev_1104,
7944 
      O => fax4_ins_counter_xy_v2_ins_frame_valid_and0001
7945 
    );
7946 
  fax4_ins_counter_xy_v2_ins_line_valid_and00001 : LUT2
7947 
    generic map(
7948 
      INIT => X"2"
7949 
    )
7950 
    port map (
7951 
      I0 => rsync_i,
7952 
      I1 => fax4_ins_counter_xy_v2_ins_rsync_i_prev_1212,
7953 
      O => fax4_ins_counter_xy_v2_ins_line_valid_and0000
7954 
    );
7955 
  fax4_ins_counter_xy_v2_ins_frame_valid_and00001 : LUT2
7956 
    generic map(
7957 
      INIT => X"2"
7958 
    )
7959 
    port map (
7960 
      I0 => fsync_i,
7961 
      I1 => fax4_ins_counter_xy_v2_ins_fsync_i_prev_1209,
7962 
      O => fax4_ins_counter_xy_v2_ins_frame_valid_and0000
7963 
    );
7964 
  fax4_ins_counter_xy_v2_ins_cnt_y_reset_or00001 : LUT4
7965 
    generic map(
7966 
      INIT => X"AEFF"
7967 
    )
7968 
    port map (
7969 
      I0 => fax4_ins_counter_xy_v2_ins_cnt_y_overflow_prev_1104,
7970 
      I1 => fsync_i,
7971 
      I2 => fax4_ins_counter_xy_v2_ins_fsync_i_prev_1209,
7972 
      I3 => fax4_ins_counter_xy_v2_ins_counter_y_ins_overflow_o_1204,
7973 
      O => fax4_ins_counter_xy_v2_ins_cnt_y_reset_or0000
7974 
    );
7975 
  fax4_ins_counter_xy_v2_ins_cnt_x_reset_or00001 : LUT4
7976 
    generic map(
7977 
      INIT => X"22F2"
7978 
    )
7979 
    port map (
7980 
      I0 => fax4_ins_counter_xy_v2_ins_rsync_i_prev_1212,
7981 
      I1 => rsync_i,
7982 
      I2 => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_1157,
7983 
      I3 => fax4_ins_counter_xy_v2_ins_cnt_x_overflow_prev_1101,
7984 
      O => fax4_ins_counter_xy_v2_ins_cnt_x_reset_or0000
7985 
    );
7986 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_overflow_o_mux00021 : LUT2
7987 
    generic map(
7988 
      INIT => X"8"
7989 
    )
7990 
    port map (
7991 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
7992 
      I1 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000,
7993 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_overflow_o_mux0002
7994 
    );
7995 
  fax4_ins_counter_xy_v2_ins_cnt_x_en1 : LUT2
7996 
    generic map(
7997 
      INIT => X"8"
7998 
    )
7999 
    port map (
8000 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
8001 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
8002 
      O => fax4_ins_counter_xy_v2_ins_cnt_x_en
8003 
    );
8004 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge00001 : LUT4
8005 
    generic map(
8006 
      INIT => X"8000"
8007 
    )
8008 
    port map (
8009 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(7),
8010 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(8),
8011 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(5),
8012 
      I3 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(6),
8013 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000
8014 
    );
8015 
  huffman_ins_v2_hor_code_width_mux0001_1_1 : LUT4
8016 
    generic map(
8017 
      INIT => X"EB41"
8018 
    )
8019 
    port map (
8020 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
8021 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
8022 
      I2 => huffman_ins_v2_mux_code_white_width(1),
8023 
      I3 => huffman_ins_v2_mux_code_black_width(1),
8024 
      O => huffman_ins_v2_hor_code_width_mux0001(1)
8025 
    );
8026 
  fax4_ins_state_FSM_Out151 : LUT3
8027 
    generic map(
8028 
      INIT => X"FE"
8029 
    )
8030 
    port map (
8031 
      I0 => fax4_ins_state_FSM_FFd11_1325,
8032 
      I1 => fax4_ins_state_FSM_FFd3_1329,
8033 
      I2 => fax4_ins_state_FSM_FFd9_1341,
8034 
      O => fax4_ins_pix_change_detector_reset
8035 
    );
8036 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000_8_1 : LUT2
8037 
    generic map(
8038 
      INIT => X"E"
8039 
    )
8040 
    port map (
8041 
      I0 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000,
8042 
      I1 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(0),
8043 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(8)
8044 
    );
8045 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000_9_1 : LUT2
8046 
    generic map(
8047 
      INIT => X"E"
8048 
    )
8049 
    port map (
8050 
      I0 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000,
8051 
      I1 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(0),
8052 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(9)
8053 
    );
8054 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_01 : LUT2
8055 
    generic map(
8056 
      INIT => X"2"
8057 
    )
8058 
    port map (
8059 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result_0_1,
8060 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000,
8061 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_0
8062 
    );
8063 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_01 : LUT2
8064 
    generic map(
8065 
      INIT => X"2"
8066 
    )
8067 
    port map (
8068 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result(0),
8069 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000,
8070 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_0
8071 
    );
8072 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_01 : LUT2
8073 
    generic map(
8074 
      INIT => X"2"
8075 
    )
8076 
    port map (
8077 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result_0_1,
8078 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000,
8079 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_0
8080 
    );
8081 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_01 : LUT2
8082 
    generic map(
8083 
      INIT => X"2"
8084 
    )
8085 
    port map (
8086 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result(0),
8087 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000,
8088 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_0
8089 
    );
8090 
  fax4_ins_state_FSM_FFd6_In11 : LUT4
8091 
    generic map(
8092 
      INIT => X"FFFE"
8093 
    )
8094 
    port map (
8095 
      I0 => fax4_ins_state_FSM_FFd10_1323,
8096 
      I1 => fax4_ins_state_FSM_FFd2_1327,
8097 
      I2 => fax4_ins_state_FSM_FFd5_1333,
8098 
      I3 => fax4_ins_state_FSM_FFd6_1336,
8099 
      O => fax4_ins_load_a1_or0000
8100 
    );
8101 
  huffman_ins_v2_hor_code_width_mux0001_2_1 : LUT4
8102 
    generic map(
8103 
      INIT => X"BE14"
8104 
    )
8105 
    port map (
8106 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
8107 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
8108 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(1),
8109 
      I3 => huffman_ins_v2_mux_code_black_width(2),
8110 
      O => huffman_ins_v2_hor_code_width_mux0001(2)
8111 
    );
8112 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge00001_SW0 : LUT3
8113 
    generic map(
8114 
      INIT => X"80"
8115 
    )
8116 
    port map (
8117 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
8118 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
8119 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
8120 
      O => N2
8121 
    );
8122 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge00001 : LUT4
8123 
    generic map(
8124 
      INIT => X"AA80"
8125 
    )
8126 
    port map (
8127 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
8128 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
8129 
      I2 => N2,
8130 
      I3 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
8131 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000
8132 
    );
8133 
  fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq00007 : LUT4
8134 
    generic map(
8135 
      INIT => X"2000"
8136 
    )
8137 
    port map (
8138 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(6),
8139 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos(4),
8140 
      I2 => fax4_ins_FIFO2_multi_read_ins_write_pos(5),
8141 
      I3 => fax4_ins_FIFO2_multi_read_ins_write_pos(7),
8142 
      O => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq00007_715
8143 
    );
8144 
  fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq000015 : LUT4
8145 
    generic map(
8146 
      INIT => X"8000"
8147 
    )
8148 
    port map (
8149 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(3),
8150 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos(2),
8151 
      I2 => fax4_ins_FIFO2_multi_read_ins_write_pos(1),
8152 
      I3 => fax4_ins_FIFO2_multi_read_ins_write_pos(0),
8153 
      O => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq000015_714
8154 
    );
8155 
  fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq00007 : LUT4
8156 
    generic map(
8157 
      INIT => X"2000"
8158 
    )
8159 
    port map (
8160 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(6),
8161 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos(4),
8162 
      I2 => fax4_ins_FIFO2_multi_read_ins_read_pos(5),
8163 
      I3 => fax4_ins_FIFO2_multi_read_ins_read_pos(7),
8164 
      O => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq00007_682
8165 
    );
8166 
  fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq000015 : LUT4
8167 
    generic map(
8168 
      INIT => X"8000"
8169 
    )
8170 
    port map (
8171 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(3),
8172 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos(2),
8173 
      I2 => fax4_ins_FIFO2_multi_read_ins_read_pos(1),
8174 
      I3 => fax4_ins_FIFO2_multi_read_ins_read_pos(0),
8175 
      O => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq000015_681
8176 
    );
8177 
  fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq00007 : LUT4
8178 
    generic map(
8179 
      INIT => X"2000"
8180 
    )
8181 
    port map (
8182 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(6),
8183 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos(4),
8184 
      I2 => fax4_ins_FIFO1_multi_read_ins_write_pos(5),
8185 
      I3 => fax4_ins_FIFO1_multi_read_ins_write_pos(7),
8186 
      O => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq00007_472
8187 
    );
8188 
  fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq000015 : LUT4
8189 
    generic map(
8190 
      INIT => X"8000"
8191 
    )
8192 
    port map (
8193 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(3),
8194 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos(2),
8195 
      I2 => fax4_ins_FIFO1_multi_read_ins_write_pos(1),
8196 
      I3 => fax4_ins_FIFO1_multi_read_ins_write_pos(0),
8197 
      O => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq000015_471
8198 
    );
8199 
  fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq00007 : LUT4
8200 
    generic map(
8201 
      INIT => X"2000"
8202 
    )
8203 
    port map (
8204 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(6),
8205 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos(4),
8206 
      I2 => fax4_ins_FIFO1_multi_read_ins_read_pos(5),
8207 
      I3 => fax4_ins_FIFO1_multi_read_ins_read_pos(7),
8208 
      O => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq00007_440
8209 
    );
8210 
  fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq000015 : LUT4
8211 
    generic map(
8212 
      INIT => X"8000"
8213 
    )
8214 
    port map (
8215 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(3),
8216 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos(2),
8217 
      I2 => fax4_ins_FIFO1_multi_read_ins_read_pos(1),
8218 
      I3 => fax4_ins_FIFO1_multi_read_ins_read_pos(0),
8219 
      O => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq000015_439
8220 
    );
8221 
  huffman_ins_v2_Mrom_run_length_i_rom000051 : LUT4
8222 
    generic map(
8223 
      INIT => X"6AAA"
8224 
    )
8225 
    port map (
8226 
      I0 => fax4_ins_mode_indicator_o(3),
8227 
      I1 => fax4_ins_mode_indicator_o(1),
8228 
      I2 => fax4_ins_mode_indicator_o(0),
8229 
      I3 => fax4_ins_mode_indicator_o(2),
8230 
      O => huffman_ins_v2_Mrom_run_length_i_rom00005
8231 
    );
8232 
  huffman_ins_v2_Mrom_run_length_i_rom000031 : LUT4
8233 
    generic map(
8234 
      INIT => X"9501"
8235 
    )
8236 
    port map (
8237 
      I0 => fax4_ins_mode_indicator_o(3),
8238 
      I1 => fax4_ins_mode_indicator_o(0),
8239 
      I2 => fax4_ins_mode_indicator_o(1),
8240 
      I3 => fax4_ins_mode_indicator_o(2),
8241 
      O => huffman_ins_v2_Mrom_run_length_i_rom00003
8242 
    );
8243 
  huffman_ins_v2_Mrom_run_length_i_rom000021 : LUT4
8244 
    generic map(
8245 
      INIT => X"8078"
8246 
    )
8247 
    port map (
8248 
      I0 => fax4_ins_mode_indicator_o(2),
8249 
      I1 => fax4_ins_mode_indicator_o(0),
8250 
      I2 => fax4_ins_mode_indicator_o(1),
8251 
      I3 => fax4_ins_mode_indicator_o(3),
8252 
      O => huffman_ins_v2_Mrom_run_length_i_rom00002
8253 
    );
8254 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000_7_1 : LUT2
8255 
    generic map(
8256 
      INIT => X"2"
8257 
    )
8258 
    port map (
8259 
      I0 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(1),
8260 
      I1 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000,
8261 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(7)
8262 
    );
8263 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000_8_1 : LUT2
8264 
    generic map(
8265 
      INIT => X"2"
8266 
    )
8267 
    port map (
8268 
      I0 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(1),
8269 
      I1 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000,
8270 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(8)
8271 
    );
8272 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_11 : LUT2
8273 
    generic map(
8274 
      INIT => X"2"
8275 
    )
8276 
    port map (
8277 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result_1_1,
8278 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000,
8279 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_1
8280 
    );
8281 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_11 : LUT2
8282 
    generic map(
8283 
      INIT => X"2"
8284 
    )
8285 
    port map (
8286 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result(1),
8287 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000,
8288 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_1
8289 
    );
8290 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_11 : LUT2
8291 
    generic map(
8292 
      INIT => X"2"
8293 
    )
8294 
    port map (
8295 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result_1_1,
8296 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000,
8297 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_1
8298 
    );
8299 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_11 : LUT2
8300 
    generic map(
8301 
      INIT => X"2"
8302 
    )
8303 
    port map (
8304 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result(1),
8305 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000,
8306 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_1
8307 
    );
8308 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000_6_1 : LUT2
8309 
    generic map(
8310 
      INIT => X"2"
8311 
    )
8312 
    port map (
8313 
      I0 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(2),
8314 
      I1 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000,
8315 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(6)
8316 
    );
8317 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000_7_1 : LUT2
8318 
    generic map(
8319 
      INIT => X"2"
8320 
    )
8321 
    port map (
8322 
      I0 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(2),
8323 
      I1 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000,
8324 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(7)
8325 
    );
8326 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_21 : LUT2
8327 
    generic map(
8328 
      INIT => X"2"
8329 
    )
8330 
    port map (
8331 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result_2_1,
8332 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000,
8333 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_2
8334 
    );
8335 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_21 : LUT2
8336 
    generic map(
8337 
      INIT => X"2"
8338 
    )
8339 
    port map (
8340 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result(2),
8341 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000,
8342 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_2
8343 
    );
8344 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_21 : LUT2
8345 
    generic map(
8346 
      INIT => X"2"
8347 
    )
8348 
    port map (
8349 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result_2_1,
8350 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000,
8351 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_2
8352 
    );
8353 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_21 : LUT2
8354 
    generic map(
8355 
      INIT => X"2"
8356 
    )
8357 
    port map (
8358 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result(2),
8359 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000,
8360 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_2
8361 
    );
8362 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000_5_1 : LUT2
8363 
    generic map(
8364 
      INIT => X"2"
8365 
    )
8366 
    port map (
8367 
      I0 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(3),
8368 
      I1 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000,
8369 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(5)
8370 
    );
8371 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000_6_1 : LUT2
8372 
    generic map(
8373 
      INIT => X"2"
8374 
    )
8375 
    port map (
8376 
      I0 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(3),
8377 
      I1 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000,
8378 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(6)
8379 
    );
8380 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_31 : LUT2
8381 
    generic map(
8382 
      INIT => X"2"
8383 
    )
8384 
    port map (
8385 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result_3_1,
8386 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000,
8387 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_3
8388 
    );
8389 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_31 : LUT2
8390 
    generic map(
8391 
      INIT => X"2"
8392 
    )
8393 
    port map (
8394 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result(3),
8395 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000,
8396 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_3
8397 
    );
8398 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_31 : LUT2
8399 
    generic map(
8400 
      INIT => X"2"
8401 
    )
8402 
    port map (
8403 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result_3_1,
8404 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000,
8405 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_3
8406 
    );
8407 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_31 : LUT2
8408 
    generic map(
8409 
      INIT => X"2"
8410 
    )
8411 
    port map (
8412 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result(3),
8413 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000,
8414 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_3
8415 
    );
8416 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000_4_1 : LUT2
8417 
    generic map(
8418 
      INIT => X"2"
8419 
    )
8420 
    port map (
8421 
      I0 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(4),
8422 
      I1 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000,
8423 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(4)
8424 
    );
8425 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000_5_1 : LUT2
8426 
    generic map(
8427 
      INIT => X"2"
8428 
    )
8429 
    port map (
8430 
      I0 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(4),
8431 
      I1 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000,
8432 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(5)
8433 
    );
8434 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_41 : LUT2
8435 
    generic map(
8436 
      INIT => X"2"
8437 
    )
8438 
    port map (
8439 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result_4_1,
8440 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000,
8441 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_4
8442 
    );
8443 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_41 : LUT2
8444 
    generic map(
8445 
      INIT => X"2"
8446 
    )
8447 
    port map (
8448 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result(4),
8449 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000,
8450 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_4
8451 
    );
8452 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_41 : LUT2
8453 
    generic map(
8454 
      INIT => X"2"
8455 
    )
8456 
    port map (
8457 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result_4_1,
8458 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000,
8459 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_4
8460 
    );
8461 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_41 : LUT2
8462 
    generic map(
8463 
      INIT => X"2"
8464 
    )
8465 
    port map (
8466 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result(4),
8467 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000,
8468 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_4
8469 
    );
8470 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000_3_1 : LUT2
8471 
    generic map(
8472 
      INIT => X"2"
8473 
    )
8474 
    port map (
8475 
      I0 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(5),
8476 
      I1 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000,
8477 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(3)
8478 
    );
8479 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000_4_1 : LUT2
8480 
    generic map(
8481 
      INIT => X"2"
8482 
    )
8483 
    port map (
8484 
      I0 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(5),
8485 
      I1 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000,
8486 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(4)
8487 
    );
8488 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_51 : LUT2
8489 
    generic map(
8490 
      INIT => X"2"
8491 
    )
8492 
    port map (
8493 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result_5_1,
8494 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000,
8495 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_5
8496 
    );
8497 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_51 : LUT2
8498 
    generic map(
8499 
      INIT => X"2"
8500 
    )
8501 
    port map (
8502 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result(5),
8503 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000,
8504 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_5
8505 
    );
8506 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_51 : LUT2
8507 
    generic map(
8508 
      INIT => X"2"
8509 
    )
8510 
    port map (
8511 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result_5_1,
8512 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000,
8513 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_5
8514 
    );
8515 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_51 : LUT2
8516 
    generic map(
8517 
      INIT => X"2"
8518 
    )
8519 
    port map (
8520 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result(5),
8521 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000,
8522 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_5
8523 
    );
8524 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000_2_1 : LUT2
8525 
    generic map(
8526 
      INIT => X"2"
8527 
    )
8528 
    port map (
8529 
      I0 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(6),
8530 
      I1 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000,
8531 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(2)
8532 
    );
8533 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000_3_1 : LUT2
8534 
    generic map(
8535 
      INIT => X"2"
8536 
    )
8537 
    port map (
8538 
      I0 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(6),
8539 
      I1 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000,
8540 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(3)
8541 
    );
8542 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_61 : LUT2
8543 
    generic map(
8544 
      INIT => X"2"
8545 
    )
8546 
    port map (
8547 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result_6_1,
8548 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000,
8549 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_6
8550 
    );
8551 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_61 : LUT2
8552 
    generic map(
8553 
      INIT => X"2"
8554 
    )
8555 
    port map (
8556 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result(6),
8557 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000,
8558 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_6
8559 
    );
8560 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_61 : LUT2
8561 
    generic map(
8562 
      INIT => X"2"
8563 
    )
8564 
    port map (
8565 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result_6_1,
8566 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000,
8567 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_6
8568 
    );
8569 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_61 : LUT2
8570 
    generic map(
8571 
      INIT => X"2"
8572 
    )
8573 
    port map (
8574 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result(6),
8575 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000,
8576 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_6
8577 
    );
8578 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000_1_1 : LUT2
8579 
    generic map(
8580 
      INIT => X"2"
8581 
    )
8582 
    port map (
8583 
      I0 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(7),
8584 
      I1 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000,
8585 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(1)
8586 
    );
8587 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000_2_1 : LUT2
8588 
    generic map(
8589 
      INIT => X"2"
8590 
    )
8591 
    port map (
8592 
      I0 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(7),
8593 
      I1 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000,
8594 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(2)
8595 
    );
8596 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_71 : LUT2
8597 
    generic map(
8598 
      INIT => X"2"
8599 
    )
8600 
    port map (
8601 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result_7_1,
8602 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000,
8603 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_7
8604 
    );
8605 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_71 : LUT2
8606 
    generic map(
8607 
      INIT => X"2"
8608 
    )
8609 
    port map (
8610 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result(7),
8611 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000,
8612 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_7
8613 
    );
8614 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_71 : LUT2
8615 
    generic map(
8616 
      INIT => X"2"
8617 
    )
8618 
    port map (
8619 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result_7_1,
8620 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000,
8621 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_7
8622 
    );
8623 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_71 : LUT2
8624 
    generic map(
8625 
      INIT => X"2"
8626 
    )
8627 
    port map (
8628 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result(7),
8629 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000,
8630 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_7
8631 
    );
8632 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000_0_1 : LUT2
8633 
    generic map(
8634 
      INIT => X"2"
8635 
    )
8636 
    port map (
8637 
      I0 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_addsub0000(8),
8638 
      I1 => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_cmp_ge0000,
8639 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt_mux0000(0)
8640 
    );
8641 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000_1_1 : LUT2
8642 
    generic map(
8643 
      INIT => X"2"
8644 
    )
8645 
    port map (
8646 
      I0 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(8),
8647 
      I1 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000,
8648 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(1)
8649 
    );
8650 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_81 : LUT2
8651 
    generic map(
8652 
      INIT => X"2"
8653 
    )
8654 
    port map (
8655 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result_8_1,
8656 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000,
8657 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_8
8658 
    );
8659 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_81 : LUT2
8660 
    generic map(
8661 
      INIT => X"2"
8662 
    )
8663 
    port map (
8664 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result(8),
8665 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000,
8666 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_8
8667 
    );
8668 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_81 : LUT2
8669 
    generic map(
8670 
      INIT => X"2"
8671 
    )
8672 
    port map (
8673 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result_8_1,
8674 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000,
8675 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_8
8676 
    );
8677 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_81 : LUT2
8678 
    generic map(
8679 
      INIT => X"2"
8680 
    )
8681 
    port map (
8682 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result(8),
8683 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000,
8684 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_8
8685 
    );
8686 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000_0_1 : LUT2
8687 
    generic map(
8688 
      INIT => X"2"
8689 
    )
8690 
    port map (
8691 
      I0 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_addsub0000(9),
8692 
      I1 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000,
8693 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_mux0000(0)
8694 
    );
8695 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_91 : LUT2
8696 
    generic map(
8697 
      INIT => X"2"
8698 
    )
8699 
    port map (
8700 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result_9_1,
8701 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000,
8702 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_eqn_9
8703 
    );
8704 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_91 : LUT2
8705 
    generic map(
8706 
      INIT => X"2"
8707 
    )
8708 
    port map (
8709 
      I0 => fax4_ins_FIFO2_multi_read_ins_Result(9),
8710 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000,
8711 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_eqn_9
8712 
    );
8713 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_91 : LUT2
8714 
    generic map(
8715 
      INIT => X"2"
8716 
    )
8717 
    port map (
8718 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result_9_1,
8719 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000,
8720 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_eqn_9
8721 
    );
8722 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_91 : LUT2
8723 
    generic map(
8724 
      INIT => X"2"
8725 
    )
8726 
    port map (
8727 
      I0 => fax4_ins_FIFO1_multi_read_ins_Result(9),
8728 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000,
8729 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_eqn_9
8730 
    );
8731 
  huffman_ins_v2_hor_code_10_mux0003151 : LUT3
8732 
    generic map(
8733 
      INIT => X"10"
8734 
    )
8735 
    port map (
8736 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
8737 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
8738 
      I2 => huffman_ins_v2_mux_code_white_width(1),
8739 
      O => huffman_ins_v2_N232
8740 
    );
8741 
  huffman_ins_v2_hor_code_width_mux0001_3_1 : LUT4
8742 
    generic map(
8743 
      INIT => X"EB41"
8744 
    )
8745 
    port map (
8746 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
8747 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
8748 
      I2 => huffman_ins_v2_N170,
8749 
      I3 => huffman_ins_v2_mux_code_black_width(3),
8750 
      O => huffman_ins_v2_hor_code_width_mux0001(3)
8751 
    );
8752 
  huffman_ins_v2_hor_code_8_mux0003111 : LUT3
8753 
    generic map(
8754 
      INIT => X"08"
8755 
    )
8756 
    port map (
8757 
      I0 => huffman_ins_v2_mux_code_black_width(3),
8758 
      I1 => huffman_ins_v2_mux_code_black_width(1),
8759 
      I2 => huffman_ins_v2_mux_code_black_width(4),
8760 
      O => huffman_ins_v2_N87
8761 
    );
8762 
  huffman_ins_v2_code_white_3_mux00001 : LUT3
8763 
    generic map(
8764 
      INIT => X"E4"
8765 
    )
8766 
    port map (
8767 
      I0 => huffman_ins_v2_code_white_8_or0000,
8768 
      I1 => huffman_ins_v2_ter_white_code(3),
8769 
      I2 => huffman_ins_v2_code_white(3),
8770 
      O => huffman_ins_v2_code_white_3_mux0000
8771 
    );
8772 
  huffman_ins_v2_code_white_2_mux00001 : LUT3
8773 
    generic map(
8774 
      INIT => X"E4"
8775 
    )
8776 
    port map (
8777 
      I0 => huffman_ins_v2_code_white_8_or0000,
8778 
      I1 => huffman_ins_v2_ter_white_code(2),
8779 
      I2 => huffman_ins_v2_code_white(2),
8780 
      O => huffman_ins_v2_code_white_2_mux0000
8781 
    );
8782 
  huffman_ins_v2_code_white_1_mux00001 : LUT3
8783 
    generic map(
8784 
      INIT => X"E4"
8785 
    )
8786 
    port map (
8787 
      I0 => huffman_ins_v2_code_white_8_or0000,
8788 
      I1 => huffman_ins_v2_ter_white_code(1),
8789 
      I2 => huffman_ins_v2_code_white(1),
8790 
      O => huffman_ins_v2_code_white_1_mux0000
8791 
    );
8792 
  huffman_ins_v2_code_white_0_mux00001 : LUT3
8793 
    generic map(
8794 
      INIT => X"E4"
8795 
    )
8796 
    port map (
8797 
      I0 => huffman_ins_v2_code_white_8_or0000,
8798 
      I1 => huffman_ins_v2_ter_white_code(0),
8799 
      I2 => huffman_ins_v2_code_white(0),
8800 
      O => huffman_ins_v2_code_white_0_mux0000
8801 
    );
8802 
  huffman_ins_v2_code_white_16_mux00001 : LUT4
8803 
    generic map(
8804 
      INIT => X"F888"
8805 
    )
8806 
    port map (
8807 
      I0 => huffman_ins_v2_code_white_8_cmp_eq0004,
8808 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(8),
8809 
      I2 => huffman_ins_v2_code_white_8_or0000,
8810 
      I3 => huffman_ins_v2_code_white(16),
8811 
      O => huffman_ins_v2_code_white_16_mux0000
8812 
    );
8813 
  huffman_ins_v2_hor_code_14_mux0003281 : LUT2
8814 
    generic map(
8815 
      INIT => X"7"
8816 
    )
8817 
    port map (
8818 
      I0 => huffman_ins_v2_code_white_width(2),
8819 
      I1 => huffman_ins_v2_code_white_width(3),
8820 
      O => huffman_ins_v2_N223
8821 
    );
8822 
  huffman_ins_v2_hor_code_14_mux0003271 : LUT2
8823 
    generic map(
8824 
      INIT => X"7"
8825 
    )
8826 
    port map (
8827 
      I0 => huffman_ins_v2_code_black_width(2),
8828 
      I1 => huffman_ins_v2_code_black_width(3),
8829 
      O => huffman_ins_v2_N203
8830 
    );
8831 
  huffman_ins_v2_hor_code_14_mux0003221 : LUT2
8832 
    generic map(
8833 
      INIT => X"1"
8834 
    )
8835 
    port map (
8836 
      I0 => huffman_ins_v2_a0_value_2_1510,
8837 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
8838 
      O => huffman_ins_v2_N103
8839 
    );
8840 
  huffman_ins_v2_hor_code_10_mux000381 : LUT2
8841 
    generic map(
8842 
      INIT => X"8"
8843 
    )
8844 
    port map (
8845 
      I0 => huffman_ins_v2_a0_value_2_1510,
8846 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
8847 
      O => huffman_ins_v2_N107
8848 
    );
8849 
  huffman_ins_v2_hor_code_14_mux000311 : LUT2
8850 
    generic map(
8851 
      INIT => X"9"
8852 
    )
8853 
    port map (
8854 
      I0 => huffman_ins_v2_a0_value_2_1510,
8855 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
8856 
      O => huffman_ins_v2_N11
8857 
    );
8858 
  huffman_ins_v2_code_white_4_mux000016 : LUT3
8859 
    generic map(
8860 
      INIT => X"10"
8861 
    )
8862 
    port map (
8863 
      I0 => huffman_ins_v2_codetab_ter_white_width(1),
8864 
      I1 => huffman_ins_v2_codetab_ter_white_width(3),
8865 
      I2 => huffman_ins_v2_codetab_ter_white_width(2),
8866 
      O => huffman_ins_v2_code_white_4_mux000016_1765
8867 
    );
8868 
  huffman_ins_v2_code_white_4_mux000039 : LUT3
8869 
    generic map(
8870 
      INIT => X"C8"
8871 
    )
8872 
    port map (
8873 
      I0 => huffman_ins_v2_code_white_8_cmp_eq0004,
8874 
      I1 => huffman_ins_v2_ter_white_code(4),
8875 
      I2 => huffman_ins_v2_N239,
8876 
      O => huffman_ins_v2_code_white_4_mux000039_1769
8877 
    );
8878 
  huffman_ins_v2_code_white_5_mux000039 : LUT3
8879 
    generic map(
8880 
      INIT => X"C8"
8881 
    )
8882 
    port map (
8883 
      I0 => huffman_ins_v2_code_white_8_cmp_eq0004,
8884 
      I1 => huffman_ins_v2_ter_white_code(5),
8885 
      I2 => huffman_ins_v2_N239,
8886 
      O => huffman_ins_v2_code_white_5_mux000039_1774
8887 
    );
8888 
  huffman_ins_v2_horizontal_mode_1_cmp_eq000111 : LUT3
8889 
    generic map(
8890 
      INIT => X"10"
8891 
    )
8892 
    port map (
8893 
      I0 => fax4_ins_mode_indicator_o(1),
8894 
      I1 => fax4_ins_mode_indicator_o(2),
8895 
      I2 => fax4_ins_mode_indicator_o(3),
8896 
      O => huffman_ins_v2_horizontal_mode_1_or0000
8897 
    );
8898 
  huffman_ins_v2_hor_code_0_mux0003111 : LUT4
8899 
    generic map(
8900 
      INIT => X"FFFE"
8901 
    )
8902 
    port map (
8903 
      I0 => huffman_ins_v2_mux_code_black_width(1),
8904 
      I1 => huffman_ins_v2_mux_code_black_width(0),
8905 
      I2 => huffman_ins_v2_mux_code_black_width(3),
8906 
      I3 => huffman_ins_v2_mux_code_black_width(2),
8907 
      O => huffman_ins_v2_N89
8908 
    );
8909 
  huffman_ins_v2_hor_code_23_mux00039 : LUT4
8910 
    generic map(
8911 
      INIT => X"F020"
8912 
    )
8913 
    port map (
8914 
      I0 => huffman_ins_v2_N244,
8915 
      I1 => huffman_ins_v2_a0_value_2_1510,
8916 
      I2 => huffman_ins_v2_code_black(23),
8917 
      I3 => huffman_ins_v2_N228,
8918 
      O => huffman_ins_v2_hor_code_23_mux00039_1971
8919 
    );
8920 
  huffman_ins_v2_hor_code_23_mux000322 : LUT4
8921 
    generic map(
8922 
      INIT => X"1000"
8923 
    )
8924 
    port map (
8925 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
8926 
      I1 => huffman_ins_v2_hor_code_13_or0005,
8927 
      I2 => huffman_ins_v2_N102,
8928 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
8929 
      O => huffman_ins_v2_hor_code_23_mux000322_1968
8930 
    );
8931 
  huffman_ins_v2_hor_code_24_mux000312 : LUT4
8932 
    generic map(
8933 
      INIT => X"22A2"
8934 
    )
8935 
    port map (
8936 
      I0 => huffman_ins_v2_N244,
8937 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
8938 
      I2 => huffman_ins_v2_code_black(24),
8939 
      I3 => huffman_ins_v2_a0_value_2_1510,
8940 
      O => huffman_ins_v2_hor_code_24_mux000312_1973
8941 
    );
8942 
  huffman_ins_v2_hor_code_24_mux000348 : LUT3
8943 
    generic map(
8944 
      INIT => X"F1"
8945 
    )
8946 
    port map (
8947 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
8948 
      I1 => huffman_ins_v2_mux_code_white_width(1),
8949 
      I2 => huffman_ins_v2_N3,
8950 
      O => huffman_ins_v2_hor_code_24_mux000348_1976
8951 
    );
8952 
  huffman_ins_v2_hor_code_24_mux000371 : LUT4
8953 
    generic map(
8954 
      INIT => X"A820"
8955 
    )
8956 
    port map (
8957 
      I0 => huffman_ins_v2_hor_code(24),
8958 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
8959 
      I2 => huffman_ins_v2_hor_code_24_mux000348_1976,
8960 
      I3 => huffman_ins_v2_hor_code_24_mux000335_1975,
8961 
      O => huffman_ins_v2_hor_code_24_mux000371_1977
8962 
    );
8963 
  huffman_ins_v2_hor_code_15_mux0003211 : LUT4
8964 
    generic map(
8965 
      INIT => X"32FA"
8966 
    )
8967 
    port map (
8968 
      I0 => huffman_ins_v2_hor_code_15_mux00038_1893,
8969 
      I1 => huffman_ins_v2_mux_code_black_width(3),
8970 
      I2 => huffman_ins_v2_hor_code_15_mux00035_1888,
8971 
      I3 => huffman_ins_v2_N99,
8972 
      O => huffman_ins_v2_hor_code_15_mux000321
8973 
    );
8974 
  huffman_ins_v2_hor_code_15_mux0003122 : LUT4
8975 
    generic map(
8976 
      INIT => X"2822"
8977 
    )
8978 
    port map (
8979 
      I0 => huffman_ins_v2_hor_code(15),
8980 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
8981 
      I2 => huffman_ins_v2_N98,
8982 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(1),
8983 
      O => huffman_ins_v2_hor_code_15_mux0003122_1884
8984 
    );
8985 
  huffman_ins_v2_hor_code_14_mux00038 : LUT3
8986 
    generic map(
8987 
      INIT => X"1F"
8988 
    )
8989 
    port map (
8990 
      I0 => huffman_ins_v2_code_black_width(1),
8991 
      I1 => huffman_ins_v2_code_black_width(2),
8992 
      I2 => huffman_ins_v2_code_black_width(3),
8993 
      O => huffman_ins_v2_hor_code_14_mux00038_1882
8994 
    );
8995 
  huffman_ins_v2_hor_code_14_mux000327 : LUT3
8996 
    generic map(
8997 
      INIT => X"1F"
8998 
    )
8999 
    port map (
9000 
      I0 => huffman_ins_v2_code_white_width(1),
9001 
      I1 => huffman_ins_v2_code_white_width(2),
9002 
      I2 => huffman_ins_v2_code_white_width(3),
9003 
      O => huffman_ins_v2_hor_code_14_mux000327_1876
9004 
    );
9005 
  huffman_ins_v2_hor_code_14_mux0003139 : LUT4
9006 
    generic map(
9007 
      INIT => X"FFEA"
9008 
    )
9009 
    port map (
9010 
      I0 => huffman_ins_v2_hor_code_14_mux000343_1879,
9011 
      I1 => huffman_ins_v2_hor_code_14_mux000371_1880,
9012 
      I2 => huffman_ins_v2_hor_code_14_mux000379_1881,
9013 
      I3 => huffman_ins_v2_hor_code_14_mux0003126_1866,
9014 
      O => huffman_ins_v2_hor_code_14_mux0003139_1867
9015 
    );
9016 
  huffman_ins_v2_hor_code_14_mux0003186 : LUT4
9017 
    generic map(
9018 
      INIT => X"22F2"
9019 
    )
9020 
    port map (
9021 
      I0 => huffman_ins_v2_hor_code_14_mux0003155_1868,
9022 
      I1 => huffman_ins_v2_code_black_width(4),
9023 
      I2 => huffman_ins_v2_hor_code_14_mux0003173_1869,
9024 
      I3 => huffman_ins_v2_code_white_width(4),
9025 
      O => huffman_ins_v2_hor_code_14_mux0003186_1870
9026 
    );
9027 
  huffman_ins_v2_hor_code_14_mux0003227 : LUT4
9028 
    generic map(
9029 
      INIT => X"0F08"
9030 
    )
9031 
    port map (
9032 
      I0 => huffman_ins_v2_code_white_width(0),
9033 
      I1 => huffman_ins_v2_hor_code_14_mux0003203_1871,
9034 
      I2 => huffman_ins_v2_N223,
9035 
      I3 => huffman_ins_v2_hor_code_14_mux0003213_1872,
9036 
      O => huffman_ins_v2_hor_code_14_mux0003227_1873
9037 
    );
9038 
  huffman_ins_v2_hor_code_14_mux0003277 : LUT4
9039 
    generic map(
9040 
      INIT => X"0F08"
9041 
    )
9042 
    port map (
9043 
      I0 => huffman_ins_v2_code_black_width(0),
9044 
      I1 => huffman_ins_v2_hor_code_14_mux0003256_1874,
9045 
      I2 => huffman_ins_v2_N203,
9046 
      I3 => huffman_ins_v2_hor_code_14_mux0003264_1875,
9047 
      O => huffman_ins_v2_hor_code_14_mux0003277_1877
9048 
    );
9049 
  huffman_ins_v2_hor_code_14_mux0003301 : LUT4
9050 
    generic map(
9051 
      INIT => X"CCC8"
9052 
    )
9053 
    port map (
9054 
      I0 => huffman_ins_v2_hor_code_14_mux0003186_1870,
9055 
      I1 => huffman_ins_v2_hor_code(14),
9056 
      I2 => huffman_ins_v2_hor_code_14_mux0003227_1873,
9057 
      I3 => huffman_ins_v2_hor_code_14_mux0003277_1877,
9058 
      O => huffman_ins_v2_hor_code_14_mux0003301_1878
9059 
    );
9060 
  huffman_ins_v2_code_white_8_cmp_eq00041 : LUT4
9061 
    generic map(
9062 
      INIT => X"0010"
9063 
    )
9064 
    port map (
9065 
      I0 => huffman_ins_v2_codetab_ter_white_width(1),
9066 
      I1 => huffman_ins_v2_codetab_ter_white_width(0),
9067 
      I2 => huffman_ins_v2_codetab_ter_white_width(3),
9068 
      I3 => huffman_ins_v2_codetab_ter_white_width(2),
9069 
      O => huffman_ins_v2_code_white_8_cmp_eq0004
9070 
    );
9071 
  huffman_ins_v2_code_white_8_cmp_eq00011 : LUT4
9072 
    generic map(
9073 
      INIT => X"1000"
9074 
    )
9075 
    port map (
9076 
      I0 => huffman_ins_v2_codetab_ter_white_width(1),
9077 
      I1 => huffman_ins_v2_codetab_ter_white_width(3),
9078 
      I2 => huffman_ins_v2_codetab_ter_white_width(2),
9079 
      I3 => huffman_ins_v2_codetab_ter_white_width(0),
9080 
      O => huffman_ins_v2_code_white_8_cmp_eq0001
9081 
    );
9082 
  huffman_ins_v2_code_white_15_mux0000_SW0 : LUT4
9083 
    generic map(
9084 
      INIT => X"F888"
9085 
    )
9086 
    port map (
9087 
      I0 => huffman_ins_v2_code_white_8_or0000,
9088 
      I1 => huffman_ins_v2_code_white(15),
9089 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(7),
9090 
      I3 => huffman_ins_v2_code_white_8_cmp_eq0004,
9091 
      O => N7
9092 
    );
9093 
  huffman_ins_v2_code_black_24_mux00001_SW0 : LUT2
9094 
    generic map(
9095 
      INIT => X"D"
9096 
    )
9097 
    port map (
9098 
      I0 => huffman_ins_v2_code_black(24),
9099 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
9100 
      O => N9
9101 
    );
9102 
  huffman_ins_v2_code_black_24_mux00001_SW1 : LUT4
9103 
    generic map(
9104 
      INIT => X"ABA8"
9105 
    )
9106 
    port map (
9107 
      I0 => huffman_ins_v2_code_black(24),
9108 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
9109 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
9110 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
9111 
      O => N10
9112 
    );
9113 
  huffman_ins_v2_code_black_24_mux00001 : LUT4
9114 
    generic map(
9115 
      INIT => X"8901"
9116 
    )
9117 
    port map (
9118 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
9119 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
9120 
      I2 => N9,
9121 
      I3 => N10,
9122 
      O => huffman_ins_v2_code_black_24_mux0000
9123 
    );
9124 
  fax4_ins_frame_finished_o1 : LUT2
9125 
    generic map(
9126 
      INIT => X"E"
9127 
    )
9128 
    port map (
9129 
      I0 => fax4_ins_state_FSM_FFd1_1322,
9130 
      I1 => fax4_ins_state_FSM_FFd4_1331,
9131 
      O => frame_finished_wire
9132 
    );
9133 
  huffman_ins_v2_hor_code_4_mux000331 : LUT3
9134 
    generic map(
9135 
      INIT => X"1F"
9136 
    )
9137 
    port map (
9138 
      I0 => huffman_ins_v2_mux_code_black_width(1),
9139 
      I1 => huffman_ins_v2_mux_code_black_width(0),
9140 
      I2 => huffman_ins_v2_mux_code_black_width(2),
9141 
      O => huffman_ins_v2_N71
9142 
    );
9143 
  huffman_ins_v2_hor_code_19_mux000311 : LUT4
9144 
    generic map(
9145 
      INIT => X"AEFF"
9146 
    )
9147 
    port map (
9148 
      I0 => huffman_ins_v2_N246,
9149 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(1),
9150 
      I2 => huffman_ins_v2_N98,
9151 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
9152 
      O => huffman_ins_v2_N3
9153 
    );
9154 
  huffman_ins_v2_hor_code_18_mux0003321 : LUT4
9155 
    generic map(
9156 
      INIT => X"AF2F"
9157 
    )
9158 
    port map (
9159 
      I0 => huffman_ins_v2_mux_code_black_width(3),
9160 
      I1 => huffman_ins_v2_N78,
9161 
      I2 => huffman_ins_v2_mux_code_black_width(4),
9162 
      I3 => huffman_ins_v2_N250,
9163 
      O => huffman_ins_v2_N186
9164 
    );
9165 
  huffman_ins_v2_hor_code_15_mux00032_SW0 : LUT3
9166 
    generic map(
9167 
      INIT => X"27"
9168 
    )
9169 
    port map (
9170 
      I0 => huffman_ins_v2_a0_value_2_1510,
9171 
      I1 => huffman_ins_v2_code_black_width(4),
9172 
      I2 => huffman_ins_v2_code_white_width(4),
9173 
      O => N12
9174 
    );
9175 
  huffman_ins_v2_hor_code_15_mux00032 : LUT3
9176 
    generic map(
9177 
      INIT => X"EA"
9178 
    )
9179 
    port map (
9180 
      I0 => N12,
9181 
      I1 => huffman_ins_v2_N251,
9182 
      I2 => huffman_ins_v2_mux_code_black_width(3),
9183 
      O => huffman_ins_v2_N65
9184 
    );
9185 
  huffman_ins_v2_hor_code_7_mux00035 : LUT4
9186 
    generic map(
9187 
      INIT => X"FFEA"
9188 
    )
9189 
    port map (
9190 
      I0 => huffman_ins_v2_N166,
9191 
      I1 => huffman_ins_v2_N100,
9192 
      I2 => huffman_ins_v2_N170,
9193 
      I3 => huffman_ins_v2_N105,
9194 
      O => huffman_ins_v2_hor_code_7_mux00035_2024
9195 
    );
9196 
  huffman_ins_v2_hor_code_7_mux000324 : LUT4
9197 
    generic map(
9198 
      INIT => X"0E04"
9199 
    )
9200 
    port map (
9201 
      I0 => huffman_ins_v2_a0_value_2_1510,
9202 
      I1 => huffman_ins_v2_code_black(7),
9203 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
9204 
      I3 => huffman_ins_v2_code_white(7),
9205 
      O => huffman_ins_v2_hor_code_7_mux000324_2022
9206 
    );
9207 
  huffman_ins_v2_hor_code_7_mux000356 : LUT4
9208 
    generic map(
9209 
      INIT => X"A820"
9210 
    )
9211 
    port map (
9212 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
9213 
      I1 => huffman_ins_v2_a0_value_2_1510,
9214 
      I2 => huffman_ins_v2_code_white(7),
9215 
      I3 => huffman_ins_v2_code_black(7),
9216 
      O => huffman_ins_v2_hor_code_7_mux000356_2025
9217 
    );
9218 
  huffman_ins_v2_hor_code_7_mux000370 : LUT3
9219 
    generic map(
9220 
      INIT => X"EA"
9221 
    )
9222 
    port map (
9223 
      I0 => huffman_ins_v2_hor_code_7_mux000368_2026,
9224 
      I1 => huffman_ins_v2_N48,
9225 
      I2 => huffman_ins_v2_hor_code_7_mux000356_2025,
9226 
      O => huffman_ins_v2_hor_code_7_mux000370_2027
9227 
    );
9228 
  huffman_ins_v2_hor_code_25_mux000342 : LUT4
9229 
    generic map(
9230 
      INIT => X"3F1F"
9231 
    )
9232 
    port map (
9233 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
9234 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
9235 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
9236 
      I3 => huffman_ins_v2_hor_code_13_or0005,
9237 
      O => huffman_ins_v2_hor_code_25_mux000342_1981
9238 
    );
9239 
  huffman_ins_v2_hor_code_11_mux000338 : LUT4
9240 
    generic map(
9241 
      INIT => X"FFFE"
9242 
    )
9243 
    port map (
9244 
      I0 => huffman_ins_v2_N166,
9245 
      I1 => huffman_ins_v2_N105,
9246 
      I2 => huffman_ins_v2_N100,
9247 
      I3 => huffman_ins_v2_hor_code_11_mux000321_1833,
9248 
      O => huffman_ins_v2_hor_code_11_mux000338_1834
9249 
    );
9250 
  huffman_ins_v2_hor_code_11_mux000373 : LUT4
9251 
    generic map(
9252 
      INIT => X"0E04"
9253 
    )
9254 
    port map (
9255 
      I0 => huffman_ins_v2_a0_value_2_1510,
9256 
      I1 => huffman_ins_v2_code_black(11),
9257 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
9258 
      I3 => huffman_ins_v2_code_white(11),
9259 
      O => huffman_ins_v2_hor_code_11_mux000373_1835
9260 
    );
9261 
  huffman_ins_v2_hor_code_11_mux00031211 : LUT4
9262 
    generic map(
9263 
      INIT => X"2000"
9264 
    )
9265 
    port map (
9266 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
9267 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
9268 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
9269 
      I3 => huffman_ins_v2_mux_code_white_width(1),
9270 
      O => huffman_ins_v2_hor_code_11_mux0003121
9271 
    );
9272 
  huffman_ins_v2_hor_code_17_mux000350 : LUT4
9273 
    generic map(
9274 
      INIT => X"1000"
9275 
    )
9276 
    port map (
9277 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
9278 
      I1 => huffman_ins_v2_N59,
9279 
      I2 => huffman_ins_v2_N102,
9280 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
9281 
      O => huffman_ins_v2_hor_code_17_mux000350_1909
9282 
    );
9283 
  huffman_ins_v2_hor_code_17_mux000353 : LUT4
9284 
    generic map(
9285 
      INIT => X"FFA8"
9286 
    )
9287 
    port map (
9288 
      I0 => huffman_ins_v2_code_black(17),
9289 
      I1 => huffman_ins_v2_hor_code_17_mux000316_1907,
9290 
      I2 => huffman_ins_v2_hor_code_17_mux000319_1908,
9291 
      I3 => huffman_ins_v2_hor_code_17_mux000350_1909,
9292 
      O => huffman_ins_v2_hor_code_17_mux000353_1910
9293 
    );
9294 
  huffman_ins_v2_hor_code_17_mux0003110 : LUT4
9295 
    generic map(
9296 
      INIT => X"313B"
9297 
    )
9298 
    port map (
9299 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
9300 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
9301 
      I2 => huffman_ins_v2_hor_code_13_or0005,
9302 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
9303 
      O => huffman_ins_v2_hor_code_17_mux0003110_1904
9304 
    );
9305 
  huffman_ins_v2_hor_code_10_mux000359 : LUT4
9306 
    generic map(
9307 
      INIT => X"A820"
9308 
    )
9309 
    port map (
9310 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
9311 
      I1 => huffman_ins_v2_a0_value_2_1510,
9312 
      I2 => huffman_ins_v2_code_white(10),
9313 
      I3 => huffman_ins_v2_code_black(10),
9314 
      O => huffman_ins_v2_hor_code_10_mux000359_1824
9315 
    );
9316 
  huffman_ins_v2_hor_code_10_mux000362 : LUT4
9317 
    generic map(
9318 
      INIT => X"AA80"
9319 
    )
9320 
    port map (
9321 
      I0 => huffman_ins_v2_hor_code_10_mux000359_1824,
9322 
      I1 => huffman_ins_v2_mux_code_black_width(0),
9323 
      I2 => huffman_ins_v2_N87,
9324 
      I3 => huffman_ins_v2_N62,
9325 
      O => huffman_ins_v2_hor_code_10_mux000362_1825
9326 
    );
9327 
  huffman_ins_v2_hor_code_10_mux000369 : LUT3
9328 
    generic map(
9329 
      INIT => X"EA"
9330 
    )
9331 
    port map (
9332 
      I0 => huffman_ins_v2_hor_code_10_mux000362_1825,
9333 
      I1 => huffman_ins_v2_hor_code(10),
9334 
      I2 => huffman_ins_v2_hor_code_10_mux000329_1823,
9335 
      O => huffman_ins_v2_hor_code_10_mux000369_1826
9336 
    );
9337 
  huffman_ins_v2_hor_code_10_mux000393 : LUT4
9338 
    generic map(
9339 
      INIT => X"A820"
9340 
    )
9341 
    port map (
9342 
      I0 => huffman_ins_v2_N38,
9343 
      I1 => huffman_ins_v2_a0_value_2_1510,
9344 
      I2 => huffman_ins_v2_code_black(10),
9345 
      I3 => huffman_ins_v2_code_white(10),
9346 
      O => huffman_ins_v2_hor_code_10_mux000393_1827
9347 
    );
9348 
  huffman_ins_v2_hor_code_10_mux000399 : LUT3
9349 
    generic map(
9350 
      INIT => X"08"
9351 
    )
9352 
    port map (
9353 
      I0 => huffman_ins_v2_N232,
9354 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
9355 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
9356 
      O => huffman_ins_v2_hor_code_10_mux000399_1828
9357 
    );
9358 
  huffman_ins_v2_hor_code_10_mux0003112 : LUT3
9359 
    generic map(
9360 
      INIT => X"32"
9361 
    )
9362 
    port map (
9363 
      I0 => huffman_ins_v2_hor_code_10_mux000399_1828,
9364 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
9365 
      I2 => huffman_ins_v2_hor_code_10_mux000393_1827,
9366 
      O => huffman_ins_v2_hor_code_10_mux0003112_1822
9367 
    );
9368 
  huffman_ins_v2_hor_code_9_mux000313 : LUT4
9369 
    generic map(
9370 
      INIT => X"2AAA"
9371 
    )
9372 
    port map (
9373 
      I0 => huffman_ins_v2_N100,
9374 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
9375 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
9376 
      I3 => huffman_ins_v2_mux_code_white_width(1),
9377 
      O => huffman_ins_v2_hor_code_9_mux000313_2042
9378 
    );
9379 
  huffman_ins_v2_hor_code_9_mux000342 : LUT4
9380 
    generic map(
9381 
      INIT => X"CCC8"
9382 
    )
9383 
    port map (
9384 
      I0 => huffman_ins_v2_N166,
9385 
      I1 => huffman_ins_v2_hor_code(9),
9386 
      I2 => huffman_ins_v2_hor_code_9_mux000313_2042,
9387 
      I3 => huffman_ins_v2_hor_code_9_mux000320_2044,
9388 
      O => huffman_ins_v2_hor_code_9_mux000342_2045
9389 
    );
9390 
  huffman_ins_v2_hor_code_9_mux000398 : LUT4
9391 
    generic map(
9392 
      INIT => X"A820"
9393 
    )
9394 
    port map (
9395 
      I0 => huffman_ins_v2_N38,
9396 
      I1 => huffman_ins_v2_a0_value_2_1510,
9397 
      I2 => huffman_ins_v2_code_black(9),
9398 
      I3 => huffman_ins_v2_code_white(9),
9399 
      O => huffman_ins_v2_hor_code_9_mux000398_2049
9400 
    );
9401 
  huffman_ins_v2_hor_code_9_mux0003114 : LUT4
9402 
    generic map(
9403 
      INIT => X"1000"
9404 
    )
9405 
    port map (
9406 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
9407 
      I1 => huffman_ins_v2_mux_code_white_width(1),
9408 
      I2 => huffman_ins_v2_hor_code_9_mux0003104_2040,
9409 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
9410 
      O => huffman_ins_v2_hor_code_9_mux0003114_2041
9411 
    );
9412 
  huffman_ins_v2_hor_code_8_mux000313 : LUT4
9413 
    generic map(
9414 
      INIT => X"020A"
9415 
    )
9416 
    port map (
9417 
      I0 => huffman_ins_v2_N109,
9418 
      I1 => huffman_ins_v2_mux_code_white_width(1),
9419 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
9420 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
9421 
      O => huffman_ins_v2_hor_code_8_mux000313_2031
9422 
    );
9423 
  huffman_ins_v2_hor_code_8_mux000341 : LUT4
9424 
    generic map(
9425 
      INIT => X"FFFE"
9426 
    )
9427 
    port map (
9428 
      I0 => huffman_ins_v2_N166,
9429 
      I1 => huffman_ins_v2_N105,
9430 
      I2 => huffman_ins_v2_hor_code_8_mux000313_2031,
9431 
      I3 => huffman_ins_v2_hor_code_8_mux000327_2035,
9432 
      O => huffman_ins_v2_hor_code_8_mux000341_2036
9433 
    );
9434 
  huffman_ins_v2_hor_code_8_mux000390 : LUT4
9435 
    generic map(
9436 
      INIT => X"A820"
9437 
    )
9438 
    port map (
9439 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
9440 
      I1 => huffman_ins_v2_a0_value_2_1510,
9441 
      I2 => huffman_ins_v2_code_white(8),
9442 
      I3 => huffman_ins_v2_code_black(8),
9443 
      O => huffman_ins_v2_hor_code_8_mux000390_2037
9444 
    );
9445 
  huffman_ins_v2_hor_code_8_mux0003129 : LUT4
9446 
    generic map(
9447 
      INIT => X"0E04"
9448 
    )
9449 
    port map (
9450 
      I0 => huffman_ins_v2_a0_value_2_1510,
9451 
      I1 => huffman_ins_v2_code_black(8),
9452 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
9453 
      I3 => huffman_ins_v2_code_white(8),
9454 
      O => huffman_ins_v2_hor_code_8_mux0003129_2030
9455 
    );
9456 
  huffman_ins_v2_hor_code_8_mux0003149 : LUT4
9457 
    generic map(
9458 
      INIT => X"1000"
9459 
    )
9460 
    port map (
9461 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
9462 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(1),
9463 
      I2 => huffman_ins_v2_N109,
9464 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
9465 
      O => huffman_ins_v2_hor_code_8_mux0003149_2032
9466 
    );
9467 
  huffman_ins_v2_hor_code_8_mux0003151 : LUT3
9468 
    generic map(
9469 
      INIT => X"EA"
9470 
    )
9471 
    port map (
9472 
      I0 => huffman_ins_v2_hor_code_8_mux0003149_2032,
9473 
      I1 => huffman_ins_v2_N51,
9474 
      I2 => huffman_ins_v2_hor_code_8_mux0003129_2030,
9475 
      O => huffman_ins_v2_hor_code_8_mux0003151_2033
9476 
    );
9477 
  huffman_ins_v2_hor_code_18_mux000346 : LUT3
9478 
    generic map(
9479 
      INIT => X"C8"
9480 
    )
9481 
    port map (
9482 
      I0 => huffman_ins_v2_N186,
9483 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
9484 
      I2 => huffman_ins_v2_hor_code_18_mux000328_1921,
9485 
      O => huffman_ins_v2_hor_code_18_mux000346_1922
9486 
    );
9487 
  huffman_ins_v2_hor_code_18_mux0003127 : LUT4
9488 
    generic map(
9489 
      INIT => X"1000"
9490 
    )
9491 
    port map (
9492 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
9493 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
9494 
      I2 => huffman_ins_v2_hor_code_18_and0001,
9495 
      I3 => huffman_ins_v2_mux_code_white_width(1),
9496 
      O => huffman_ins_v2_hor_code_18_mux0003127_1915
9497 
    );
9498 
  huffman_ins_v2_hor_code_18_mux0003130 : LUT4
9499 
    generic map(
9500 
      INIT => X"FFA8"
9501 
    )
9502 
    port map (
9503 
      I0 => huffman_ins_v2_hor_code(18),
9504 
      I1 => huffman_ins_v2_hor_code_18_mux000346_1922,
9505 
      I2 => huffman_ins_v2_hor_code_18_mux000381_1923,
9506 
      I3 => huffman_ins_v2_hor_code_18_mux0003127_1915,
9507 
      O => huffman_ins_v2_hor_code_18_mux0003130_1916
9508 
    );
9509 
  huffman_ins_v2_hor_code_18_mux0003181 : LUT4
9510 
    generic map(
9511 
      INIT => X"E444"
9512 
    )
9513 
    port map (
9514 
      I0 => huffman_ins_v2_hor_code_18_and0001,
9515 
      I1 => huffman_ins_v2_N245,
9516 
      I2 => huffman_ins_v2_N103,
9517 
      I3 => huffman_ins_v2_mux_code_white_width(1),
9518 
      O => huffman_ins_v2_hor_code_18_mux0003181_1918
9519 
    );
9520 
  huffman_ins_v2_hor_code_18_mux0003230 : LUT4
9521 
    generic map(
9522 
      INIT => X"AA80"
9523 
    )
9524 
    port map (
9525 
      I0 => huffman_ins_v2_code_black(18),
9526 
      I1 => huffman_ins_v2_hor_code_18_mux0003181_1918,
9527 
      I2 => huffman_ins_v2_hor_code_18_mux0003199_1919,
9528 
      I3 => huffman_ins_v2_hor_code_18_mux0003164_1917,
9529 
      O => huffman_ins_v2_hor_code_18_mux0003230_1920
9530 
    );
9531 
  huffman_ins_v2_code_white_8_cmp_eq000211 : LUT3
9532 
    generic map(
9533 
      INIT => X"08"
9534 
    )
9535 
    port map (
9536 
      I0 => huffman_ins_v2_codetab_ter_white_width(2),
9537 
      I1 => huffman_ins_v2_codetab_ter_white_width(1),
9538 
      I2 => huffman_ins_v2_codetab_ter_white_width(3),
9539 
      O => huffman_ins_v2_N239
9540 
    );
9541 
  huffman_ins_v2_code_white_8_cmp_eq00001 : LUT4
9542 
    generic map(
9543 
      INIT => X"0010"
9544 
    )
9545 
    port map (
9546 
      I0 => huffman_ins_v2_codetab_ter_white_width(0),
9547 
      I1 => huffman_ins_v2_codetab_ter_white_width(1),
9548 
      I2 => huffman_ins_v2_codetab_ter_white_width(2),
9549 
      I3 => huffman_ins_v2_codetab_ter_white_width(3),
9550 
      O => huffman_ins_v2_code_white_8_cmp_eq0000
9551 
    );
9552 
  huffman_ins_v2_code_white_8_or00001 : LUT4
9553 
    generic map(
9554 
      INIT => X"DDD9"
9555 
    )
9556 
    port map (
9557 
      I0 => huffman_ins_v2_codetab_ter_white_width(2),
9558 
      I1 => huffman_ins_v2_codetab_ter_white_width(3),
9559 
      I2 => huffman_ins_v2_codetab_ter_white_width(1),
9560 
      I3 => huffman_ins_v2_codetab_ter_white_width(0),
9561 
      O => huffman_ins_v2_code_white_8_or0000
9562 
    );
9563 
  huffman_ins_v2_code_white_14_mux00004 : LUT4
9564 
    generic map(
9565 
      INIT => X"F888"
9566 
    )
9567 
    port map (
9568 
      I0 => huffman_ins_v2_code_white_8_or0000,
9569 
      I1 => huffman_ins_v2_code_white(14),
9570 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0004,
9571 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(6),
9572 
      O => huffman_ins_v2_code_white_14_mux00004_1754
9573 
    );
9574 
  huffman_ins_v2_code_white_6_mux00004 : LUT4
9575 
    generic map(
9576 
      INIT => X"F888"
9577 
    )
9578 
    port map (
9579 
      I0 => huffman_ins_v2_code_white_8_cmp_eq0000,
9580 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(2),
9581 
      I2 => huffman_ins_v2_code_white(6),
9582 
      I3 => huffman_ins_v2_code_white_8_or0000,
9583 
      O => huffman_ins_v2_code_white_6_mux00004_1778
9584 
    );
9585 
  huffman_ins_v2_code_white_9_mux00004 : LUT4
9586 
    generic map(
9587 
      INIT => X"F888"
9588 
    )
9589 
    port map (
9590 
      I0 => huffman_ins_v2_code_white_8_cmp_eq0001,
9591 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(4),
9592 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0000,
9593 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(5),
9594 
      O => huffman_ins_v2_code_white_9_mux00004_1796
9595 
    );
9596 
  huffman_ins_v2_code_white_9_mux00009 : LUT4
9597 
    generic map(
9598 
      INIT => X"F888"
9599 
    )
9600 
    port map (
9601 
      I0 => huffman_ins_v2_code_white_8_or0000,
9602 
      I1 => huffman_ins_v2_code_white(9),
9603 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0004,
9604 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(1),
9605 
      O => huffman_ins_v2_code_white_9_mux00009_1797
9606 
    );
9607 
  huffman_ins_v2_code_white_9_mux000010 : LUT2
9608 
    generic map(
9609 
      INIT => X"E"
9610 
    )
9611 
    port map (
9612 
      I0 => huffman_ins_v2_code_white_9_mux00004_1796,
9613 
      I1 => huffman_ins_v2_code_white_9_mux00009_1797,
9614 
      O => huffman_ins_v2_code_white_9_mux000010_1794
9615 
    );
9616 
  huffman_ins_v2_code_white_8_mux00004 : LUT4
9617 
    generic map(
9618 
      INIT => X"F888"
9619 
    )
9620 
    port map (
9621 
      I0 => huffman_ins_v2_code_white_8_cmp_eq0001,
9622 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(3),
9623 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0000,
9624 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(4),
9625 
      O => huffman_ins_v2_code_white_8_mux00004_1790
9626 
    );
9627 
  huffman_ins_v2_code_white_8_mux00009 : LUT4
9628 
    generic map(
9629 
      INIT => X"F888"
9630 
    )
9631 
    port map (
9632 
      I0 => huffman_ins_v2_code_white_8_or0000,
9633 
      I1 => huffman_ins_v2_code_white(8),
9634 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0004,
9635 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(0),
9636 
      O => huffman_ins_v2_code_white_8_mux00009_1791
9637 
    );
9638 
  huffman_ins_v2_code_white_8_mux000010 : LUT2
9639 
    generic map(
9640 
      INIT => X"E"
9641 
    )
9642 
    port map (
9643 
      I0 => huffman_ins_v2_code_white_8_mux00004_1790,
9644 
      I1 => huffman_ins_v2_code_white_8_mux00009_1791,
9645 
      O => huffman_ins_v2_code_white_8_mux000010_1788
9646 
    );
9647 
  huffman_ins_v2_code_white_7_mux00004 : LUT4
9648 
    generic map(
9649 
      INIT => X"F888"
9650 
    )
9651 
    port map (
9652 
      I0 => huffman_ins_v2_code_white_8_cmp_eq0001,
9653 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(2),
9654 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0000,
9655 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(3),
9656 
      O => huffman_ins_v2_code_white_7_mux00004_1782
9657 
    );
9658 
  huffman_ins_v2_code_white_7_mux00009 : LUT4
9659 
    generic map(
9660 
      INIT => X"F888"
9661 
    )
9662 
    port map (
9663 
      I0 => huffman_ins_v2_code_white_8_or0000,
9664 
      I1 => huffman_ins_v2_code_white(7),
9665 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0004,
9666 
      I3 => huffman_ins_v2_ter_white_code(7),
9667 
      O => huffman_ins_v2_code_white_7_mux00009_1783
9668 
    );
9669 
  huffman_ins_v2_code_white_7_mux000010 : LUT2
9670 
    generic map(
9671 
      INIT => X"E"
9672 
    )
9673 
    port map (
9674 
      I0 => huffman_ins_v2_code_white_7_mux00004_1782,
9675 
      I1 => huffman_ins_v2_code_white_7_mux00009_1783,
9676 
      O => huffman_ins_v2_code_white_7_mux000010_1780
9677 
    );
9678 
  huffman_ins_v2_code_white_12_mux00004 : LUT4
9679 
    generic map(
9680 
      INIT => X"F888"
9681 
    )
9682 
    port map (
9683 
      I0 => huffman_ins_v2_code_white_8_cmp_eq0001,
9684 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(7),
9685 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0000,
9686 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(8),
9687 
      O => huffman_ins_v2_code_white_12_mux00004_1747
9688 
    );
9689 
  huffman_ins_v2_code_white_12_mux00009 : LUT4
9690 
    generic map(
9691 
      INIT => X"F888"
9692 
    )
9693 
    port map (
9694 
      I0 => huffman_ins_v2_code_white_8_or0000,
9695 
      I1 => huffman_ins_v2_code_white(12),
9696 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0004,
9697 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(4),
9698 
      O => huffman_ins_v2_code_white_12_mux00009_1748
9699 
    );
9700 
  huffman_ins_v2_code_white_12_mux000010 : LUT2
9701 
    generic map(
9702 
      INIT => X"E"
9703 
    )
9704 
    port map (
9705 
      I0 => huffman_ins_v2_code_white_12_mux00004_1747,
9706 
      I1 => huffman_ins_v2_code_white_12_mux00009_1748,
9707 
      O => huffman_ins_v2_code_white_12_mux000010_1745
9708 
    );
9709 
  huffman_ins_v2_code_white_11_mux00004 : LUT4
9710 
    generic map(
9711 
      INIT => X"F888"
9712 
    )
9713 
    port map (
9714 
      I0 => huffman_ins_v2_code_white_8_cmp_eq0001,
9715 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(6),
9716 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0000,
9717 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(7),
9718 
      O => huffman_ins_v2_code_white_11_mux00004_1742
9719 
    );
9720 
  huffman_ins_v2_code_white_11_mux00009 : LUT4
9721 
    generic map(
9722 
      INIT => X"F888"
9723 
    )
9724 
    port map (
9725 
      I0 => huffman_ins_v2_code_white_8_or0000,
9726 
      I1 => huffman_ins_v2_code_white(11),
9727 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0004,
9728 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(3),
9729 
      O => huffman_ins_v2_code_white_11_mux00009_1743
9730 
    );
9731 
  huffman_ins_v2_code_white_11_mux000010 : LUT2
9732 
    generic map(
9733 
      INIT => X"E"
9734 
    )
9735 
    port map (
9736 
      I0 => huffman_ins_v2_code_white_11_mux00004_1742,
9737 
      I1 => huffman_ins_v2_code_white_11_mux00009_1743,
9738 
      O => huffman_ins_v2_code_white_11_mux000010_1740
9739 
    );
9740 
  huffman_ins_v2_code_white_10_mux00004 : LUT4
9741 
    generic map(
9742 
      INIT => X"F888"
9743 
    )
9744 
    port map (
9745 
      I0 => huffman_ins_v2_code_white_8_cmp_eq0001,
9746 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(5),
9747 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0000,
9748 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(6),
9749 
      O => huffman_ins_v2_code_white_10_mux00004_1737
9750 
    );
9751 
  huffman_ins_v2_code_white_10_mux00009 : LUT4
9752 
    generic map(
9753 
      INIT => X"F888"
9754 
    )
9755 
    port map (
9756 
      I0 => huffman_ins_v2_code_white_8_or0000,
9757 
      I1 => huffman_ins_v2_code_white(10),
9758 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0004,
9759 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(2),
9760 
      O => huffman_ins_v2_code_white_10_mux00009_1738
9761 
    );
9762 
  huffman_ins_v2_code_white_10_mux000010 : LUT2
9763 
    generic map(
9764 
      INIT => X"E"
9765 
    )
9766 
    port map (
9767 
      I0 => huffman_ins_v2_code_white_10_mux00004_1737,
9768 
      I1 => huffman_ins_v2_code_white_10_mux00009_1738,
9769 
      O => huffman_ins_v2_code_white_10_mux000010_1735
9770 
    );
9771 
  fax4_ins_state_FSM_FFd5_In5 : LUT4
9772 
    generic map(
9773 
      INIT => X"CCC8"
9774 
    )
9775 
    port map (
9776 
      I0 => fax4_ins_state_FSM_FFd2_1327,
9777 
      I1 => fax4_ins_pass_mode,
9778 
      I2 => fax4_ins_state_FSM_FFd6_1336,
9779 
      I3 => fax4_ins_state_FSM_FFd10_1323,
9780 
      O => fax4_ins_state_FSM_FFd5_In5_1335
9781 
    );
9782 
  huffman_ins_v2_run_length_black_0_1 : LUT3
9783 
    generic map(
9784 
      INIT => X"E4"
9785 
    )
9786 
    port map (
9787 
      I0 => fax4_ins_a0_value_o_950,
9788 
      I1 => huffman_ins_v2_run_length_white_sub0000(0),
9789 
      I2 => huffman_ins_v2_run_length_white_sub0001(0),
9790 
      O => huffman_ins_v2_run_length_black(0)
9791 
    );
9792 
  huffman_ins_v2_hor_code_4_mux0003211 : LUT3
9793 
    generic map(
9794 
      INIT => X"C8"
9795 
    )
9796 
    port map (
9797 
      I0 => huffman_ins_v2_mux_code_black_width(0),
9798 
      I1 => huffman_ins_v2_mux_code_black_width(2),
9799 
      I2 => huffman_ins_v2_mux_code_black_width(1),
9800 
      O => huffman_ins_v2_N251
9801 
    );
9802 
  huffman_ins_v2_mux_code_white_width_4_1 : LUT3
9803 
    generic map(
9804 
      INIT => X"E4"
9805 
    )
9806 
    port map (
9807 
      I0 => huffman_ins_v2_a0_value_2_1510,
9808 
      I1 => huffman_ins_v2_code_black_width(4),
9809 
      I2 => huffman_ins_v2_code_white_width(4),
9810 
      O => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4)
9811 
    );
9812 
  huffman_ins_v2_mux_code_white_width_3_1 : LUT3
9813 
    generic map(
9814 
      INIT => X"E4"
9815 
    )
9816 
    port map (
9817 
      I0 => huffman_ins_v2_a0_value_2_1510,
9818 
      I1 => huffman_ins_v2_code_black_width(3),
9819 
      I2 => huffman_ins_v2_code_white_width(3),
9820 
      O => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3)
9821 
    );
9822 
  huffman_ins_v2_mux_code_white_width_0_1 : LUT3
9823 
    generic map(
9824 
      INIT => X"E4"
9825 
    )
9826 
    port map (
9827 
      I0 => huffman_ins_v2_a0_value_2_1510,
9828 
      I1 => huffman_ins_v2_code_black_width(0),
9829 
      I2 => huffman_ins_v2_code_white_width(0),
9830 
      O => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0)
9831 
    );
9832 
  huffman_ins_v2_mux_code_black_width_4_1 : LUT3
9833 
    generic map(
9834 
      INIT => X"E4"
9835 
    )
9836 
    port map (
9837 
      I0 => huffman_ins_v2_a0_value_2_1510,
9838 
      I1 => huffman_ins_v2_code_white_width(4),
9839 
      I2 => huffman_ins_v2_code_black_width(4),
9840 
      O => huffman_ins_v2_mux_code_black_width(4)
9841 
    );
9842 
  huffman_ins_v2_mux_code_black_width_3_1 : LUT3
9843 
    generic map(
9844 
      INIT => X"E4"
9845 
    )
9846 
    port map (
9847 
      I0 => huffman_ins_v2_a0_value_2_1510,
9848 
      I1 => huffman_ins_v2_code_white_width(3),
9849 
      I2 => huffman_ins_v2_code_black_width(3),
9850 
      O => huffman_ins_v2_mux_code_black_width(3)
9851 
    );
9852 
  huffman_ins_v2_mux_code_black_width_0_1 : LUT3
9853 
    generic map(
9854 
      INIT => X"E4"
9855 
    )
9856 
    port map (
9857 
      I0 => huffman_ins_v2_a0_value_2_1510,
9858 
      I1 => huffman_ins_v2_code_white_width(0),
9859 
      I2 => huffman_ins_v2_code_black_width(0),
9860 
      O => huffman_ins_v2_mux_code_black_width(0)
9861 
    );
9862 
  huffman_ins_v2_hor_code_13_or00031 : LUT3
9863 
    generic map(
9864 
      INIT => X"B5"
9865 
    )
9866 
    port map (
9867 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
9868 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
9869 
      I2 => huffman_ins_v2_mux_code_white_width(1),
9870 
      O => huffman_ins_v2_hor_code_13_or0003
9871 
    );
9872 
  huffman_ins_v2_hor_code_10_mux000342 : LUT4
9873 
    generic map(
9874 
      INIT => X"8000"
9875 
    )
9876 
    port map (
9877 
      I0 => huffman_ins_v2_mux_code_black_width(4),
9878 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
9879 
      I2 => huffman_ins_v2_N251,
9880 
      I3 => huffman_ins_v2_mux_code_black_width(3),
9881 
      O => huffman_ins_v2_N82
9882 
    );
9883 
  huffman_ins_v2_hor_code_10_mux00031212 : LUT4
9884 
    generic map(
9885 
      INIT => X"AEAA"
9886 
    )
9887 
    port map (
9888 
      I0 => huffman_ins_v2_N82,
9889 
      I1 => huffman_ins_v2_N102,
9890 
      I2 => huffman_ins_v2_N170,
9891 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
9892 
      O => huffman_ins_v2_N166
9893 
    );
9894 
  huffman_ins_v2_hor_code_5_mux000315 : LUT4
9895 
    generic map(
9896 
      INIT => X"FFEA"
9897 
    )
9898 
    port map (
9899 
      I0 => huffman_ins_v2_N166,
9900 
      I1 => huffman_ins_v2_N105,
9901 
      I2 => huffman_ins_v2_N78,
9902 
      I3 => huffman_ins_v2_hor_code_5_mux00037_2010,
9903 
      O => huffman_ins_v2_hor_code_5_mux000315_2007
9904 
    );
9905 
  huffman_ins_v2_hor_code_5_mux000349 : LUT4
9906 
    generic map(
9907 
      INIT => X"0E04"
9908 
    )
9909 
    port map (
9910 
      I0 => huffman_ins_v2_a0_value_2_1510,
9911 
      I1 => huffman_ins_v2_code_black(5),
9912 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
9913 
      I3 => huffman_ins_v2_code_white(5),
9914 
      O => huffman_ins_v2_hor_code_5_mux000349_2009
9915 
    );
9916 
  huffman_ins_v2_hor_code_5_mux000376 : LUT4
9917 
    generic map(
9918 
      INIT => X"A820"
9919 
    )
9920 
    port map (
9921 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
9922 
      I1 => huffman_ins_v2_a0_value_2_1510,
9923 
      I2 => huffman_ins_v2_code_white(5),
9924 
      I3 => huffman_ins_v2_code_black(5),
9925 
      O => huffman_ins_v2_hor_code_5_mux000376_2011
9926 
    );
9927 
  huffman_ins_v2_hor_code_5_mux000380 : LUT4
9928 
    generic map(
9929 
      INIT => X"AA02"
9930 
    )
9931 
    port map (
9932 
      I0 => huffman_ins_v2_hor_code_5_mux000376_2011,
9933 
      I1 => huffman_ins_v2_mux_code_black_width(4),
9934 
      I2 => huffman_ins_v2_N78,
9935 
      I3 => huffman_ins_v2_N48,
9936 
      O => huffman_ins_v2_hor_code_5_mux000380_2012
9937 
    );
9938 
  huffman_ins_v2_hor_code_3_mux000340 : LUT4
9939 
    generic map(
9940 
      INIT => X"2000"
9941 
    )
9942 
    port map (
9943 
      I0 => huffman_ins_v2_mux_code_white_width(1),
9944 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
9945 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
9946 
      I3 => huffman_ins_v2_N100,
9947 
      O => huffman_ins_v2_hor_code_3_mux000340_1993
9948 
    );
9949 
  huffman_ins_v2_hor_code_3_mux000342 : LUT3
9950 
    generic map(
9951 
      INIT => X"EA"
9952 
    )
9953 
    port map (
9954 
      I0 => huffman_ins_v2_hor_code_3_mux000340_1993,
9955 
      I1 => huffman_ins_v2_hor_code(3),
9956 
      I2 => huffman_ins_v2_hor_code_3_mux000318_1991,
9957 
      O => huffman_ins_v2_hor_code_3_mux000342_1994
9958 
    );
9959 
  huffman_ins_v2_hor_code_0_mux000310 : LUT4
9960 
    generic map(
9961 
      INIT => X"FF04"
9962 
    )
9963 
    port map (
9964 
      I0 => huffman_ins_v2_N99,
9965 
      I1 => huffman_ins_v2_N105,
9966 
      I2 => huffman_ins_v2_mux_code_black_width(0),
9967 
      I3 => huffman_ins_v2_N166,
9968 
      O => huffman_ins_v2_hor_code_0_mux000310_1816
9969 
    );
9970 
  huffman_ins_v2_hor_code_0_mux000324 : LUT3
9971 
    generic map(
9972 
      INIT => X"EA"
9973 
    )
9974 
    port map (
9975 
      I0 => huffman_ins_v2_hor_code_0_mux000322_1817,
9976 
      I1 => huffman_ins_v2_hor_code(0),
9977 
      I2 => huffman_ins_v2_hor_code_0_mux000310_1816,
9978 
      O => huffman_ins_v2_hor_code_0_mux000324_1818
9979 
    );
9980 
  huffman_ins_v2_hor_code_1_mux000339 : LUT4
9981 
    generic map(
9982 
      INIT => X"0E04"
9983 
    )
9984 
    port map (
9985 
      I0 => huffman_ins_v2_a0_value_2_1510,
9986 
      I1 => huffman_ins_v2_code_black(1),
9987 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
9988 
      I3 => huffman_ins_v2_code_white(1),
9989 
      O => huffman_ins_v2_hor_code_1_mux000339_1931
9990 
    );
9991 
  huffman_ins_v2_hor_code_1_mux000347 : LUT4
9992 
    generic map(
9993 
      INIT => X"70E0"
9994 
    )
9995 
    port map (
9996 
      I0 => huffman_ins_v2_N59,
9997 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
9998 
      I2 => huffman_ins_v2_hor_code_1_mux000339_1931,
9999 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
10000 
      O => huffman_ins_v2_hor_code_1_mux000347_1932
10001 
    );
10002 
  huffman_ins_v2_hor_code_1_mux000379 : LUT4
10003 
    generic map(
10004 
      INIT => X"FF04"
10005 
    )
10006 
    port map (
10007 
      I0 => huffman_ins_v2_mux_code_black_width(2),
10008 
      I1 => huffman_ins_v2_N105,
10009 
      I2 => huffman_ins_v2_mux_code_black_width(1),
10010 
      I3 => huffman_ins_v2_N166,
10011 
      O => huffman_ins_v2_hor_code_1_mux000379_1934
10012 
    );
10013 
  huffman_ins_v2_hor_code_1_mux000386 : LUT3
10014 
    generic map(
10015 
      INIT => X"EA"
10016 
    )
10017 
    port map (
10018 
      I0 => huffman_ins_v2_hor_code_1_mux000354_1933,
10019 
      I1 => huffman_ins_v2_hor_code(1),
10020 
      I2 => huffman_ins_v2_hor_code_1_mux000379_1934,
10021 
      O => huffman_ins_v2_hor_code_1_mux000386_1935
10022 
    );
10023 
  huffman_ins_v2_hor_code_1_mux0003116 : LUT4
10024 
    generic map(
10025 
      INIT => X"A820"
10026 
    )
10027 
    port map (
10028 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
10029 
      I1 => huffman_ins_v2_a0_value_2_1510,
10030 
      I2 => huffman_ins_v2_code_white(1),
10031 
      I3 => huffman_ins_v2_code_black(1),
10032 
      O => huffman_ins_v2_hor_code_1_mux0003116_1929
10033 
    );
10034 
  huffman_ins_v2_hor_code_1_mux0003120 : LUT4
10035 
    generic map(
10036 
      INIT => X"F020"
10037 
    )
10038 
    port map (
10039 
      I0 => huffman_ins_v2_mux_code_black_width(1),
10040 
      I1 => huffman_ins_v2_mux_code_black_width(4),
10041 
      I2 => huffman_ins_v2_hor_code_1_mux0003116_1929,
10042 
      I3 => huffman_ins_v2_N52,
10043 
      O => huffman_ins_v2_hor_code_1_mux0003120_1930
10044 
    );
10045 
  huffman_ins_v2_hor_code_4_mux000310 : LUT4
10046 
    generic map(
10047 
      INIT => X"FFEA"
10048 
    )
10049 
    port map (
10050 
      I0 => huffman_ins_v2_N166,
10051 
      I1 => huffman_ins_v2_N105,
10052 
      I2 => huffman_ins_v2_N71,
10053 
      I3 => huffman_ins_v2_hor_code_4_mux00033_1999,
10054 
      O => huffman_ins_v2_hor_code_4_mux000310_1997
10055 
    );
10056 
  huffman_ins_v2_hor_code_4_mux0003311 : LUT4
10057 
    generic map(
10058 
      INIT => X"1000"
10059 
    )
10060 
    port map (
10061 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
10062 
      I1 => huffman_ins_v2_mux_code_white_width(1),
10063 
      I2 => huffman_ins_v2_N100,
10064 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
10065 
      O => huffman_ins_v2_hor_code_4_mux000331_2000
10066 
    );
10067 
  huffman_ins_v2_hor_code_4_mux000333 : LUT3
10068 
    generic map(
10069 
      INIT => X"EA"
10070 
    )
10071 
    port map (
10072 
      I0 => huffman_ins_v2_hor_code_4_mux000331_2000,
10073 
      I1 => huffman_ins_v2_hor_code(4),
10074 
      I2 => huffman_ins_v2_hor_code_4_mux000310_1997,
10075 
      O => huffman_ins_v2_hor_code_4_mux000333_2001
10076 
    );
10077 
  huffman_ins_v2_hor_code_4_mux000358 : LUT4
10078 
    generic map(
10079 
      INIT => X"0E04"
10080 
    )
10081 
    port map (
10082 
      I0 => huffman_ins_v2_a0_value_2_1510,
10083 
      I1 => huffman_ins_v2_code_black(4),
10084 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
10085 
      I3 => huffman_ins_v2_code_white(4),
10086 
      O => huffman_ins_v2_hor_code_4_mux000358_2002
10087 
    );
10088 
  huffman_ins_v2_hor_code_4_mux000384 : LUT4
10089 
    generic map(
10090 
      INIT => X"A820"
10091 
    )
10092 
    port map (
10093 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
10094 
      I1 => huffman_ins_v2_a0_value_2_1510,
10095 
      I2 => huffman_ins_v2_code_white(4),
10096 
      I3 => huffman_ins_v2_code_black(4),
10097 
      O => huffman_ins_v2_hor_code_4_mux000384_2003
10098 
    );
10099 
  huffman_ins_v2_hor_code_4_mux000388 : LUT4
10100 
    generic map(
10101 
      INIT => X"F020"
10102 
    )
10103 
    port map (
10104 
      I0 => huffman_ins_v2_N251,
10105 
      I1 => huffman_ins_v2_mux_code_black_width(4),
10106 
      I2 => huffman_ins_v2_hor_code_4_mux000384_2003,
10107 
      I3 => huffman_ins_v2_N48,
10108 
      O => huffman_ins_v2_hor_code_4_mux000388_2004
10109 
    );
10110 
  huffman_ins_v2_hor_code_22_mux000317 : LUT4
10111 
    generic map(
10112 
      INIT => X"028A"
10113 
    )
10114 
    port map (
10115 
      I0 => huffman_ins_v2_N95,
10116 
      I1 => huffman_ins_v2_mux_code_black_width(3),
10117 
      I2 => huffman_ins_v2_N67,
10118 
      I3 => huffman_ins_v2_N99,
10119 
      O => huffman_ins_v2_hor_code_22_mux000317_1961
10120 
    );
10121 
  huffman_ins_v2_hor_code_22_mux000360 : LUT4
10122 
    generic map(
10123 
      INIT => X"45EF"
10124 
    )
10125 
    port map (
10126 
      I0 => huffman_ins_v2_a0_value_2_1510,
10127 
      I1 => huffman_ins_v2_code_black(22),
10128 
      I2 => huffman_ins_v2_code_black_width(0),
10129 
      I3 => huffman_ins_v2_code_white_width(0),
10130 
      O => huffman_ins_v2_hor_code_22_mux000360_1963
10131 
    );
10132 
  huffman_ins_v2_hor_code_22_mux000375 : LUT4
10133 
    generic map(
10134 
      INIT => X"1000"
10135 
    )
10136 
    port map (
10137 
      I0 => huffman_ins_v2_hor_code_13_or0005,
10138 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
10139 
      I2 => huffman_ins_v2_hor_code_22_mux000360_1963,
10140 
      I3 => huffman_ins_v2_N102,
10141 
      O => huffman_ins_v2_hor_code_22_mux000375_1964
10142 
    );
10143 
  huffman_ins_v2_hor_code_22_mux000385 : LUT4
10144 
    generic map(
10145 
      INIT => X"FFA8"
10146 
    )
10147 
    port map (
10148 
      I0 => huffman_ins_v2_code_black(22),
10149 
      I1 => huffman_ins_v2_hor_code_22_mux000317_1961,
10150 
      I2 => huffman_ins_v2_hor_code_22_mux000320_1962,
10151 
      I3 => huffman_ins_v2_hor_code_22_mux000375_1964,
10152 
      O => huffman_ins_v2_hor_code_22_mux000385_1965
10153 
    );
10154 
  huffman_ins_v2_hor_code_22_mux0003112 : LUT4
10155 
    generic map(
10156 
      INIT => X"FD75"
10157 
    )
10158 
    port map (
10159 
      I0 => huffman_ins_v2_mux_code_black_width(4),
10160 
      I1 => huffman_ins_v2_mux_code_black_width(3),
10161 
      I2 => huffman_ins_v2_N67,
10162 
      I3 => huffman_ins_v2_N251,
10163 
      O => huffman_ins_v2_hor_code_22_mux0003112_1959
10164 
    );
10165 
  huffman_ins_v2_hor_code_2_mux000330 : LUT4
10166 
    generic map(
10167 
      INIT => X"0E04"
10168 
    )
10169 
    port map (
10170 
      I0 => huffman_ins_v2_a0_value_2_1510,
10171 
      I1 => huffman_ins_v2_code_black(2),
10172 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
10173 
      I3 => huffman_ins_v2_code_white(2),
10174 
      O => huffman_ins_v2_hor_code_2_mux000330_1986
10175 
    );
10176 
  huffman_ins_v2_hor_code_2_mux0003104 : LUT4
10177 
    generic map(
10178 
      INIT => X"AEAA"
10179 
    )
10180 
    port map (
10181 
      I0 => huffman_ins_v2_N52,
10182 
      I1 => huffman_ins_v2_mux_code_black_width(0),
10183 
      I2 => huffman_ins_v2_mux_code_black_width(4),
10184 
      I3 => huffman_ins_v2_mux_code_black_width(1),
10185 
      O => huffman_ins_v2_hor_code_2_mux0003104_1983
10186 
    );
10187 
  huffman_ins_v2_hor_code_2_mux0003117 : LUT4
10188 
    generic map(
10189 
      INIT => X"A820"
10190 
    )
10191 
    port map (
10192 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
10193 
      I1 => huffman_ins_v2_a0_value_2_1510,
10194 
      I2 => huffman_ins_v2_code_white(2),
10195 
      I3 => huffman_ins_v2_code_black(2),
10196 
      O => huffman_ins_v2_hor_code_2_mux0003117_1984
10197 
    );
10198 
  huffman_ins_v2_hor_code_20_mux000370 : LUT4
10199 
    generic map(
10200 
      INIT => X"FFE2"
10201 
    )
10202 
    port map (
10203 
      I0 => huffman_ins_v2_hor_code_20_mux000350_1946,
10204 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
10205 
      I2 => huffman_ins_v2_hor_code_20_mux000315_1942,
10206 
      I3 => huffman_ins_v2_hor_code_20_mux00030_1938,
10207 
      O => huffman_ins_v2_hor_code_20_mux000370_1947
10208 
    );
10209 
  huffman_ins_v2_hor_code_20_mux0003105 : LUT4
10210 
    generic map(
10211 
      INIT => X"1000"
10212 
    )
10213 
    port map (
10214 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
10215 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(1),
10216 
      I2 => huffman_ins_v2_N102,
10217 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
10218 
      O => huffman_ins_v2_hor_code_20_mux0003105_1939
10219 
    );
10220 
  huffman_ins_v2_hor_code_20_mux0003127 : LUT4
10221 
    generic map(
10222 
      INIT => X"F020"
10223 
    )
10224 
    port map (
10225 
      I0 => huffman_ins_v2_N250,
10226 
      I1 => huffman_ins_v2_mux_code_black_width(3),
10227 
      I2 => huffman_ins_v2_N95,
10228 
      I3 => huffman_ins_v2_N169,
10229 
      O => huffman_ins_v2_hor_code_20_mux0003127_1940
10230 
    );
10231 
  huffman_ins_v2_hor_code_20_mux0003145 : LUT4
10232 
    generic map(
10233 
      INIT => X"028A"
10234 
    )
10235 
    port map (
10236 
      I0 => huffman_ins_v2_N245,
10237 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
10238 
      I2 => huffman_ins_v2_N170,
10239 
      I3 => huffman_ins_v2_N59,
10240 
      O => huffman_ins_v2_hor_code_20_mux0003145_1941
10241 
    );
10242 
  huffman_ins_v2_hor_code_20_mux0003158 : LUT3
10243 
    generic map(
10244 
      INIT => X"C8"
10245 
    )
10246 
    port map (
10247 
      I0 => huffman_ins_v2_hor_code_20_mux0003127_1940,
10248 
      I1 => huffman_ins_v2_code_black(20),
10249 
      I2 => huffman_ins_v2_hor_code_20_mux0003145_1941,
10250 
      O => huffman_ins_v2_hor_code_20_mux0003158_1943
10251 
    );
10252 
  huffman_ins_v2_hor_code_16_mux000394 : LUT2
10253 
    generic map(
10254 
      INIT => X"8"
10255 
    )
10256 
    port map (
10257 
      I0 => huffman_ins_v2_code_white_width(4),
10258 
      I1 => huffman_ins_v2_code_white(16),
10259 
      O => huffman_ins_v2_hor_code_16_mux000394_1902
10260 
    );
10261 
  huffman_ins_v2_hor_code_16_mux0003102 : LUT4
10262 
    generic map(
10263 
      INIT => X"F888"
10264 
    )
10265 
    port map (
10266 
      I0 => huffman_ins_v2_hor_code(16),
10267 
      I1 => huffman_ins_v2_hor_code_16_mux000359_1900,
10268 
      I2 => huffman_ins_v2_hor_code_16_mux000393_1901,
10269 
      I3 => huffman_ins_v2_hor_code_16_mux000394_1902,
10270 
      O => huffman_ins_v2_hor_code_16_mux0003102_1896
10271 
    );
10272 
  huffman_ins_v2_hor_code_16_mux0003136 : LUT4
10273 
    generic map(
10274 
      INIT => X"0010"
10275 
    )
10276 
    port map (
10277 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
10278 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
10279 
      I2 => huffman_ins_v2_N102,
10280 
      I3 => huffman_ins_v2_N59,
10281 
      O => huffman_ins_v2_hor_code_16_mux0003136_1898
10282 
    );
10283 
  huffman_ins_v2_hor_code_21_mux000334 : LUT4
10284 
    generic map(
10285 
      INIT => X"1810"
10286 
    )
10287 
    port map (
10288 
      I0 => huffman_ins_v2_code_black_width(2),
10289 
      I1 => huffman_ins_v2_code_black_width(1),
10290 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
10291 
      I3 => huffman_ins_v2_hor_code_13_or0003,
10292 
      O => huffman_ins_v2_hor_code_21_mux000334_1953
10293 
    );
10294 
  huffman_ins_v2_hor_code_21_mux000379 : LUT4
10295 
    generic map(
10296 
      INIT => X"FFA8"
10297 
    )
10298 
    port map (
10299 
      I0 => huffman_ins_v2_code_black(21),
10300 
      I1 => huffman_ins_v2_hor_code_21_mux000310_1949,
10301 
      I2 => huffman_ins_v2_hor_code_21_mux000335_1954,
10302 
      I3 => huffman_ins_v2_hor_code_21_mux000376_1955,
10303 
      O => huffman_ins_v2_hor_code_21_mux000379_1956
10304 
    );
10305 
  huffman_ins_v2_hor_code_21_mux0003123 : LUT4
10306 
    generic map(
10307 
      INIT => X"AEAA"
10308 
    )
10309 
    port map (
10310 
      I0 => huffman_ins_v2_hor_code_13_cmp_eq0000,
10311 
      I1 => huffman_ins_v2_hor_code_13_or0003,
10312 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
10313 
      I3 => huffman_ins_v2_hor_code_13_or0005,
10314 
      O => huffman_ins_v2_hor_code_21_mux0003123_1950
10315 
    );
10316 
  huffman_ins_v2_hor_code_21_mux0003179 : LUT2
10317 
    generic map(
10318 
      INIT => X"8"
10319 
    )
10320 
    port map (
10321 
      I0 => huffman_ins_v2_hor_code(21),
10322 
      I1 => huffman_ins_v2_hor_code_21_mux0003168_1951,
10323 
      O => huffman_ins_v2_hor_code_21_mux0003179_1952
10324 
    );
10325 
  huffman_ins_v2_hor_code_13_mux00039 : LUT4
10326 
    generic map(
10327 
      INIT => X"FAF2"
10328 
    )
10329 
    port map (
10330 
      I0 => huffman_ins_v2_N110,
10331 
      I1 => huffman_ins_v2_mux_code_black_width(3),
10332 
      I2 => huffman_ins_v2_N82,
10333 
      I3 => huffman_ins_v2_N78,
10334 
      O => huffman_ins_v2_hor_code_13_mux00039_1861
10335 
    );
10336 
  huffman_ins_v2_hor_code_13_mux000320 : LUT4
10337 
    generic map(
10338 
      INIT => X"3111"
10339 
    )
10340 
    port map (
10341 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
10342 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
10343 
      I2 => huffman_ins_v2_hor_code_13_or0003,
10344 
      I3 => huffman_ins_v2_hor_code_13_or0005,
10345 
      O => huffman_ins_v2_hor_code_13_mux000320_1856
10346 
    );
10347 
  huffman_ins_v2_hor_code_13_mux000350 : LUT4
10348 
    generic map(
10349 
      INIT => X"F3F2"
10350 
    )
10351 
    port map (
10352 
      I0 => huffman_ins_v2_hor_code_13_mux000325_1857,
10353 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
10354 
      I2 => huffman_ins_v2_hor_code_13_mux00039_1861,
10355 
      I3 => huffman_ins_v2_hor_code_13_mux000320_1856,
10356 
      O => huffman_ins_v2_hor_code_13_mux000350_1858
10357 
    );
10358 
  huffman_ins_v2_hor_code_13_mux0003161 : LUT4
10359 
    generic map(
10360 
      INIT => X"0010"
10361 
    )
10362 
    port map (
10363 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
10364 
      I1 => huffman_ins_v2_mux_code_white_width(1),
10365 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
10366 
      I3 => huffman_ins_v2_N98,
10367 
      O => huffman_ins_v2_hor_code_13_mux0003161_1853
10368 
    );
10369 
  huffman_ins_v2_hor_code_13_mux0003181 : LUT3
10370 
    generic map(
10371 
      INIT => X"32"
10372 
    )
10373 
    port map (
10374 
      I0 => huffman_ins_v2_hor_code_13_mux0003161_1853,
10375 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
10376 
      I2 => huffman_ins_v2_hor_code_13_mux0003137_1852,
10377 
      O => huffman_ins_v2_hor_code_13_mux0003181_1854
10378 
    );
10379 
  huffman_ins_v2_hor_code_12_mux000311 : LUT4
10380 
    generic map(
10381 
      INIT => X"0010"
10382 
    )
10383 
    port map (
10384 
      I0 => huffman_ins_v2_code_black_width(4),
10385 
      I1 => huffman_ins_v2_code_black_width(0),
10386 
      I2 => huffman_ins_v2_a0_value_2_1510,
10387 
      I3 => huffman_ins_v2_code_black_width(1),
10388 
      O => huffman_ins_v2_hor_code_12_mux000311_1839
10389 
    );
10390 
  huffman_ins_v2_hor_code_12_mux000324 : LUT4
10391 
    generic map(
10392 
      INIT => X"0001"
10393 
    )
10394 
    port map (
10395 
      I0 => huffman_ins_v2_code_white_width(4),
10396 
      I1 => huffman_ins_v2_a0_value_2_1510,
10397 
      I2 => huffman_ins_v2_code_white_width(0),
10398 
      I3 => huffman_ins_v2_code_white_width(1),
10399 
      O => huffman_ins_v2_hor_code_12_mux000324_1846
10400 
    );
10401 
  huffman_ins_v2_hor_code_12_mux0003104 : LUT4
10402 
    generic map(
10403 
      INIT => X"0010"
10404 
    )
10405 
    port map (
10406 
      I0 => huffman_ins_v2_code_white_width(4),
10407 
      I1 => huffman_ins_v2_code_white_width(0),
10408 
      I2 => huffman_ins_v2_a0_value_2_1510,
10409 
      I3 => huffman_ins_v2_code_white_width(1),
10410 
      O => huffman_ins_v2_hor_code_12_mux0003104_1838
10411 
    );
10412 
  huffman_ins_v2_hor_code_12_mux0003117 : LUT4
10413 
    generic map(
10414 
      INIT => X"0001"
10415 
    )
10416 
    port map (
10417 
      I0 => huffman_ins_v2_code_black_width(4),
10418 
      I1 => huffman_ins_v2_a0_value_2_1510,
10419 
      I2 => huffman_ins_v2_code_black_width(0),
10420 
      I3 => huffman_ins_v2_code_black_width(1),
10421 
      O => huffman_ins_v2_hor_code_12_mux0003117_1840
10422 
    );
10423 
  huffman_ins_v2_hor_code_12_mux0003135 : LUT4
10424 
    generic map(
10425 
      INIT => X"FFAE"
10426 
    )
10427 
    port map (
10428 
      I0 => huffman_ins_v2_hor_code_12_mux0003104_1838,
10429 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(1),
10430 
      I2 => huffman_ins_v2_N98,
10431 
      I3 => huffman_ins_v2_hor_code_12_mux0003117_1840,
10432 
      O => huffman_ins_v2_hor_code_12_mux0003135_1841
10433 
    );
10434 
  huffman_ins_v2_hor_code_12_mux0003163 : LUT4
10435 
    generic map(
10436 
      INIT => X"F888"
10437 
    )
10438 
    port map (
10439 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
10440 
      I1 => huffman_ins_v2_hor_code_12_mux000364_1849,
10441 
      I2 => huffman_ins_v2_N102,
10442 
      I3 => huffman_ins_v2_hor_code_12_mux0003135_1841,
10443 
      O => huffman_ins_v2_hor_code_12_mux0003163_1842
10444 
    );
10445 
  huffman_ins_v2_hor_code_12_mux0003216 : LUT4
10446 
    generic map(
10447 
      INIT => X"0001"
10448 
    )
10449 
    port map (
10450 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
10451 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
10452 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(1),
10453 
      I3 => huffman_ins_v2_N98,
10454 
      O => huffman_ins_v2_hor_code_12_mux0003216_1844
10455 
    );
10456 
  huffman_ins_v2_hor_code_12_mux0003219 : LUT4
10457 
    generic map(
10458 
      INIT => X"FFA8"
10459 
    )
10460 
    port map (
10461 
      I0 => huffman_ins_v2_hor_code(12),
10462 
      I1 => huffman_ins_v2_hor_code_12_mux0003163_1842,
10463 
      I2 => huffman_ins_v2_hor_code_12_mux0003175_1843,
10464 
      I3 => huffman_ins_v2_hor_code_12_mux0003216_1844,
10465 
      O => huffman_ins_v2_hor_code_12_mux0003219_1845
10466 
    );
10467 
  huffman_ins_v2_code_black_15_mux000031 : LUT2
10468 
    generic map(
10469 
      INIT => X"8"
10470 
    )
10471 
    port map (
10472 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
10473 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
10474 
      O => huffman_ins_v2_code_black_15_mux0000_bdd1
10475 
    );
10476 
  huffman_ins_v2_Madd_code_white_width_add0000_lut_0_1 : LUT2
10477 
    generic map(
10478 
      INIT => X"6"
10479 
    )
10480 
    port map (
10481 
      I0 => huffman_ins_v2_code_table_ins_makeup_white(9),
10482 
      I1 => huffman_ins_v2_codetab_ter_white_width(0),
10483 
      O => huffman_ins_v2_Madd_code_white_width_add0000_lut(0)
10484 
    );
10485 
  huffman_ins_v2_Madd_code_black_width_add0000_lut_0_1 : LUT2
10486 
    generic map(
10487 
      INIT => X"6"
10488 
    )
10489 
    port map (
10490 
      I0 => huffman_ins_v2_code_table_ins_makeup_black_13_Q,
10491 
      I1 => huffman_ins_v2_codetab_ter_black_width(0),
10492 
      O => huffman_ins_v2_Madd_code_black_width_add0000_lut(0)
10493 
    );
10494 
  huffman_ins_v2_code_black_11_mux000071 : LUT3
10495 
    generic map(
10496 
      INIT => X"E4"
10497 
    )
10498 
    port map (
10499 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
10500 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_7_Q,
10501 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_6_Q,
10502 
      O => huffman_ins_v2_code_black_11_mux0000_bdd5
10503 
    );
10504 
  huffman_ins_v2_code_black_11_mux000051 : LUT3
10505 
    generic map(
10506 
      INIT => X"E4"
10507 
    )
10508 
    port map (
10509 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
10510 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_5_Q,
10511 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_4_Q,
10512 
      O => huffman_ins_v2_code_black_11_mux0000_bdd3
10513 
    );
10514 
  huffman_ins_v2_code_black_11_mux000041 : LUT3
10515 
    generic map(
10516 
      INIT => X"E4"
10517 
    )
10518 
    port map (
10519 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
10520 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_3_Q,
10521 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_2_Q,
10522 
      O => huffman_ins_v2_code_black_11_mux0000_bdd2
10523 
    );
10524 
  huffman_ins_v2_code_black_11_mux000021 : LUT3
10525 
    generic map(
10526 
      INIT => X"E4"
10527 
    )
10528 
    port map (
10529 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
10530 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_1_Q,
10531 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_0_Q,
10532 
      O => huffman_ins_v2_code_black_11_mux0000_bdd0
10533 
    );
10534 
  huffman_ins_v2_code_black_10_mux000071 : LUT3
10535 
    generic map(
10536 
      INIT => X"E4"
10537 
    )
10538 
    port map (
10539 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
10540 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_6_Q,
10541 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_5_Q,
10542 
      O => huffman_ins_v2_code_black_10_mux0000_bdd5
10543 
    );
10544 
  huffman_ins_v2_code_black_10_mux000061 : LUT3
10545 
    generic map(
10546 
      INIT => X"E4"
10547 
    )
10548 
    port map (
10549 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
10550 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
10551 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_7_Q,
10552 
      O => huffman_ins_v2_code_black_10_mux0000_bdd4
10553 
    );
10554 
  huffman_ins_v2_code_black_10_mux000051 : LUT3
10555 
    generic map(
10556 
      INIT => X"E4"
10557 
    )
10558 
    port map (
10559 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
10560 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_4_Q,
10561 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_3_Q,
10562 
      O => huffman_ins_v2_code_black_10_mux0000_bdd3
10563 
    );
10564 
  huffman_ins_v2_code_black_10_mux000041 : LUT3
10565 
    generic map(
10566 
      INIT => X"E4"
10567 
    )
10568 
    port map (
10569 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
10570 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_2_Q,
10571 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_1_Q,
10572 
      O => huffman_ins_v2_code_black_10_mux0000_bdd2
10573 
    );
10574 
  huffman_ins_v2_code_black_1_mux00001_SW0 : LUT4
10575 
    generic map(
10576 
      INIT => X"8891"
10577 
    )
10578 
    port map (
10579 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
10580 
      I1 => huffman_ins_v2_codetab_ter_black_width(3),
10581 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
10582 
      I3 => huffman_ins_v2_codetab_ter_black_width(1),
10583 
      O => N18
10584 
    );
10585 
  huffman_ins_v2_code_black_1_mux00001 : LUT3
10586 
    generic map(
10587 
      INIT => X"E4"
10588 
    )
10589 
    port map (
10590 
      I0 => N18,
10591 
      I1 => huffman_ins_v2_ter_black_code(1),
10592 
      I2 => huffman_ins_v2_code_black(1),
10593 
      O => huffman_ins_v2_code_black_1_mux0000
10594 
    );
10595 
  huffman_ins_v2_code_black_0_mux00001 : LUT3
10596 
    generic map(
10597 
      INIT => X"E4"
10598 
    )
10599 
    port map (
10600 
      I0 => N18,
10601 
      I1 => huffman_ins_v2_ter_black_code(0),
10602 
      I2 => huffman_ins_v2_code_black(0),
10603 
      O => huffman_ins_v2_code_black_0_mux0000
10604 
    );
10605 
  huffman_ins_v2_code_black_23_mux0000112 : LUT4
10606 
    generic map(
10607 
      INIT => X"A820"
10608 
    )
10609 
    port map (
10610 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
10611 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
10612 
      I2 => huffman_ins_v2_code_black_15_mux0000_bdd1,
10613 
      I3 => huffman_ins_v2_code_black(23),
10614 
      O => huffman_ins_v2_code_black_23_mux0000112_1613
10615 
    );
10616 
  huffman_ins_v2_code_black_23_mux0000123 : LUT2
10617 
    generic map(
10618 
      INIT => X"2"
10619 
    )
10620 
    port map (
10621 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
10622 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
10623 
      O => huffman_ins_v2_code_black_22_mux0000123
10624 
    );
10625 
  huffman_ins_v2_code_black_23_mux0000128 : LUT4
10626 
    generic map(
10627 
      INIT => X"A820"
10628 
    )
10629 
    port map (
10630 
      I0 => huffman_ins_v2_code_black_22_mux0000123,
10631 
      I1 => huffman_ins_v2_codetab_ter_black_width(0),
10632 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
10633 
      I3 => huffman_ins_v2_code_black(23),
10634 
      O => huffman_ins_v2_code_black_23_mux0000128_1614
10635 
    );
10636 
  huffman_ins_v2_code_black_23_mux0000169 : LUT4
10637 
    generic map(
10638 
      INIT => X"0010"
10639 
    )
10640 
    port map (
10641 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
10642 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
10643 
      I2 => huffman_ins_v2_code_black(23),
10644 
      I3 => huffman_ins_v2_codetab_ter_black_width(1),
10645 
      O => huffman_ins_v2_code_black_23_mux0000169_1615
10646 
    );
10647 
  huffman_ins_v2_code_black_22_mux0000112 : LUT4
10648 
    generic map(
10649 
      INIT => X"A820"
10650 
    )
10651 
    port map (
10652 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
10653 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
10654 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
10655 
      I3 => huffman_ins_v2_code_black(22),
10656 
      O => huffman_ins_v2_code_black_22_mux0000112_1607
10657 
    );
10658 
  huffman_ins_v2_code_black_22_mux0000128 : LUT4
10659 
    generic map(
10660 
      INIT => X"A820"
10661 
    )
10662 
    port map (
10663 
      I0 => huffman_ins_v2_code_black_22_mux0000123,
10664 
      I1 => huffman_ins_v2_codetab_ter_black_width(0),
10665 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
10666 
      I3 => huffman_ins_v2_code_black(22),
10667 
      O => huffman_ins_v2_code_black_22_mux0000128_1609
10668 
    );
10669 
  huffman_ins_v2_code_black_22_mux0000169 : LUT4
10670 
    generic map(
10671 
      INIT => X"0010"
10672 
    )
10673 
    port map (
10674 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
10675 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
10676 
      I2 => huffman_ins_v2_code_black(22),
10677 
      I3 => huffman_ins_v2_codetab_ter_black_width(1),
10678 
      O => huffman_ins_v2_code_black_22_mux0000169_1610
10679 
    );
10680 
  huffman_ins_v2_code_black_3_mux000011 : LUT4
10681 
    generic map(
10682 
      INIT => X"FF57"
10683 
    )
10684 
    port map (
10685 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
10686 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
10687 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
10688 
      I3 => huffman_ins_v2_code_black(3),
10689 
      O => huffman_ins_v2_code_black_3_mux00001
10690 
    );
10691 
  huffman_ins_v2_code_black_3_mux000012 : LUT4
10692 
    generic map(
10693 
      INIT => X"C080"
10694 
    )
10695 
    port map (
10696 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
10697 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
10698 
      I2 => huffman_ins_v2_code_black(3),
10699 
      I3 => huffman_ins_v2_codetab_ter_black_width(0),
10700 
      O => huffman_ins_v2_code_black_3_mux000011_1629
10701 
    );
10702 
  huffman_ins_v2_code_black_3_mux00001_f5 : MUXF5
10703 
    port map (
10704 
      I0 => huffman_ins_v2_code_black_3_mux000011_1629,
10705 
      I1 => huffman_ins_v2_code_black_3_mux00001,
10706 
      S => huffman_ins_v2_ter_black_code(3),
10707 
      O => huffman_ins_v2_code_black_3_mux00001_f5_1632
10708 
    );
10709 
  huffman_ins_v2_code_black_3_mux000013 : LUT4
10710 
    generic map(
10711 
      INIT => X"FFE2"
10712 
    )
10713 
    port map (
10714 
      I0 => huffman_ins_v2_code_black(3),
10715 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
10716 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd0,
10717 
      I3 => huffman_ins_v2_codetab_ter_black_width(2),
10718 
      O => huffman_ins_v2_code_black_3_mux000012_1630
10719 
    );
10720 
  huffman_ins_v2_code_black_3_mux000014 : LUT4
10721 
    generic map(
10722 
      INIT => X"0E04"
10723 
    )
10724 
    port map (
10725 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
10726 
      I1 => huffman_ins_v2_code_black(3),
10727 
      I2 => huffman_ins_v2_codetab_ter_black_width(2),
10728 
      I3 => huffman_ins_v2_code_black_11_mux0000_bdd0,
10729 
      O => huffman_ins_v2_code_black_3_mux000013_1631
10730 
    );
10731 
  huffman_ins_v2_code_black_3_mux00001_f5_0 : MUXF5
10732 
    port map (
10733 
      I0 => huffman_ins_v2_code_black_3_mux000013_1631,
10734 
      I1 => huffman_ins_v2_code_black_3_mux000012_1630,
10735 
      S => huffman_ins_v2_ter_black_code(3),
10736 
      O => huffman_ins_v2_code_black_3_mux00001_f51
10737 
    );
10738 
  huffman_ins_v2_code_black_3_mux00001_f6 : MUXF6
10739 
    port map (
10740 
      I0 => huffman_ins_v2_code_black_3_mux00001_f51,
10741 
      I1 => huffman_ins_v2_code_black_3_mux00001_f5_1632,
10742 
      S => huffman_ins_v2_codetab_ter_black_width(3),
10743 
      O => huffman_ins_v2_code_black_3_mux0000
10744 
    );
10745 
  huffman_ins_v2_code_black_2_mux000021 : LUT4
10746 
    generic map(
10747 
      INIT => X"FF57"
10748 
    )
10749 
    port map (
10750 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
10751 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
10752 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
10753 
      I3 => huffman_ins_v2_code_black(2),
10754 
      O => huffman_ins_v2_code_black_2_mux00002
10755 
    );
10756 
  huffman_ins_v2_code_black_2_mux000022 : LUT4
10757 
    generic map(
10758 
      INIT => X"C080"
10759 
    )
10760 
    port map (
10761 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
10762 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
10763 
      I2 => huffman_ins_v2_code_black(2),
10764 
      I3 => huffman_ins_v2_codetab_ter_black_width(0),
10765 
      O => huffman_ins_v2_code_black_2_mux000021_1621
10766 
    );
10767 
  huffman_ins_v2_code_black_2_mux00002_f5 : MUXF5
10768 
    port map (
10769 
      I0 => huffman_ins_v2_code_black_2_mux000021_1621,
10770 
      I1 => huffman_ins_v2_code_black_2_mux00002,
10771 
      S => huffman_ins_v2_ter_black_code(2),
10772 
      O => huffman_ins_v2_code_black_2_mux00002_f5_1624
10773 
    );
10774 
  huffman_ins_v2_code_black_2_mux000023 : LUT4
10775 
    generic map(
10776 
      INIT => X"ABA8"
10777 
    )
10778 
    port map (
10779 
      I0 => huffman_ins_v2_ter_black_code(2),
10780 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
10781 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
10782 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_0_Q,
10783 
      O => huffman_ins_v2_code_black_2_mux000022_1622
10784 
    );
10785 
  huffman_ins_v2_code_black_2_mux000024 : LUT3
10786 
    generic map(
10787 
      INIT => X"E4"
10788 
    )
10789 
    port map (
10790 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
10791 
      I1 => huffman_ins_v2_code_black(2),
10792 
      I2 => huffman_ins_v2_ter_black_code(2),
10793 
      O => huffman_ins_v2_code_black_2_mux000023_1623
10794 
    );
10795 
  huffman_ins_v2_code_black_2_mux00002_f5_0 : MUXF5
10796 
    port map (
10797 
      I0 => huffman_ins_v2_code_black_2_mux000023_1623,
10798 
      I1 => huffman_ins_v2_code_black_2_mux000022_1622,
10799 
      S => huffman_ins_v2_codetab_ter_black_width(1),
10800 
      O => huffman_ins_v2_code_black_2_mux00002_f51
10801 
    );
10802 
  huffman_ins_v2_code_black_2_mux00002_f6 : MUXF6
10803 
    port map (
10804 
      I0 => huffman_ins_v2_code_black_2_mux00002_f51,
10805 
      I1 => huffman_ins_v2_code_black_2_mux00002_f5_1624,
10806 
      S => huffman_ins_v2_codetab_ter_black_width(3),
10807 
      O => huffman_ins_v2_code_black_2_mux0000
10808 
    );
10809 
  huffman_ins_v2_code_black_21_mux000011 : LUT4
10810 
    generic map(
10811 
      INIT => X"ABA8"
10812 
    )
10813 
    port map (
10814 
      I0 => huffman_ins_v2_code_black(21),
10815 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
10816 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
10817 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
10818 
      O => huffman_ins_v2_code_black_21_mux00001
10819 
    );
10820 
  huffman_ins_v2_code_black_21_mux00001_f5 : MUXF5
10821 
    port map (
10822 
      I0 => huffman_ins_v2_code_black_21_mux000011_1603,
10823 
      I1 => huffman_ins_v2_code_black_21_mux00001,
10824 
      S => huffman_ins_v2_codetab_ter_black_width(2),
10825 
      O => huffman_ins_v2_code_black_21_mux00001_f5_1605
10826 
    );
10827 
  huffman_ins_v2_code_black_21_mux000013 : LUT3
10828 
    generic map(
10829 
      INIT => X"10"
10830 
    )
10831 
    port map (
10832 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
10833 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
10834 
      I2 => huffman_ins_v2_code_black(21),
10835 
      O => huffman_ins_v2_code_black_21_mux000012_1604
10836 
    );
10837 
  huffman_ins_v2_code_black_21_mux00001_f6 : MUXF6
10838 
    port map (
10839 
      I0 => huffman_ins_v2_code_black_21_mux000012_1604,
10840 
      I1 => huffman_ins_v2_code_black_21_mux00001_f5_1605,
10841 
      S => huffman_ins_v2_codetab_ter_black_width(3),
10842 
      O => huffman_ins_v2_code_black_21_mux0000
10843 
    );
10844 
  huffman_ins_v2_code_black_20_mux0000187 : LUT4
10845 
    generic map(
10846 
      INIT => X"0010"
10847 
    )
10848 
    port map (
10849 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
10850 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
10851 
      I2 => huffman_ins_v2_code_black(20),
10852 
      I3 => huffman_ins_v2_codetab_ter_black_width(1),
10853 
      O => huffman_ins_v2_code_black_20_mux0000187_1599
10854 
    );
10855 
  huffman_ins_v2_code_black_5_mux000011 : LUT4
10856 
    generic map(
10857 
      INIT => X"FF57"
10858 
    )
10859 
    port map (
10860 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
10861 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
10862 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
10863 
      I3 => huffman_ins_v2_code_black(5),
10864 
      O => huffman_ins_v2_code_black_5_mux00001
10865 
    );
10866 
  huffman_ins_v2_code_black_5_mux000012 : LUT4
10867 
    generic map(
10868 
      INIT => X"C080"
10869 
    )
10870 
    port map (
10871 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
10872 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
10873 
      I2 => huffman_ins_v2_code_black(5),
10874 
      I3 => huffman_ins_v2_codetab_ter_black_width(0),
10875 
      O => huffman_ins_v2_code_black_5_mux000011_1645
10876 
    );
10877 
  huffman_ins_v2_code_black_5_mux00001_f5 : MUXF5
10878 
    port map (
10879 
      I0 => huffman_ins_v2_code_black_5_mux000011_1645,
10880 
      I1 => huffman_ins_v2_code_black_5_mux00001,
10881 
      S => huffman_ins_v2_ter_black_code(5),
10882 
      O => huffman_ins_v2_code_black_5_mux00001_f5_1648
10883 
    );
10884 
  huffman_ins_v2_code_black_5_mux000013 : LUT3
10885 
    generic map(
10886 
      INIT => X"E4"
10887 
    )
10888 
    port map (
10889 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
10890 
      I1 => huffman_ins_v2_code_black_11_mux0000_bdd0,
10891 
      I2 => huffman_ins_v2_ter_black_code(5),
10892 
      O => huffman_ins_v2_code_black_5_mux000012_1646
10893 
    );
10894 
  huffman_ins_v2_code_black_5_mux000014 : LUT3
10895 
    generic map(
10896 
      INIT => X"E4"
10897 
    )
10898 
    port map (
10899 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
10900 
      I1 => huffman_ins_v2_code_black(5),
10901 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd2,
10902 
      O => huffman_ins_v2_code_black_5_mux000013_1647
10903 
    );
10904 
  huffman_ins_v2_code_black_5_mux00001_f5_0 : MUXF5
10905 
    port map (
10906 
      I0 => huffman_ins_v2_code_black_5_mux000013_1647,
10907 
      I1 => huffman_ins_v2_code_black_5_mux000012_1646,
10908 
      S => huffman_ins_v2_codetab_ter_black_width(2),
10909 
      O => huffman_ins_v2_code_black_5_mux00001_f51
10910 
    );
10911 
  huffman_ins_v2_code_black_5_mux00001_f6 : MUXF6
10912 
    port map (
10913 
      I0 => huffman_ins_v2_code_black_5_mux00001_f51,
10914 
      I1 => huffman_ins_v2_code_black_5_mux00001_f5_1648,
10915 
      S => huffman_ins_v2_codetab_ter_black_width(3),
10916 
      O => huffman_ins_v2_code_black_5_mux0000
10917 
    );
10918 
  huffman_ins_v2_code_black_4_mux000011 : LUT4
10919 
    generic map(
10920 
      INIT => X"ABA8"
10921 
    )
10922 
    port map (
10923 
      I0 => huffman_ins_v2_code_black(4),
10924 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
10925 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
10926 
      I3 => huffman_ins_v2_ter_black_code(4),
10927 
      O => huffman_ins_v2_code_black_4_mux00001
10928 
    );
10929 
  huffman_ins_v2_code_black_4_mux000012 : LUT4
10930 
    generic map(
10931 
      INIT => X"ABA8"
10932 
    )
10933 
    port map (
10934 
      I0 => huffman_ins_v2_ter_black_code(4),
10935 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
10936 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
10937 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_0_Q,
10938 
      O => huffman_ins_v2_code_black_4_mux000011_1637
10939 
    );
10940 
  huffman_ins_v2_code_black_4_mux00001_f5 : MUXF5
10941 
    port map (
10942 
      I0 => huffman_ins_v2_code_black_4_mux000011_1637,
10943 
      I1 => huffman_ins_v2_code_black_4_mux00001,
10944 
      S => huffman_ins_v2_codetab_ter_black_width(3),
10945 
      O => huffman_ins_v2_code_black_4_mux00001_f5_1640
10946 
    );
10947 
  huffman_ins_v2_code_black_4_mux000013 : LUT4
10948 
    generic map(
10949 
      INIT => X"FFE2"
10950 
    )
10951 
    port map (
10952 
      I0 => huffman_ins_v2_code_black(4),
10953 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
10954 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd2,
10955 
      I3 => huffman_ins_v2_codetab_ter_black_width(3),
10956 
      O => huffman_ins_v2_code_black_4_mux000012_1638
10957 
    );
10958 
  huffman_ins_v2_code_black_4_mux000014 : LUT4
10959 
    generic map(
10960 
      INIT => X"0E04"
10961 
    )
10962 
    port map (
10963 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
10964 
      I1 => huffman_ins_v2_code_black(4),
10965 
      I2 => huffman_ins_v2_codetab_ter_black_width(3),
10966 
      I3 => huffman_ins_v2_code_black_10_mux0000_bdd2,
10967 
      O => huffman_ins_v2_code_black_4_mux000013_1639
10968 
    );
10969 
  huffman_ins_v2_code_black_4_mux00001_f5_0 : MUXF5
10970 
    port map (
10971 
      I0 => huffman_ins_v2_code_black_4_mux000013_1639,
10972 
      I1 => huffman_ins_v2_code_black_4_mux000012_1638,
10973 
      S => huffman_ins_v2_ter_black_code(4),
10974 
      O => huffman_ins_v2_code_black_4_mux00001_f51
10975 
    );
10976 
  huffman_ins_v2_code_black_4_mux00001_f6 : MUXF6
10977 
    port map (
10978 
      I0 => huffman_ins_v2_code_black_4_mux00001_f51,
10979 
      I1 => huffman_ins_v2_code_black_4_mux00001_f5_1640,
10980 
      S => huffman_ins_v2_codetab_ter_black_width(2),
10981 
      O => huffman_ins_v2_code_black_4_mux0000
10982 
    );
10983 
  huffman_ins_v2_code_black_19_mux000011 : LUT4
10984 
    generic map(
10985 
      INIT => X"ABA8"
10986 
    )
10987 
    port map (
10988 
      I0 => huffman_ins_v2_code_black(19),
10989 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
10990 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
10991 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_7_Q,
10992 
      O => huffman_ins_v2_code_black_19_mux00001
10993 
    );
10994 
  huffman_ins_v2_code_black_19_mux00001_f5 : MUXF5
10995 
    port map (
10996 
      I0 => huffman_ins_v2_code_black_19_mux00001_f5_rt_1594,
10997 
      I1 => huffman_ins_v2_code_black_19_mux00001,
10998 
      S => huffman_ins_v2_codetab_ter_black_width(2),
10999 
      O => huffman_ins_v2_code_black_19_mux00001_f5_1593
11000 
    );
11001 
  huffman_ins_v2_code_black_19_mux000012 : LUT4
11002 
    generic map(
11003 
      INIT => X"9810"
11004 
    )
11005 
    port map (
11006 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
11007 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
11008 
      I2 => huffman_ins_v2_code_black(19),
11009 
      I3 => huffman_ins_v2_code_black_15_mux0000_bdd1,
11010 
      O => huffman_ins_v2_code_black_19_mux000011_1592
11011 
    );
11012 
  huffman_ins_v2_code_black_19_mux00001_f6 : MUXF6
11013 
    port map (
11014 
      I0 => huffman_ins_v2_code_black_19_mux000011_1592,
11015 
      I1 => huffman_ins_v2_code_black_19_mux00001_f5_1593,
11016 
      S => huffman_ins_v2_codetab_ter_black_width(3),
11017 
      O => huffman_ins_v2_code_black_19_mux0000
11018 
    );
11019 
  huffman_ins_v2_code_black_18_mux000011 : LUT4
11020 
    generic map(
11021 
      INIT => X"ABA8"
11022 
    )
11023 
    port map (
11024 
      I0 => huffman_ins_v2_code_black(18),
11025 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
11026 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
11027 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_6_Q,
11028 
      O => huffman_ins_v2_code_black_18_mux00001
11029 
    );
11030 
  huffman_ins_v2_code_black_18_mux00001_f5 : MUXF5
11031 
    port map (
11032 
      I0 => huffman_ins_v2_code_black_18_mux000011_1586,
11033 
      I1 => huffman_ins_v2_code_black_18_mux00001,
11034 
      S => huffman_ins_v2_codetab_ter_black_width(2),
11035 
      O => huffman_ins_v2_code_black_18_mux00001_f5_1588
11036 
    );
11037 
  huffman_ins_v2_code_black_18_mux000013 : LUT4
11038 
    generic map(
11039 
      INIT => X"9810"
11040 
    )
11041 
    port map (
11042 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
11043 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
11044 
      I2 => huffman_ins_v2_code_black(18),
11045 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
11046 
      O => huffman_ins_v2_code_black_18_mux000012_1587
11047 
    );
11048 
  huffman_ins_v2_code_black_18_mux00001_f6 : MUXF6
11049 
    port map (
11050 
      I0 => huffman_ins_v2_code_black_18_mux000012_1587,
11051 
      I1 => huffman_ins_v2_code_black_18_mux00001_f5_1588,
11052 
      S => huffman_ins_v2_codetab_ter_black_width(3),
11053 
      O => huffman_ins_v2_code_black_18_mux0000
11054 
    );
11055 
  huffman_ins_v2_code_black_7_mux000011 : LUT4
11056 
    generic map(
11057 
      INIT => X"FF57"
11058 
    )
11059 
    port map (
11060 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
11061 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
11062 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
11063 
      I3 => huffman_ins_v2_code_black(7),
11064 
      O => huffman_ins_v2_code_black_7_mux00001
11065 
    );
11066 
  huffman_ins_v2_code_black_7_mux000012 : LUT4
11067 
    generic map(
11068 
      INIT => X"C080"
11069 
    )
11070 
    port map (
11071 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11072 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
11073 
      I2 => huffman_ins_v2_code_black(7),
11074 
      I3 => huffman_ins_v2_codetab_ter_black_width(0),
11075 
      O => huffman_ins_v2_code_black_7_mux000011_1658
11076 
    );
11077 
  huffman_ins_v2_code_black_7_mux00001_f5 : MUXF5
11078 
    port map (
11079 
      I0 => huffman_ins_v2_code_black_7_mux000011_1658,
11080 
      I1 => huffman_ins_v2_code_black_7_mux00001,
11081 
      S => huffman_ins_v2_ter_black_code(7),
11082 
      O => huffman_ins_v2_code_black_7_mux00001_f5_1661
11083 
    );
11084 
  huffman_ins_v2_code_black_7_mux000013 : LUT3
11085 
    generic map(
11086 
      INIT => X"E4"
11087 
    )
11088 
    port map (
11089 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11090 
      I1 => huffman_ins_v2_code_black_11_mux0000_bdd2,
11091 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd0,
11092 
      O => huffman_ins_v2_code_black_7_mux000012_1659
11093 
    );
11094 
  huffman_ins_v2_code_black_7_mux000014 : LUT3
11095 
    generic map(
11096 
      INIT => X"E4"
11097 
    )
11098 
    port map (
11099 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11100 
      I1 => huffman_ins_v2_code_black(7),
11101 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd3,
11102 
      O => huffman_ins_v2_code_black_7_mux000013_1660
11103 
    );
11104 
  huffman_ins_v2_code_black_7_mux00001_f5_0 : MUXF5
11105 
    port map (
11106 
      I0 => huffman_ins_v2_code_black_7_mux000013_1660,
11107 
      I1 => huffman_ins_v2_code_black_7_mux000012_1659,
11108 
      S => huffman_ins_v2_codetab_ter_black_width(2),
11109 
      O => huffman_ins_v2_code_black_7_mux00001_f51
11110 
    );
11111 
  huffman_ins_v2_code_black_7_mux00001_f6 : MUXF6
11112 
    port map (
11113 
      I0 => huffman_ins_v2_code_black_7_mux00001_f51,
11114 
      I1 => huffman_ins_v2_code_black_7_mux00001_f5_1661,
11115 
      S => huffman_ins_v2_codetab_ter_black_width(3),
11116 
      O => huffman_ins_v2_code_black_7_mux0000
11117 
    );
11118 
  huffman_ins_v2_code_black_6_mux0000282 : LUT3
11119 
    generic map(
11120 
      INIT => X"E4"
11121 
    )
11122 
    port map (
11123 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
11124 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_0_Q,
11125 
      I2 => huffman_ins_v2_ter_black_code(6),
11126 
      O => huffman_ins_v2_code_black_6_mux0000282_1654
11127 
    );
11128 
  huffman_ins_v2_code_black_17_mux000011 : LUT4
11129 
    generic map(
11130 
      INIT => X"ABA8"
11131 
    )
11132 
    port map (
11133 
      I0 => huffman_ins_v2_code_black(17),
11134 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
11135 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
11136 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_5_Q,
11137 
      O => huffman_ins_v2_code_black_17_mux00001
11138 
    );
11139 
  huffman_ins_v2_code_black_17_mux000012 : LUT3
11140 
    generic map(
11141 
      INIT => X"E4"
11142 
    )
11143 
    port map (
11144 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11145 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
11146 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd5,
11147 
      O => huffman_ins_v2_code_black_17_mux000011_1578
11148 
    );
11149 
  huffman_ins_v2_code_black_17_mux00001_f5 : MUXF5
11150 
    port map (
11151 
      I0 => huffman_ins_v2_code_black_17_mux000011_1578,
11152 
      I1 => huffman_ins_v2_code_black_17_mux00001,
11153 
      S => huffman_ins_v2_codetab_ter_black_width(2),
11154 
      O => huffman_ins_v2_code_black_17_mux00001_f5_1581
11155 
    );
11156 
  huffman_ins_v2_code_black_17_mux000013 : LUT4
11157 
    generic map(
11158 
      INIT => X"DC54"
11159 
    )
11160 
    port map (
11161 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11162 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
11163 
      I2 => huffman_ins_v2_code_black(17),
11164 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
11165 
      O => huffman_ins_v2_code_black_17_mux000012_1579
11166 
    );
11167 
  huffman_ins_v2_code_black_17_mux000014 : LUT4
11168 
    generic map(
11169 
      INIT => X"9810"
11170 
    )
11171 
    port map (
11172 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
11173 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
11174 
      I2 => huffman_ins_v2_code_black(17),
11175 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
11176 
      O => huffman_ins_v2_code_black_17_mux000013_1580
11177 
    );
11178 
  huffman_ins_v2_code_black_17_mux00001_f5_0 : MUXF5
11179 
    port map (
11180 
      I0 => huffman_ins_v2_code_black_17_mux000013_1580,
11181 
      I1 => huffman_ins_v2_code_black_17_mux000012_1579,
11182 
      S => huffman_ins_v2_code_black_15_mux0000_bdd1,
11183 
      O => huffman_ins_v2_code_black_17_mux00001_f51
11184 
    );
11185 
  huffman_ins_v2_code_black_17_mux00001_f6 : MUXF6
11186 
    port map (
11187 
      I0 => huffman_ins_v2_code_black_17_mux00001_f51,
11188 
      I1 => huffman_ins_v2_code_black_17_mux00001_f5_1581,
11189 
      S => huffman_ins_v2_codetab_ter_black_width(3),
11190 
      O => huffman_ins_v2_code_black_17_mux0000
11191 
    );
11192 
  huffman_ins_v2_code_black_16_mux000011 : LUT4
11193 
    generic map(
11194 
      INIT => X"ABA8"
11195 
    )
11196 
    port map (
11197 
      I0 => huffman_ins_v2_code_black(16),
11198 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
11199 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
11200 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_4_Q,
11201 
      O => huffman_ins_v2_code_black_16_mux00001
11202 
    );
11203 
  huffman_ins_v2_code_black_16_mux000012 : LUT3
11204 
    generic map(
11205 
      INIT => X"E4"
11206 
    )
11207 
    port map (
11208 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11209 
      I1 => huffman_ins_v2_code_black_10_mux0000_bdd4,
11210 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd5,
11211 
      O => huffman_ins_v2_code_black_16_mux000011_1572
11212 
    );
11213 
  huffman_ins_v2_code_black_16_mux00001_f5 : MUXF5
11214 
    port map (
11215 
      I0 => huffman_ins_v2_code_black_16_mux000011_1572,
11216 
      I1 => huffman_ins_v2_code_black_16_mux00001,
11217 
      S => huffman_ins_v2_codetab_ter_black_width(2),
11218 
      O => huffman_ins_v2_code_black_16_mux00001_f5_1574
11219 
    );
11220 
  huffman_ins_v2_code_black_16_mux000013 : LUT4
11221 
    generic map(
11222 
      INIT => X"AE04"
11223 
    )
11224 
    port map (
11225 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
11226 
      I1 => huffman_ins_v2_code_black(16),
11227 
      I2 => huffman_ins_v2_codetab_ter_black_width(1),
11228 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
11229 
      O => huffman_ins_v2_code_black_16_mux000012_1573
11230 
    );
11231 
  huffman_ins_v2_code_black_16_mux00001_f6 : MUXF6
11232 
    port map (
11233 
      I0 => huffman_ins_v2_code_black_16_mux000012_1573,
11234 
      I1 => huffman_ins_v2_code_black_16_mux00001_f5_1574,
11235 
      S => huffman_ins_v2_codetab_ter_black_width(3),
11236 
      O => huffman_ins_v2_code_black_16_mux0000
11237 
    );
11238 
  huffman_ins_v2_code_black_9_mux0000212 : LUT4
11239 
    generic map(
11240 
      INIT => X"A820"
11241 
    )
11242 
    port map (
11243 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11244 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
11245 
      I2 => huffman_ins_v2_ter_black_code(9),
11246 
      I3 => huffman_ins_v2_code_black(9),
11247 
      O => huffman_ins_v2_code_black_9_mux0000212_1670
11248 
    );
11249 
  huffman_ins_v2_code_black_9_mux00002135 : LUT4
11250 
    generic map(
11251 
      INIT => X"FAD8"
11252 
    )
11253 
    port map (
11254 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
11255 
      I1 => huffman_ins_v2_code_black_9_mux0000212_1670,
11256 
      I2 => huffman_ins_v2_code_black_9_mux00002107_1669,
11257 
      I3 => huffman_ins_v2_code_black_9_mux0000243,
11258 
      O => huffman_ins_v2_code_black_9_mux0000
11259 
    );
11260 
  huffman_ins_v2_code_black_8_mux00001153 : LUT3
11261 
    generic map(
11262 
      INIT => X"E4"
11263 
    )
11264 
    port map (
11265 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
11266 
      I1 => huffman_ins_v2_code_black_8_mux00001126_1665,
11267 
      I2 => huffman_ins_v2_code_black_8_mux0000172_1666,
11268 
      O => huffman_ins_v2_code_black_8_mux0000
11269 
    );
11270 
  huffman_ins_v2_code_black_15_mux0000112 : LUT4
11271 
    generic map(
11272 
      INIT => X"A820"
11273 
    )
11274 
    port map (
11275 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11276 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
11277 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd3,
11278 
      I3 => huffman_ins_v2_code_black(15),
11279 
      O => huffman_ins_v2_code_black_15_mux0000112_1564
11280 
    );
11281 
  huffman_ins_v2_code_black_15_mux00001135 : LUT4
11282 
    generic map(
11283 
      INIT => X"FAD8"
11284 
    )
11285 
    port map (
11286 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
11287 
      I1 => huffman_ins_v2_code_black_15_mux0000112_1564,
11288 
      I2 => huffman_ins_v2_code_black_15_mux00001107,
11289 
      I3 => huffman_ins_v2_code_black_15_mux0000143,
11290 
      O => huffman_ins_v2_code_black_15_mux0000
11291 
    );
11292 
  huffman_ins_v2_code_black_14_mux0000112 : LUT4
11293 
    generic map(
11294 
      INIT => X"A820"
11295 
    )
11296 
    port map (
11297 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11298 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
11299 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd3,
11300 
      I3 => huffman_ins_v2_code_black(14),
11301 
      O => huffman_ins_v2_code_black_14_mux0000112_1555
11302 
    );
11303 
  huffman_ins_v2_code_black_14_mux00001135 : LUT4
11304 
    generic map(
11305 
      INIT => X"FAD8"
11306 
    )
11307 
    port map (
11308 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
11309 
      I1 => huffman_ins_v2_code_black_14_mux0000112_1555,
11310 
      I2 => huffman_ins_v2_code_black_14_mux00001107_1554,
11311 
      I3 => huffman_ins_v2_code_black_14_mux0000143,
11312 
      O => huffman_ins_v2_code_black_14_mux0000
11313 
    );
11314 
  huffman_ins_v2_code_black_13_mux0000112 : LUT4
11315 
    generic map(
11316 
      INIT => X"A820"
11317 
    )
11318 
    port map (
11319 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11320 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
11321 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd2,
11322 
      I3 => huffman_ins_v2_code_black(13),
11323 
      O => huffman_ins_v2_code_black_13_mux0000112_1548
11324 
    );
11325 
  huffman_ins_v2_code_black_13_mux00001135 : LUT4
11326 
    generic map(
11327 
      INIT => X"FAD8"
11328 
    )
11329 
    port map (
11330 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
11331 
      I1 => huffman_ins_v2_code_black_13_mux0000112_1548,
11332 
      I2 => huffman_ins_v2_code_black_13_mux00001107_1547,
11333 
      I3 => huffman_ins_v2_code_black_13_mux0000143,
11334 
      O => huffman_ins_v2_code_black_13_mux0000
11335 
    );
11336 
  huffman_ins_v2_code_black_12_mux0000112 : LUT4
11337 
    generic map(
11338 
      INIT => X"A820"
11339 
    )
11340 
    port map (
11341 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11342 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
11343 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd2,
11344 
      I3 => huffman_ins_v2_code_black(12),
11345 
      O => huffman_ins_v2_code_black_12_mux0000112_1541
11346 
    );
11347 
  huffman_ins_v2_code_black_12_mux00001135 : LUT4
11348 
    generic map(
11349 
      INIT => X"FAD8"
11350 
    )
11351 
    port map (
11352 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
11353 
      I1 => huffman_ins_v2_code_black_12_mux0000112_1541,
11354 
      I2 => huffman_ins_v2_code_black_12_mux00001107_1540,
11355 
      I3 => huffman_ins_v2_code_black_12_mux0000143,
11356 
      O => huffman_ins_v2_code_black_12_mux0000
11357 
    );
11358 
  huffman_ins_v2_code_black_11_mux0000112 : LUT4
11359 
    generic map(
11360 
      INIT => X"A820"
11361 
    )
11362 
    port map (
11363 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
11364 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
11365 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd0,
11366 
      I3 => huffman_ins_v2_code_black(11),
11367 
      O => huffman_ins_v2_code_black_11_mux0000112_1530
11368 
    );
11369 
  huffman_ins_v2_code_black_11_mux00001135 : LUT4
11370 
    generic map(
11371 
      INIT => X"FAD8"
11372 
    )
11373 
    port map (
11374 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
11375 
      I1 => huffman_ins_v2_code_black_11_mux0000112_1530,
11376 
      I2 => huffman_ins_v2_code_black_11_mux00001107_1529,
11377 
      I3 => huffman_ins_v2_code_black_11_mux0000143,
11378 
      O => huffman_ins_v2_code_black_11_mux0000
11379 
    );
11380 
  huffman_ins_v2_code_black_10_mux000010 : LUT2
11381 
    generic map(
11382 
      INIT => X"8"
11383 
    )
11384 
    port map (
11385 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
11386 
      I1 => huffman_ins_v2_code_black(10),
11387 
      O => huffman_ins_v2_code_black_10_mux000010_1516
11388 
    );
11389 
  huffman_ins_v2_code_black_10_mux0000115 : LUT4
11390 
    generic map(
11391 
      INIT => X"0E04"
11392 
    )
11393 
    port map (
11394 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
11395 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_0_Q,
11396 
      I2 => huffman_ins_v2_codetab_ter_black_width(2),
11397 
      I3 => huffman_ins_v2_ter_black_code(10),
11398 
      O => huffman_ins_v2_code_black_10_mux0000115_1519
11399 
    );
11400 
  huffman_ins_v2_code_black_10_mux00001103 : LUT3
11401 
    generic map(
11402 
      INIT => X"E4"
11403 
    )
11404 
    port map (
11405 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
11406 
      I1 => huffman_ins_v2_code_black_10_mux0000_bdd4,
11407 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd3,
11408 
      O => huffman_ins_v2_code_black_10_mux00001103_1517
11409 
    );
11410 
  huffman_ins_v2_code_black_10_mux00001116 : LUT3
11411 
    generic map(
11412 
      INIT => X"E4"
11413 
    )
11414 
    port map (
11415 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
11416 
      I1 => huffman_ins_v2_code_black(10),
11417 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd5,
11418 
      O => huffman_ins_v2_code_black_10_mux00001116_1518
11419 
    );
11420 
  fax4_ins_state_updated_mux000824 : LUT4
11421 
    generic map(
11422 
      INIT => X"0001"
11423 
    )
11424 
    port map (
11425 
      I0 => fax4_ins_state_FSM_FFd5_1333,
11426 
      I1 => fax4_ins_state_FSM_FFd10_1323,
11427 
      I2 => fax4_ins_state_FSM_FFd11_1325,
11428 
      I3 => fax4_ins_state_FSM_FFd8_1338,
11429 
      O => fax4_ins_state_updated_mux000824_1346
11430 
    );
11431 
  fax4_ins_FIFO2_multi_read_ins_mux2_and000011 : LUT3
11432 
    generic map(
11433 
      INIT => X"01"
11434 
    )
11435 
    port map (
11436 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(2),
11437 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(1),
11438 
      I2 => fax4_ins_FIFO2_multi_read_ins_N4,
11439 
      O => fax4_ins_FIFO2_multi_read_ins_N7
11440 
    );
11441 
  fax4_ins_FIFO1_multi_read_ins_mux2_and000011 : LUT3
11442 
    generic map(
11443 
      INIT => X"01"
11444 
    )
11445 
    port map (
11446 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(2),
11447 
      I1 => fax4_ins_FIFO1_multi_read_ins_used(1),
11448 
      I2 => fax4_ins_FIFO1_multi_read_ins_N4,
11449 
      O => fax4_ins_FIFO1_multi_read_ins_N7
11450 
    );
11451 
  fax4_ins_FIFO2_multi_read_ins_mem_rd11_SW0 : LUT4
11452 
    generic map(
11453 
      INIT => X"FFFE"
11454 
    )
11455 
    port map (
11456 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(6),
11457 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(4),
11458 
      I2 => fax4_ins_FIFO2_multi_read_ins_used(3),
11459 
      I3 => fax4_ins_FIFO2_multi_read_ins_used(5),
11460 
      O => N24
11461 
    );
11462 
  fax4_ins_FIFO2_multi_read_ins_mem_rd11 : LUT4
11463 
    generic map(
11464 
      INIT => X"FFFE"
11465 
    )
11466 
    port map (
11467 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(9),
11468 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(8),
11469 
      I2 => fax4_ins_FIFO2_multi_read_ins_used(7),
11470 
      I3 => N24,
11471 
      O => fax4_ins_FIFO2_multi_read_ins_N4
11472 
    );
11473 
  fax4_ins_FIFO1_multi_read_ins_mem_rd11_SW0 : LUT4
11474 
    generic map(
11475 
      INIT => X"FFFE"
11476 
    )
11477 
    port map (
11478 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(6),
11479 
      I1 => fax4_ins_FIFO1_multi_read_ins_used(4),
11480 
      I2 => fax4_ins_FIFO1_multi_read_ins_used(3),
11481 
      I3 => fax4_ins_FIFO1_multi_read_ins_used(5),
11482 
      O => N26
11483 
    );
11484 
  fax4_ins_FIFO1_multi_read_ins_mem_rd11 : LUT4
11485 
    generic map(
11486 
      INIT => X"FFFE"
11487 
    )
11488 
    port map (
11489 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(9),
11490 
      I1 => fax4_ins_FIFO1_multi_read_ins_used(8),
11491 
      I2 => fax4_ins_FIFO1_multi_read_ins_used(7),
11492 
      I3 => N26,
11493 
      O => fax4_ins_FIFO1_multi_read_ins_N4
11494 
    );
11495 
  huffman_ins_v2_mux_code_white_width_2_1 : LUT3
11496 
    generic map(
11497 
      INIT => X"E4"
11498 
    )
11499 
    port map (
11500 
      I0 => huffman_ins_v2_a0_value_2_1510,
11501 
      I1 => huffman_ins_v2_code_black_width(2),
11502 
      I2 => huffman_ins_v2_code_white_width(2),
11503 
      O => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2)
11504 
    );
11505 
  huffman_ins_v2_mux_code_white_width_1_1 : LUT3
11506 
    generic map(
11507 
      INIT => X"E4"
11508 
    )
11509 
    port map (
11510 
      I0 => huffman_ins_v2_a0_value_2_1510,
11511 
      I1 => huffman_ins_v2_code_black_width(1),
11512 
      I2 => huffman_ins_v2_code_white_width(1),
11513 
      O => huffman_ins_v2_mux_code_white_width(1)
11514 
    );
11515 
  huffman_ins_v2_mux_code_black_width_2_1 : LUT3
11516 
    generic map(
11517 
      INIT => X"E4"
11518 
    )
11519 
    port map (
11520 
      I0 => huffman_ins_v2_a0_value_2_1510,
11521 
      I1 => huffman_ins_v2_code_white_width(2),
11522 
      I2 => huffman_ins_v2_code_black_width(2),
11523 
      O => huffman_ins_v2_mux_code_black_width(2)
11524 
    );
11525 
  huffman_ins_v2_mux_code_black_width_1_1 : LUT3
11526 
    generic map(
11527 
      INIT => X"E4"
11528 
    )
11529 
    port map (
11530 
      I0 => huffman_ins_v2_a0_value_2_1510,
11531 
      I1 => huffman_ins_v2_code_white_width(1),
11532 
      I2 => huffman_ins_v2_code_black_width(1),
11533 
      O => huffman_ins_v2_mux_code_black_width(1)
11534 
    );
11535 
  huffman_ins_v2_hor_code_6_mux000327 : LUT4
11536 
    generic map(
11537 
      INIT => X"2000"
11538 
    )
11539 
    port map (
11540 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
11541 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
11542 
      I2 => huffman_ins_v2_mux_code_white_width(1),
11543 
      I3 => huffman_ins_v2_N100,
11544 
      O => huffman_ins_v2_hor_code_6_mux000327_2015
11545 
    );
11546 
  huffman_ins_v2_hor_code_6_mux000329 : LUT3
11547 
    generic map(
11548 
      INIT => X"EA"
11549 
    )
11550 
    port map (
11551 
      I0 => huffman_ins_v2_hor_code_6_mux000327_2015,
11552 
      I1 => huffman_ins_v2_hor_code(6),
11553 
      I2 => huffman_ins_v2_hor_code_6_mux000310_2014,
11554 
      O => huffman_ins_v2_hor_code_6_mux000329_2016
11555 
    );
11556 
  huffman_ins_v2_hor_code_6_mux000367 : LUT4
11557 
    generic map(
11558 
      INIT => X"AA80"
11559 
    )
11560 
    port map (
11561 
      I0 => huffman_ins_v2_code_black(6),
11562 
      I1 => huffman_ins_v2_N103,
11563 
      I2 => huffman_ins_v2_N39,
11564 
      I3 => huffman_ins_v2_hor_code_6_mux000361_2018,
11565 
      O => huffman_ins_v2_hor_code_6_mux000367_2019
11566 
    );
11567 
  fax4_ins_FIFO2_multi_read_ins_mux3_valid1 : LUT3
11568 
    generic map(
11569 
      INIT => X"FE"
11570 
    )
11571 
    port map (
11572 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11573 
      I1 => fax4_ins_FIFO2_multi_read_ins_N4,
11574 
      I2 => fax4_ins_FIFO2_multi_read_ins_used(2),
11575 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_valid
11576 
    );
11577 
  fax4_ins_FIFO1_multi_read_ins_mux3_valid1 : LUT3
11578 
    generic map(
11579 
      INIT => X"FE"
11580 
    )
11581 
    port map (
11582 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11583 
      I1 => fax4_ins_FIFO1_multi_read_ins_N4,
11584 
      I2 => fax4_ins_FIFO1_multi_read_ins_used(2),
11585 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_valid
11586 
    );
11587 
  fax4_ins_FIFO2_multi_read_ins_mux3_x_9_1 : LUT3
11588 
    generic map(
11589 
      INIT => X"E4"
11590 
    )
11591 
    port map (
11592 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11593 
      I1 => fax4_ins_FIFO2_multi_read_ins_mem_data_out(9),
11594 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
11595 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_x(9)
11596 
    );
11597 
  fax4_ins_FIFO2_multi_read_ins_mux3_x_8_1 : LUT3
11598 
    generic map(
11599 
      INIT => X"E4"
11600 
    )
11601 
    port map (
11602 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11603 
      I1 => fax4_ins_FIFO2_multi_read_ins_mem_data_out(8),
11604 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
11605 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_x(8)
11606 
    );
11607 
  fax4_ins_FIFO2_multi_read_ins_mux3_x_7_1 : LUT3
11608 
    generic map(
11609 
      INIT => X"E4"
11610 
    )
11611 
    port map (
11612 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11613 
      I1 => fax4_ins_FIFO2_multi_read_ins_mem_data_out(7),
11614 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
11615 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_x(7)
11616 
    );
11617 
  fax4_ins_FIFO2_multi_read_ins_mux3_x_6_1 : LUT3
11618 
    generic map(
11619 
      INIT => X"E4"
11620 
    )
11621 
    port map (
11622 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11623 
      I1 => fax4_ins_FIFO2_multi_read_ins_mem_data_out(6),
11624 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
11625 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_x(6)
11626 
    );
11627 
  fax4_ins_FIFO2_multi_read_ins_mux3_x_5_1 : LUT3
11628 
    generic map(
11629 
      INIT => X"E4"
11630 
    )
11631 
    port map (
11632 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11633 
      I1 => fax4_ins_FIFO2_multi_read_ins_mem_data_out(5),
11634 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
11635 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_x(5)
11636 
    );
11637 
  fax4_ins_FIFO2_multi_read_ins_mux3_x_4_1 : LUT3
11638 
    generic map(
11639 
      INIT => X"E4"
11640 
    )
11641 
    port map (
11642 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11643 
      I1 => fax4_ins_FIFO2_multi_read_ins_mem_data_out(4),
11644 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
11645 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_x(4)
11646 
    );
11647 
  fax4_ins_FIFO2_multi_read_ins_mux3_x_3_1 : LUT3
11648 
    generic map(
11649 
      INIT => X"E4"
11650 
    )
11651 
    port map (
11652 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11653 
      I1 => fax4_ins_FIFO2_multi_read_ins_mem_data_out(3),
11654 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
11655 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_x(3)
11656 
    );
11657 
  fax4_ins_FIFO2_multi_read_ins_mux3_x_2_1 : LUT3
11658 
    generic map(
11659 
      INIT => X"E4"
11660 
    )
11661 
    port map (
11662 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11663 
      I1 => fax4_ins_FIFO2_multi_read_ins_mem_data_out(2),
11664 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
11665 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_x(2)
11666 
    );
11667 
  fax4_ins_FIFO2_multi_read_ins_mux3_x_1_1 : LUT3
11668 
    generic map(
11669 
      INIT => X"E4"
11670 
    )
11671 
    port map (
11672 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11673 
      I1 => fax4_ins_FIFO2_multi_read_ins_mem_data_out(1),
11674 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
11675 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_x(1)
11676 
    );
11677 
  fax4_ins_FIFO2_multi_read_ins_mux3_x_0_1 : LUT3
11678 
    generic map(
11679 
      INIT => X"E4"
11680 
    )
11681 
    port map (
11682 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11683 
      I1 => fax4_ins_FIFO2_multi_read_ins_mem_data_out(0),
11684 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
11685 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_x(0)
11686 
    );
11687 
  fax4_ins_FIFO2_multi_read_ins_mux3_to_white1 : LUT3
11688 
    generic map(
11689 
      INIT => X"E4"
11690 
    )
11691 
    port map (
11692 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
11693 
      I1 => fax4_ins_FIFO2_multi_read_ins_mem_data_out(10),
11694 
      I2 => fax4_ins_to_white_1349,
11695 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_to_white
11696 
    );
11697 
  fax4_ins_FIFO1_multi_read_ins_mux3_x_9_1 : LUT3
11698 
    generic map(
11699 
      INIT => X"E4"
11700 
    )
11701 
    port map (
11702 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11703 
      I1 => fax4_ins_FIFO1_multi_read_ins_mem_data_out(9),
11704 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
11705 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_x(9)
11706 
    );
11707 
  fax4_ins_FIFO1_multi_read_ins_mux3_x_8_1 : LUT3
11708 
    generic map(
11709 
      INIT => X"E4"
11710 
    )
11711 
    port map (
11712 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11713 
      I1 => fax4_ins_FIFO1_multi_read_ins_mem_data_out(8),
11714 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
11715 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_x(8)
11716 
    );
11717 
  fax4_ins_FIFO1_multi_read_ins_mux3_x_7_1 : LUT3
11718 
    generic map(
11719 
      INIT => X"E4"
11720 
    )
11721 
    port map (
11722 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11723 
      I1 => fax4_ins_FIFO1_multi_read_ins_mem_data_out(7),
11724 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
11725 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_x(7)
11726 
    );
11727 
  fax4_ins_FIFO1_multi_read_ins_mux3_x_6_1 : LUT3
11728 
    generic map(
11729 
      INIT => X"E4"
11730 
    )
11731 
    port map (
11732 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11733 
      I1 => fax4_ins_FIFO1_multi_read_ins_mem_data_out(6),
11734 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
11735 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_x(6)
11736 
    );
11737 
  fax4_ins_FIFO1_multi_read_ins_mux3_x_5_1 : LUT3
11738 
    generic map(
11739 
      INIT => X"E4"
11740 
    )
11741 
    port map (
11742 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11743 
      I1 => fax4_ins_FIFO1_multi_read_ins_mem_data_out(5),
11744 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
11745 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_x(5)
11746 
    );
11747 
  fax4_ins_FIFO1_multi_read_ins_mux3_x_4_1 : LUT3
11748 
    generic map(
11749 
      INIT => X"E4"
11750 
    )
11751 
    port map (
11752 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11753 
      I1 => fax4_ins_FIFO1_multi_read_ins_mem_data_out(4),
11754 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
11755 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_x(4)
11756 
    );
11757 
  fax4_ins_FIFO1_multi_read_ins_mux3_x_3_1 : LUT3
11758 
    generic map(
11759 
      INIT => X"E4"
11760 
    )
11761 
    port map (
11762 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11763 
      I1 => fax4_ins_FIFO1_multi_read_ins_mem_data_out(3),
11764 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
11765 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_x(3)
11766 
    );
11767 
  fax4_ins_FIFO1_multi_read_ins_mux3_x_2_1 : LUT3
11768 
    generic map(
11769 
      INIT => X"E4"
11770 
    )
11771 
    port map (
11772 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11773 
      I1 => fax4_ins_FIFO1_multi_read_ins_mem_data_out(2),
11774 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
11775 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_x(2)
11776 
    );
11777 
  fax4_ins_FIFO1_multi_read_ins_mux3_x_1_1 : LUT3
11778 
    generic map(
11779 
      INIT => X"E4"
11780 
    )
11781 
    port map (
11782 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11783 
      I1 => fax4_ins_FIFO1_multi_read_ins_mem_data_out(1),
11784 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
11785 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_x(1)
11786 
    );
11787 
  fax4_ins_FIFO1_multi_read_ins_mux3_x_0_1 : LUT3
11788 
    generic map(
11789 
      INIT => X"E4"
11790 
    )
11791 
    port map (
11792 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11793 
      I1 => fax4_ins_FIFO1_multi_read_ins_mem_data_out(0),
11794 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
11795 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_x(0)
11796 
    );
11797 
  fax4_ins_FIFO1_multi_read_ins_mux3_to_white1 : LUT3
11798 
    generic map(
11799 
      INIT => X"E4"
11800 
    )
11801 
    port map (
11802 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux3,
11803 
      I1 => fax4_ins_FIFO1_multi_read_ins_mem_data_out(10),
11804 
      I2 => fax4_ins_to_white_1349,
11805 
      O => fax4_ins_FIFO1_multi_read_ins_mux3_to_white
11806 
    );
11807 
  huffman_ins_v2_run_length_black_1_1 : LUT3
11808 
    generic map(
11809 
      INIT => X"E4"
11810 
    )
11811 
    port map (
11812 
      I0 => fax4_ins_a0_value_o_950,
11813 
      I1 => huffman_ins_v2_run_length_white_sub0000(1),
11814 
      I2 => huffman_ins_v2_run_length_white_sub0001(1),
11815 
      O => huffman_ins_v2_run_length_black(1)
11816 
    );
11817 
  huffman_ins_v2_run_length_black_2_1 : LUT3
11818 
    generic map(
11819 
      INIT => X"E4"
11820 
    )
11821 
    port map (
11822 
      I0 => fax4_ins_a0_value_o_950,
11823 
      I1 => huffman_ins_v2_run_length_white_sub0000(2),
11824 
      I2 => huffman_ins_v2_run_length_white_sub0001(2),
11825 
      O => huffman_ins_v2_run_length_black(2)
11826 
    );
11827 
  huffman_ins_v2_run_length_black_3_1 : LUT3
11828 
    generic map(
11829 
      INIT => X"E4"
11830 
    )
11831 
    port map (
11832 
      I0 => fax4_ins_a0_value_o_950,
11833 
      I1 => huffman_ins_v2_run_length_white_sub0000(3),
11834 
      I2 => huffman_ins_v2_run_length_white_sub0001(3),
11835 
      O => huffman_ins_v2_run_length_black(3)
11836 
    );
11837 
  huffman_ins_v2_run_length_black_4_1 : LUT3
11838 
    generic map(
11839 
      INIT => X"E4"
11840 
    )
11841 
    port map (
11842 
      I0 => fax4_ins_a0_value_o_950,
11843 
      I1 => huffman_ins_v2_run_length_white_sub0000(4),
11844 
      I2 => huffman_ins_v2_run_length_white_sub0001(4),
11845 
      O => huffman_ins_v2_run_length_black(4)
11846 
    );
11847 
  huffman_ins_v2_run_length_black_5_1 : LUT3
11848 
    generic map(
11849 
      INIT => X"E4"
11850 
    )
11851 
    port map (
11852 
      I0 => fax4_ins_a0_value_o_950,
11853 
      I1 => huffman_ins_v2_run_length_white_sub0000(5),
11854 
      I2 => huffman_ins_v2_run_length_white_sub0001(5),
11855 
      O => huffman_ins_v2_run_length_black(5)
11856 
    );
11857 
  fax4_ins_state_updated_mux000811 : LUT2
11858 
    generic map(
11859 
      INIT => X"7"
11860 
    )
11861 
    port map (
11862 
      I0 => fax4_ins_pix_changed_1319,
11863 
      I1 => fax4_ins_state_FSM_FFd8_1338,
11864 
      O => fax4_ins_N20
11865 
    );
11866 
  fax4_ins_FIFO2_multi_read_ins_mux2_x_9_1 : LUT3
11867 
    generic map(
11868 
      INIT => X"E4"
11869 
    )
11870 
    port map (
11871 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux2,
11872 
      I1 => fax4_ins_FIFO2_multi_read_ins_data3_o(9),
11873 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
11874 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_x(9)
11875 
    );
11876 
  fax4_ins_FIFO2_multi_read_ins_mux2_x_8_1 : LUT3
11877 
    generic map(
11878 
      INIT => X"E4"
11879 
    )
11880 
    port map (
11881 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux2,
11882 
      I1 => fax4_ins_FIFO2_multi_read_ins_data3_o(8),
11883 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
11884 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_x(8)
11885 
    );
11886 
  fax4_ins_FIFO2_multi_read_ins_mux2_x_7_1 : LUT3
11887 
    generic map(
11888 
      INIT => X"E4"
11889 
    )
11890 
    port map (
11891 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux2,
11892 
      I1 => fax4_ins_FIFO2_multi_read_ins_data3_o(7),
11893 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
11894 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_x(7)
11895 
    );
11896 
  fax4_ins_FIFO2_multi_read_ins_mux2_x_6_1 : LUT3
11897 
    generic map(
11898 
      INIT => X"E4"
11899 
    )
11900 
    port map (
11901 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux2,
11902 
      I1 => fax4_ins_FIFO2_multi_read_ins_data3_o(6),
11903 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
11904 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_x(6)
11905 
    );
11906 
  fax4_ins_FIFO2_multi_read_ins_mux2_x_5_1 : LUT3
11907 
    generic map(
11908 
      INIT => X"E4"
11909 
    )
11910 
    port map (
11911 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux2,
11912 
      I1 => fax4_ins_FIFO2_multi_read_ins_data3_o(5),
11913 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
11914 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_x(5)
11915 
    );
11916 
  fax4_ins_FIFO2_multi_read_ins_mux2_x_4_1 : LUT3
11917 
    generic map(
11918 
      INIT => X"E4"
11919 
    )
11920 
    port map (
11921 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux2,
11922 
      I1 => fax4_ins_FIFO2_multi_read_ins_data3_o(4),
11923 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
11924 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_x(4)
11925 
    );
11926 
  fax4_ins_FIFO2_multi_read_ins_mux2_x_3_1 : LUT3
11927 
    generic map(
11928 
      INIT => X"E4"
11929 
    )
11930 
    port map (
11931 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux2,
11932 
      I1 => fax4_ins_FIFO2_multi_read_ins_data3_o(3),
11933 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
11934 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_x(3)
11935 
    );
11936 
  fax4_ins_FIFO2_multi_read_ins_mux2_x_2_1 : LUT3
11937 
    generic map(
11938 
      INIT => X"E4"
11939 
    )
11940 
    port map (
11941 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux2,
11942 
      I1 => fax4_ins_FIFO2_multi_read_ins_data3_o(2),
11943 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
11944 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_x(2)
11945 
    );
11946 
  fax4_ins_FIFO2_multi_read_ins_mux2_x_1_1 : LUT3
11947 
    generic map(
11948 
      INIT => X"E4"
11949 
    )
11950 
    port map (
11951 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux2,
11952 
      I1 => fax4_ins_FIFO2_multi_read_ins_data3_o(1),
11953 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
11954 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_x(1)
11955 
    );
11956 
  fax4_ins_FIFO2_multi_read_ins_mux2_x_0_1 : LUT3
11957 
    generic map(
11958 
      INIT => X"E4"
11959 
    )
11960 
    port map (
11961 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux2,
11962 
      I1 => fax4_ins_FIFO2_multi_read_ins_data3_o(0),
11963 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
11964 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_x(0)
11965 
    );
11966 
  fax4_ins_FIFO2_multi_read_ins_mux2_to_white1 : LUT3
11967 
    generic map(
11968 
      INIT => X"E4"
11969 
    )
11970 
    port map (
11971 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux2,
11972 
      I1 => fax4_ins_FIFO2_multi_read_ins_to_white3_o_685,
11973 
      I2 => fax4_ins_to_white_1349,
11974 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_to_white
11975 
    );
11976 
  fax4_ins_FIFO2_multi_read_ins_mux1_x_9_1 : LUT3
11977 
    generic map(
11978 
      INIT => X"E4"
11979 
    )
11980 
    port map (
11981 
      I0 => fax4_ins_FIFO2_multi_read_ins_N11,
11982 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
11983 
      I2 => fax4_ins_FIFO2_multi_read_ins_data2_o(9),
11984 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_x(9)
11985 
    );
11986 
  fax4_ins_FIFO2_multi_read_ins_mux1_x_8_1 : LUT3
11987 
    generic map(
11988 
      INIT => X"E4"
11989 
    )
11990 
    port map (
11991 
      I0 => fax4_ins_FIFO2_multi_read_ins_N11,
11992 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
11993 
      I2 => fax4_ins_FIFO2_multi_read_ins_data2_o(8),
11994 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_x(8)
11995 
    );
11996 
  fax4_ins_FIFO2_multi_read_ins_mux1_x_7_1 : LUT3
11997 
    generic map(
11998 
      INIT => X"E4"
11999 
    )
12000 
    port map (
12001 
      I0 => fax4_ins_FIFO2_multi_read_ins_N11,
12002 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
12003 
      I2 => fax4_ins_FIFO2_multi_read_ins_data2_o(7),
12004 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_x(7)
12005 
    );
12006 
  fax4_ins_FIFO2_multi_read_ins_mux1_x_6_1 : LUT3
12007 
    generic map(
12008 
      INIT => X"E4"
12009 
    )
12010 
    port map (
12011 
      I0 => fax4_ins_FIFO2_multi_read_ins_N11,
12012 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
12013 
      I2 => fax4_ins_FIFO2_multi_read_ins_data2_o(6),
12014 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_x(6)
12015 
    );
12016 
  fax4_ins_FIFO2_multi_read_ins_mux1_x_5_1 : LUT3
12017 
    generic map(
12018 
      INIT => X"E4"
12019 
    )
12020 
    port map (
12021 
      I0 => fax4_ins_FIFO2_multi_read_ins_N11,
12022 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
12023 
      I2 => fax4_ins_FIFO2_multi_read_ins_data2_o(5),
12024 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_x(5)
12025 
    );
12026 
  fax4_ins_FIFO2_multi_read_ins_mux1_x_4_1 : LUT3
12027 
    generic map(
12028 
      INIT => X"E4"
12029 
    )
12030 
    port map (
12031 
      I0 => fax4_ins_FIFO2_multi_read_ins_N11,
12032 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
12033 
      I2 => fax4_ins_FIFO2_multi_read_ins_data2_o(4),
12034 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_x(4)
12035 
    );
12036 
  fax4_ins_FIFO2_multi_read_ins_mux1_x_3_1 : LUT3
12037 
    generic map(
12038 
      INIT => X"E4"
12039 
    )
12040 
    port map (
12041 
      I0 => fax4_ins_FIFO2_multi_read_ins_N11,
12042 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
12043 
      I2 => fax4_ins_FIFO2_multi_read_ins_data2_o(3),
12044 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_x(3)
12045 
    );
12046 
  fax4_ins_FIFO2_multi_read_ins_mux1_x_2_1 : LUT3
12047 
    generic map(
12048 
      INIT => X"E4"
12049 
    )
12050 
    port map (
12051 
      I0 => fax4_ins_FIFO2_multi_read_ins_N11,
12052 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
12053 
      I2 => fax4_ins_FIFO2_multi_read_ins_data2_o(2),
12054 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_x(2)
12055 
    );
12056 
  fax4_ins_FIFO2_multi_read_ins_mux1_x_1_1 : LUT3
12057 
    generic map(
12058 
      INIT => X"E4"
12059 
    )
12060 
    port map (
12061 
      I0 => fax4_ins_FIFO2_multi_read_ins_N11,
12062 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
12063 
      I2 => fax4_ins_FIFO2_multi_read_ins_data2_o(1),
12064 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_x(1)
12065 
    );
12066 
  fax4_ins_FIFO2_multi_read_ins_mux1_x_0_1 : LUT3
12067 
    generic map(
12068 
      INIT => X"E4"
12069 
    )
12070 
    port map (
12071 
      I0 => fax4_ins_FIFO2_multi_read_ins_N11,
12072 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
12073 
      I2 => fax4_ins_FIFO2_multi_read_ins_data2_o(0),
12074 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_x(0)
12075 
    );
12076 
  fax4_ins_FIFO2_multi_read_ins_mux1_to_white2 : LUT3
12077 
    generic map(
12078 
      INIT => X"E4"
12079 
    )
12080 
    port map (
12081 
      I0 => fax4_ins_FIFO2_multi_read_ins_N11,
12082 
      I1 => fax4_ins_to_white_1349,
12083 
      I2 => fax4_ins_FIFO2_multi_read_ins_to_white2_o_684,
12084 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_to_white
12085 
    );
12086 
  fax4_ins_FIFO1_multi_read_ins_mux2_x_9_1 : LUT3
12087 
    generic map(
12088 
      INIT => X"E4"
12089 
    )
12090 
    port map (
12091 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux2,
12092 
      I1 => fax4_ins_FIFO1_multi_read_ins_data3_o(9),
12093 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
12094 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_x(9)
12095 
    );
12096 
  fax4_ins_FIFO1_multi_read_ins_mux2_x_8_1 : LUT3
12097 
    generic map(
12098 
      INIT => X"E4"
12099 
    )
12100 
    port map (
12101 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux2,
12102 
      I1 => fax4_ins_FIFO1_multi_read_ins_data3_o(8),
12103 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
12104 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_x(8)
12105 
    );
12106 
  fax4_ins_FIFO1_multi_read_ins_mux2_x_7_1 : LUT3
12107 
    generic map(
12108 
      INIT => X"E4"
12109 
    )
12110 
    port map (
12111 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux2,
12112 
      I1 => fax4_ins_FIFO1_multi_read_ins_data3_o(7),
12113 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
12114 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_x(7)
12115 
    );
12116 
  fax4_ins_FIFO1_multi_read_ins_mux2_x_6_1 : LUT3
12117 
    generic map(
12118 
      INIT => X"E4"
12119 
    )
12120 
    port map (
12121 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux2,
12122 
      I1 => fax4_ins_FIFO1_multi_read_ins_data3_o(6),
12123 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
12124 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_x(6)
12125 
    );
12126 
  fax4_ins_FIFO1_multi_read_ins_mux2_x_5_1 : LUT3
12127 
    generic map(
12128 
      INIT => X"E4"
12129 
    )
12130 
    port map (
12131 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux2,
12132 
      I1 => fax4_ins_FIFO1_multi_read_ins_data3_o(5),
12133 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
12134 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_x(5)
12135 
    );
12136 
  fax4_ins_FIFO1_multi_read_ins_mux2_x_4_1 : LUT3
12137 
    generic map(
12138 
      INIT => X"E4"
12139 
    )
12140 
    port map (
12141 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux2,
12142 
      I1 => fax4_ins_FIFO1_multi_read_ins_data3_o(4),
12143 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
12144 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_x(4)
12145 
    );
12146 
  fax4_ins_FIFO1_multi_read_ins_mux2_x_3_1 : LUT3
12147 
    generic map(
12148 
      INIT => X"E4"
12149 
    )
12150 
    port map (
12151 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux2,
12152 
      I1 => fax4_ins_FIFO1_multi_read_ins_data3_o(3),
12153 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
12154 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_x(3)
12155 
    );
12156 
  fax4_ins_FIFO1_multi_read_ins_mux2_x_2_1 : LUT3
12157 
    generic map(
12158 
      INIT => X"E4"
12159 
    )
12160 
    port map (
12161 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux2,
12162 
      I1 => fax4_ins_FIFO1_multi_read_ins_data3_o(2),
12163 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
12164 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_x(2)
12165 
    );
12166 
  fax4_ins_FIFO1_multi_read_ins_mux2_x_1_1 : LUT3
12167 
    generic map(
12168 
      INIT => X"E4"
12169 
    )
12170 
    port map (
12171 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux2,
12172 
      I1 => fax4_ins_FIFO1_multi_read_ins_data3_o(1),
12173 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
12174 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_x(1)
12175 
    );
12176 
  fax4_ins_FIFO1_multi_read_ins_mux2_x_0_1 : LUT3
12177 
    generic map(
12178 
      INIT => X"E4"
12179 
    )
12180 
    port map (
12181 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux2,
12182 
      I1 => fax4_ins_FIFO1_multi_read_ins_data3_o(0),
12183 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
12184 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_x(0)
12185 
    );
12186 
  fax4_ins_FIFO1_multi_read_ins_mux2_to_white1 : LUT3
12187 
    generic map(
12188 
      INIT => X"E4"
12189 
    )
12190 
    port map (
12191 
      I0 => fax4_ins_FIFO1_multi_read_ins_mux2,
12192 
      I1 => fax4_ins_FIFO1_multi_read_ins_to_white3_o_443,
12193 
      I2 => fax4_ins_to_white_1349,
12194 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_to_white
12195 
    );
12196 
  fax4_ins_FIFO1_multi_read_ins_mux1_x_9_1 : LUT3
12197 
    generic map(
12198 
      INIT => X"E4"
12199 
    )
12200 
    port map (
12201 
      I0 => fax4_ins_FIFO1_multi_read_ins_N11,
12202 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
12203 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(9),
12204 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_x(9)
12205 
    );
12206 
  fax4_ins_FIFO1_multi_read_ins_mux1_x_8_1 : LUT3
12207 
    generic map(
12208 
      INIT => X"E4"
12209 
    )
12210 
    port map (
12211 
      I0 => fax4_ins_FIFO1_multi_read_ins_N11,
12212 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
12213 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(8),
12214 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_x(8)
12215 
    );
12216 
  fax4_ins_FIFO1_multi_read_ins_mux1_x_7_1 : LUT3
12217 
    generic map(
12218 
      INIT => X"E4"
12219 
    )
12220 
    port map (
12221 
      I0 => fax4_ins_FIFO1_multi_read_ins_N11,
12222 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
12223 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(7),
12224 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_x(7)
12225 
    );
12226 
  fax4_ins_FIFO1_multi_read_ins_mux1_x_6_1 : LUT3
12227 
    generic map(
12228 
      INIT => X"E4"
12229 
    )
12230 
    port map (
12231 
      I0 => fax4_ins_FIFO1_multi_read_ins_N11,
12232 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
12233 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(6),
12234 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_x(6)
12235 
    );
12236 
  fax4_ins_FIFO1_multi_read_ins_mux1_x_5_1 : LUT3
12237 
    generic map(
12238 
      INIT => X"E4"
12239 
    )
12240 
    port map (
12241 
      I0 => fax4_ins_FIFO1_multi_read_ins_N11,
12242 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
12243 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(5),
12244 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_x(5)
12245 
    );
12246 
  fax4_ins_FIFO1_multi_read_ins_mux1_x_4_1 : LUT3
12247 
    generic map(
12248 
      INIT => X"E4"
12249 
    )
12250 
    port map (
12251 
      I0 => fax4_ins_FIFO1_multi_read_ins_N11,
12252 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
12253 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(4),
12254 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_x(4)
12255 
    );
12256 
  fax4_ins_FIFO1_multi_read_ins_mux1_x_3_1 : LUT3
12257 
    generic map(
12258 
      INIT => X"E4"
12259 
    )
12260 
    port map (
12261 
      I0 => fax4_ins_FIFO1_multi_read_ins_N11,
12262 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
12263 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(3),
12264 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_x(3)
12265 
    );
12266 
  fax4_ins_FIFO1_multi_read_ins_mux1_x_2_1 : LUT3
12267 
    generic map(
12268 
      INIT => X"E4"
12269 
    )
12270 
    port map (
12271 
      I0 => fax4_ins_FIFO1_multi_read_ins_N11,
12272 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
12273 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(2),
12274 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_x(2)
12275 
    );
12276 
  fax4_ins_FIFO1_multi_read_ins_mux1_x_1_1 : LUT3
12277 
    generic map(
12278 
      INIT => X"E4"
12279 
    )
12280 
    port map (
12281 
      I0 => fax4_ins_FIFO1_multi_read_ins_N11,
12282 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
12283 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(1),
12284 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_x(1)
12285 
    );
12286 
  fax4_ins_FIFO1_multi_read_ins_mux1_x_0_1 : LUT3
12287 
    generic map(
12288 
      INIT => X"E4"
12289 
    )
12290 
    port map (
12291 
      I0 => fax4_ins_FIFO1_multi_read_ins_N11,
12292 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
12293 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(0),
12294 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_x(0)
12295 
    );
12296 
  fax4_ins_FIFO1_multi_read_ins_mux1_to_white2 : LUT3
12297 
    generic map(
12298 
      INIT => X"E4"
12299 
    )
12300 
    port map (
12301 
      I0 => fax4_ins_FIFO1_multi_read_ins_N11,
12302 
      I1 => fax4_ins_to_white_1349,
12303 
      I2 => fax4_ins_FIFO1_multi_read_ins_to_white2_o_442,
12304 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_to_white
12305 
    );
12306 
  huffman_ins_v2_run_length_white_and000020 : LUT4
12307 
    generic map(
12308 
      INIT => X"0001"
12309 
    )
12310 
    port map (
12311 
      I0 => fax4_ins_a0_o(2),
12312 
      I1 => fax4_ins_a0_o(3),
12313 
      I2 => fax4_ins_a0_o(4),
12314 
      I3 => fax4_ins_a0_o(0),
12315 
      O => huffman_ins_v2_run_length_white_and000020_2134
12316 
    );
12317 
  huffman_ins_v2_run_length_white_and000043 : LUT4
12318 
    generic map(
12319 
      INIT => X"0001"
12320 
    )
12321 
    port map (
12322 
      I0 => fax4_ins_a0_o(6),
12323 
      I1 => fax4_ins_a0_o(7),
12324 
      I2 => fax4_ins_a0_o(8),
12325 
      I3 => fax4_ins_a0_o(1),
12326 
      O => huffman_ins_v2_run_length_white_and000043_2135
12327 
    );
12328 
  huffman_ins_v2_run_length_white_and000045 : LUT3
12329 
    generic map(
12330 
      INIT => X"80"
12331 
    )
12332 
    port map (
12333 
      I0 => huffman_ins_v2_run_length_white_and00007_2136,
12334 
      I1 => huffman_ins_v2_run_length_white_and000020_2134,
12335 
      I2 => huffman_ins_v2_run_length_white_and000043_2135,
12336 
      O => huffman_ins_v2_run_length_white_and0000
12337 
    );
12338 
  fax4_ins_FIFO2_multi_read_ins_mux2_and00001 : LUT3
12339 
    generic map(
12340 
      INIT => X"80"
12341 
    )
12342 
    port map (
12343 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(0),
12344 
      I1 => fax4_ins_fifo2_wr,
12345 
      I2 => fax4_ins_FIFO2_multi_read_ins_N7,
12346 
      O => fax4_ins_FIFO2_multi_read_ins_mux2
12347 
    );
12348 
  fax4_ins_FIFO2_multi_read_ins_mux1_to_white11 : LUT3
12349 
    generic map(
12350 
      INIT => X"F7"
12351 
    )
12352 
    port map (
12353 
      I0 => fax4_ins_fifo2_wr,
12354 
      I1 => fax4_ins_FIFO2_multi_read_ins_N7,
12355 
      I2 => fax4_ins_FIFO2_multi_read_ins_used(0),
12356 
      O => fax4_ins_FIFO2_multi_read_ins_N11
12357 
    );
12358 
  fax4_ins_FIFO1_multi_read_ins_mux2_and00001 : LUT3
12359 
    generic map(
12360 
      INIT => X"80"
12361 
    )
12362 
    port map (
12363 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(0),
12364 
      I1 => fax4_ins_fifo1_wr,
12365 
      I2 => fax4_ins_FIFO1_multi_read_ins_N7,
12366 
      O => fax4_ins_FIFO1_multi_read_ins_mux2
12367 
    );
12368 
  fax4_ins_FIFO1_multi_read_ins_mux1_to_white11 : LUT3
12369 
    generic map(
12370 
      INIT => X"F7"
12371 
    )
12372 
    port map (
12373 
      I0 => fax4_ins_fifo1_wr,
12374 
      I1 => fax4_ins_FIFO1_multi_read_ins_N7,
12375 
      I2 => fax4_ins_FIFO1_multi_read_ins_used(0),
12376 
      O => fax4_ins_FIFO1_multi_read_ins_N11
12377 
    );
12378 
  huffman_ins_v2_run_length_black_6_1 : LUT3
12379 
    generic map(
12380 
      INIT => X"E4"
12381 
    )
12382 
    port map (
12383 
      I0 => fax4_ins_a0_value_o_950,
12384 
      I1 => huffman_ins_v2_run_length_white_sub0000(6),
12385 
      I2 => huffman_ins_v2_run_length_white_sub0001(6),
12386 
      O => huffman_ins_v2_run_length_black(6)
12387 
    );
12388 
  huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000141 : LUT3
12389 
    generic map(
12390 
      INIT => X"A2"
12391 
    )
12392 
    port map (
12393 
      I0 => huffman_ins_v2_run_length_black(8),
12394 
      I1 => huffman_ins_v2_run_length_black(9),
12395 
      I2 => huffman_ins_v2_run_length_black(7),
12396 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00014
12397 
    );
12398 
  huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux0001111 : LUT4
12399 
    generic map(
12400 
      INIT => X"9998"
12401 
    )
12402 
    port map (
12403 
      I0 => huffman_ins_v2_run_length_black(9),
12404 
      I1 => huffman_ins_v2_run_length_black(7),
12405 
      I2 => huffman_ins_v2_run_length_black(6),
12406 
      I3 => huffman_ins_v2_run_length_black(8),
12407 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00011
12408 
    );
12409 
  huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000151 : LUT4
12410 
    generic map(
12411 
      INIT => X"9C98"
12412 
    )
12413 
    port map (
12414 
      I0 => N465,
12415 
      I1 => huffman_ins_v2_run_length_black(8),
12416 
      I2 => huffman_ins_v2_run_length_black(9),
12417 
      I3 => huffman_ins_v2_run_length_black(6),
12418 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00015
12419 
    );
12420 
  huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000131 : LUT4
12421 
    generic map(
12422 
      INIT => X"3F36"
12423 
    )
12424 
    port map (
12425 
      I0 => huffman_ins_v2_run_length_black(6),
12426 
      I1 => huffman_ins_v2_run_length_black(8),
12427 
      I2 => huffman_ins_v2_run_length_black(7),
12428 
      I3 => huffman_ins_v2_run_length_black(9),
12429 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00013
12430 
    );
12431 
  huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000121 : LUT4
12432 
    generic map(
12433 
      INIT => X"6362"
12434 
    )
12435 
    port map (
12436 
      I0 => huffman_ins_v2_run_length_black(9),
12437 
      I1 => huffman_ins_v2_run_length_black(7),
12438 
      I2 => huffman_ins_v2_run_length_black(8),
12439 
      I3 => huffman_ins_v2_run_length_black(6),
12440 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00012
12441 
    );
12442 
  fax4_ins_load_mux_b_SW0 : LUT3
12443 
    generic map(
12444 
      INIT => X"EA"
12445 
    )
12446 
    port map (
12447 
      I0 => fax4_ins_pass_mode,
12448 
      I1 => fax4_ins_state_FSM_FFd10_1323,
12449 
      I2 => fax4_ins_state_updated_1345,
12450 
      O => N56
12451 
    );
12452 
  fax4_ins_load_mux_b : LUT4
12453 
    generic map(
12454 
      INIT => X"FFA8"
12455 
    )
12456 
    port map (
12457 
      I0 => fax4_ins_pix_changed_1319,
12458 
      I1 => fax4_ins_vertical_mode_cmp_le0000,
12459 
      I2 => fax4_ins_state_FSM_FFd8_1338,
12460 
      I3 => N56,
12461 
      O => fax4_ins_load_mux_b_1285
12462 
    );
12463 
  fax4_ins_fifo_out2_valid1 : LUT3
12464 
    generic map(
12465 
      INIT => X"E4"
12466 
    )
12467 
    port map (
12468 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12469 
      I1 => fax4_ins_FIFO2_multi_read_ins_valid2_o_699,
12470 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid2_o_457,
12471 
      O => fax4_ins_fifo_out2_valid
12472 
    );
12473 
  huffman_ins_v2_run_length_black_8_1 : LUT3
12474 
    generic map(
12475 
      INIT => X"E4"
12476 
    )
12477 
    port map (
12478 
      I0 => fax4_ins_a0_value_o_950,
12479 
      I1 => huffman_ins_v2_run_length_white_sub0000(8),
12480 
      I2 => huffman_ins_v2_run_length_white_sub0001(8),
12481 
      O => huffman_ins_v2_run_length_black(8)
12482 
    );
12483 
  huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux0001151 : LUT3
12484 
    generic map(
12485 
      INIT => X"FE"
12486 
    )
12487 
    port map (
12488 
      I0 => huffman_ins_v2_run_length_black(9),
12489 
      I1 => huffman_ins_v2_run_length_black(7),
12490 
      I2 => huffman_ins_v2_run_length_black(8),
12491 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000115
12492 
    );
12493 
  huffman_ins_v2_run_length_black_9_1 : LUT3
12494 
    generic map(
12495 
      INIT => X"E4"
12496 
    )
12497 
    port map (
12498 
      I0 => fax4_ins_a0_value_o_950,
12499 
      I1 => huffman_ins_v2_run_length_white_sub0000(9),
12500 
      I2 => huffman_ins_v2_run_length_white_sub0001(9),
12501 
      O => huffman_ins_v2_run_length_black(9)
12502 
    );
12503 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000113 : LUT3
12504 
    generic map(
12505 
      INIT => X"36"
12506 
    )
12507 
    port map (
12508 
      I0 => huffman_ins_v2_run_length_white(8),
12509 
      I1 => huffman_ins_v2_run_length_white(6),
12510 
      I2 => huffman_ins_v2_run_length_white(9),
12511 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001
12512 
    );
12513 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000171 : LUT4
12514 
    generic map(
12515 
      INIT => X"AA80"
12516 
    )
12517 
    port map (
12518 
      I0 => huffman_ins_v2_run_length_white(9),
12519 
      I1 => huffman_ins_v2_run_length_white(6),
12520 
      I2 => huffman_ins_v2_run_length_white(7),
12521 
      I3 => huffman_ins_v2_run_length_white(8),
12522 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00017
12523 
    );
12524 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000151 : LUT4
12525 
    generic map(
12526 
      INIT => X"2666"
12527 
    )
12528 
    port map (
12529 
      I0 => huffman_ins_v2_run_length_white(8),
12530 
      I1 => huffman_ins_v2_run_length_white(9),
12531 
      I2 => huffman_ins_v2_run_length_white(6),
12532 
      I3 => huffman_ins_v2_run_length_white(7),
12533 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00015
12534 
    );
12535 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000131 : LUT4
12536 
    generic map(
12537 
      INIT => X"2062"
12538 
    )
12539 
    port map (
12540 
      I0 => huffman_ins_v2_run_length_white(6),
12541 
      I1 => huffman_ins_v2_run_length_white(8),
12542 
      I2 => huffman_ins_v2_run_length_white(9),
12543 
      I3 => huffman_ins_v2_run_length_white(7),
12544 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00013
12545 
    );
12546 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000121 : LUT4
12547 
    generic map(
12548 
      INIT => X"F62E"
12549 
    )
12550 
    port map (
12551 
      I0 => huffman_ins_v2_run_length_white(8),
12552 
      I1 => huffman_ins_v2_run_length_white(9),
12553 
      I2 => huffman_ins_v2_run_length_white(6),
12554 
      I3 => huffman_ins_v2_run_length_white(7),
12555 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00012
12556 
    );
12557 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001111 : LUT4
12558 
    generic map(
12559 
      INIT => X"578E"
12560 
    )
12561 
    port map (
12562 
      I0 => huffman_ins_v2_run_length_white(6),
12563 
      I1 => huffman_ins_v2_run_length_white(8),
12564 
      I2 => huffman_ins_v2_run_length_white(9),
12565 
      I3 => huffman_ins_v2_run_length_white(7),
12566 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00011
12567 
    );
12568 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000141 : LUT4
12569 
    generic map(
12570 
      INIT => X"C78E"
12571 
    )
12572 
    port map (
12573 
      I0 => huffman_ins_v2_run_length_white(7),
12574 
      I1 => huffman_ins_v2_run_length_white(8),
12575 
      I2 => huffman_ins_v2_run_length_white(9),
12576 
      I3 => huffman_ins_v2_run_length_white(6),
12577 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00014
12578 
    );
12579 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000191 : LUT4
12580 
    generic map(
12581 
      INIT => X"F816"
12582 
    )
12583 
    port map (
12584 
      I0 => huffman_ins_v2_run_length_white(6),
12585 
      I1 => huffman_ins_v2_run_length_white(7),
12586 
      I2 => huffman_ins_v2_run_length_white(8),
12587 
      I3 => huffman_ins_v2_run_length_white(9),
12588 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00019
12589 
    );
12590 
  fax4_ins_fifo_out1_to_white1 : LUT3
12591 
    generic map(
12592 
      INIT => X"E4"
12593 
    )
12594 
    port map (
12595 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12596 
      I1 => fax4_ins_FIFO2_multi_read_ins_to_white1_o_683,
12597 
      I2 => fax4_ins_FIFO1_multi_read_ins_to_white1_o_441,
12598 
      O => fax4_ins_fifo_out1_to_white
12599 
    );
12600 
  fax4_ins_mux_a0_or00001 : LUT4
12601 
    generic map(
12602 
      INIT => X"FFD5"
12603 
    )
12604 
    port map (
12605 
      I0 => fax4_ins_state_FSM_N7,
12606 
      I1 => fax4_ins_state_updated_1345,
12607 
      I2 => fax4_ins_state_FSM_FFd10_1323,
12608 
      I3 => fax4_ins_state_FSM_FFd11_1325,
12609 
      O => fax4_ins_mux_a0_0_Q
12610 
    );
12611 
  fax4_ins_b2_mux0004_1_21 : LUT4
12612 
    generic map(
12613 
      INIT => X"0103"
12614 
    )
12615 
    port map (
12616 
      I0 => fax4_ins_fifo_out2_valid,
12617 
      I1 => fax4_ins_b2_to_white_and0000,
12618 
      I2 => fax4_ins_b2_to_white_and0001,
12619 
      I3 => N498,
12620 
      O => fax4_ins_N19
12621 
    );
12622 
  fax4_ins_fifo_out1_x_9_1 : LUT3
12623 
    generic map(
12624 
      INIT => X"E4"
12625 
    )
12626 
    port map (
12627 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12628 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(9),
12629 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(9),
12630 
      O => fax4_ins_fifo_out1_x(9)
12631 
    );
12632 
  fax4_ins_fifo_out1_x_8_1 : LUT3
12633 
    generic map(
12634 
      INIT => X"E4"
12635 
    )
12636 
    port map (
12637 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12638 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(8),
12639 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(8),
12640 
      O => fax4_ins_fifo_out1_x(8)
12641 
    );
12642 
  fax4_ins_fifo_out1_x_7_1 : LUT3
12643 
    generic map(
12644 
      INIT => X"E4"
12645 
    )
12646 
    port map (
12647 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12648 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(7),
12649 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(7),
12650 
      O => fax4_ins_fifo_out1_x(7)
12651 
    );
12652 
  fax4_ins_fifo_out1_x_6_1 : LUT3
12653 
    generic map(
12654 
      INIT => X"E4"
12655 
    )
12656 
    port map (
12657 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12658 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(6),
12659 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(6),
12660 
      O => fax4_ins_fifo_out1_x(6)
12661 
    );
12662 
  fax4_ins_b2_to_white_and00001 : LUT2
12663 
    generic map(
12664 
      INIT => X"8"
12665 
    )
12666 
    port map (
12667 
      I0 => fax4_ins_fifo_out_prev1_valid_1240,
12668 
      I1 => N492,
12669 
      O => fax4_ins_b2_to_white_and0000
12670 
    );
12671 
  fax4_ins_b2_to_white_and00011 : LUT4
12672 
    generic map(
12673 
      INIT => X"D800"
12674 
    )
12675 
    port map (
12676 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12677 
      I1 => fax4_ins_FIFO1_multi_read_ins_valid1_o_456,
12678 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid1_o_698,
12679 
      I3 => fax4_ins_mux_b1(1),
12680 
      O => fax4_ins_b2_to_white_and0001
12681 
    );
12682 
  fax4_ins_mux_b1_1_and0000_SW0 : LUT2
12683 
    generic map(
12684 
      INIT => X"8"
12685 
    )
12686 
    port map (
12687 
      I0 => fax4_ins_fifo_out_prev1_valid_1240,
12688 
      I1 => fax4_ins_pass_mode,
12689 
      O => N73
12690 
    );
12691 
  fax4_ins_mux_b1_0_and0000_SW0 : LUT2
12692 
    generic map(
12693 
      INIT => X"8"
12694 
    )
12695 
    port map (
12696 
      I0 => fax4_ins_fifo_out_prev2_valid_1253,
12697 
      I1 => fax4_ins_pass_mode,
12698 
      O => N75
12699 
    );
12700 
  fax4_ins_fifo_out1_x_5_1 : LUT3
12701 
    generic map(
12702 
      INIT => X"E4"
12703 
    )
12704 
    port map (
12705 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12706 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(5),
12707 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(5),
12708 
      O => fax4_ins_fifo_out1_x(5)
12709 
    );
12710 
  fax4_ins_fifo_out1_x_4_1 : LUT3
12711 
    generic map(
12712 
      INIT => X"E4"
12713 
    )
12714 
    port map (
12715 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12716 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(4),
12717 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(4),
12718 
      O => fax4_ins_fifo_out1_x(4)
12719 
    );
12720 
  fax4_ins_fifo_out1_x_3_1 : LUT3
12721 
    generic map(
12722 
      INIT => X"E4"
12723 
    )
12724 
    port map (
12725 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12726 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(3),
12727 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(3),
12728 
      O => fax4_ins_fifo_out1_x(3)
12729 
    );
12730 
  fax4_ins_mode_indicator_o_mux0001_2_232 : LUT4
12731 
    generic map(
12732 
      INIT => X"0001"
12733 
    )
12734 
    port map (
12735 
      I0 => fax4_ins_a1b1(4),
12736 
      I1 => fax4_ins_a1b1(5),
12737 
      I2 => fax4_ins_a1b1(6),
12738 
      I3 => N483,
12739 
      O => fax4_ins_mode_indicator_o_mux0001_2_232_1296
12740 
    );
12741 
  fax4_ins_fifo_out1_x_2_1 : LUT3
12742 
    generic map(
12743 
      INIT => X"E4"
12744 
    )
12745 
    port map (
12746 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12747 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(2),
12748 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(2),
12749 
      O => fax4_ins_fifo_out1_x(2)
12750 
    );
12751 
  fax4_ins_fifo_out2_x_9_1 : LUT3
12752 
    generic map(
12753 
      INIT => X"E4"
12754 
    )
12755 
    port map (
12756 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12757 
      I1 => fax4_ins_FIFO2_multi_read_ins_data2_o(9),
12758 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(9),
12759 
      O => fax4_ins_fifo_out2_x(9)
12760 
    );
12761 
  fax4_ins_fifo_out1_x_1_1 : LUT3
12762 
    generic map(
12763 
      INIT => X"E4"
12764 
    )
12765 
    port map (
12766 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12767 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(1),
12768 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(1),
12769 
      O => fax4_ins_fifo_out1_x(1)
12770 
    );
12771 
  fax4_ins_fifo_out2_x_8_1 : LUT3
12772 
    generic map(
12773 
      INIT => X"E4"
12774 
    )
12775 
    port map (
12776 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12777 
      I1 => fax4_ins_FIFO2_multi_read_ins_data2_o(8),
12778 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(8),
12779 
      O => fax4_ins_fifo_out2_x(8)
12780 
    );
12781 
  fax4_ins_fifo_out1_x_0_1 : LUT3
12782 
    generic map(
12783 
      INIT => X"E4"
12784 
    )
12785 
    port map (
12786 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12787 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(0),
12788 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(0),
12789 
      O => fax4_ins_fifo_out1_x(0)
12790 
    );
12791 
  fax4_ins_b1_mux0004_9_18 : LUT4
12792 
    generic map(
12793 
      INIT => X"0E04"
12794 
    )
12795 
    port map (
12796 
      I0 => fax4_ins_mux_b1(2),
12797 
      I1 => fax4_ins_fifo_out2_x(9),
12798 
      I2 => fax4_ins_mux_b1(1),
12799 
      I3 => fax4_ins_fifo_out1_x(9),
12800 
      O => fax4_ins_b1_mux0004_9_18_1053
12801 
    );
12802 
  fax4_ins_b2_mux0004_0_10 : LUT4
12803 
    generic map(
12804 
      INIT => X"EC20"
12805 
    )
12806 
    port map (
12807 
      I0 => fax4_ins_fifo_out1_x(0),
12808 
      I1 => fax4_ins_b2_to_white_and0000,
12809 
      I2 => fax4_ins_b2_to_white_and0001,
12810 
      I3 => fax4_ins_fifo_out_prev1_x(0),
12811 
      O => fax4_ins_b2_mux0004_0_10_1065
12812 
    );
12813 
  fax4_ins_b2_to_white_mux000410 : LUT4
12814 
    generic map(
12815 
      INIT => X"EC20"
12816 
    )
12817 
    port map (
12818 
      I0 => fax4_ins_fifo_out1_to_white,
12819 
      I1 => fax4_ins_b2_to_white_and0000,
12820 
      I2 => fax4_ins_b2_to_white_and0001,
12821 
      I3 => fax4_ins_fifo_out_prev1_to_white_1239,
12822 
      O => fax4_ins_b2_to_white_mux000410_1098
12823 
    );
12824 
  fax4_ins_fifo_out2_x_7_1 : LUT3
12825 
    generic map(
12826 
      INIT => X"E4"
12827 
    )
12828 
    port map (
12829 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12830 
      I1 => fax4_ins_FIFO2_multi_read_ins_data2_o(7),
12831 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(7),
12832 
      O => fax4_ins_fifo_out2_x(7)
12833 
    );
12834 
  fax4_ins_fifo_out2_x_6_1 : LUT3
12835 
    generic map(
12836 
      INIT => X"E4"
12837 
    )
12838 
    port map (
12839 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12840 
      I1 => fax4_ins_FIFO2_multi_read_ins_data2_o(6),
12841 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(6),
12842 
      O => fax4_ins_fifo_out2_x(6)
12843 
    );
12844 
  fax4_ins_FIFO2_multi_read_ins_latch3_or00001 : LUT2
12845 
    generic map(
12846 
      INIT => X"E"
12847 
    )
12848 
    port map (
12849 
      I0 => fax4_ins_FIFO2_multi_read_ins_mux3,
12850 
      I1 => fax4_ins_fifo2_rd,
12851 
      O => fax4_ins_FIFO2_multi_read_ins_latch3
12852 
    );
12853 
  fax4_ins_FIFO1_multi_read_ins_latch3_or00001 : LUT2
12854 
    generic map(
12855 
      INIT => X"E"
12856 
    )
12857 
    port map (
12858 
      I0 => N495,
12859 
      I1 => fax4_ins_fifo1_rd,
12860 
      O => fax4_ins_FIFO1_multi_read_ins_latch3
12861 
    );
12862 
  fax4_ins_fifo_out2_x_5_1 : LUT3
12863 
    generic map(
12864 
      INIT => X"E4"
12865 
    )
12866 
    port map (
12867 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12868 
      I1 => fax4_ins_FIFO2_multi_read_ins_data2_o(5),
12869 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(5),
12870 
      O => fax4_ins_fifo_out2_x(5)
12871 
    );
12872 
  fax4_ins_fifo_out2_x_4_1 : LUT3
12873 
    generic map(
12874 
      INIT => X"E4"
12875 
    )
12876 
    port map (
12877 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12878 
      I1 => fax4_ins_FIFO2_multi_read_ins_data2_o(4),
12879 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(4),
12880 
      O => fax4_ins_fifo_out2_x(4)
12881 
    );
12882 
  fax4_ins_fifo_out2_x_3_1 : LUT3
12883 
    generic map(
12884 
      INIT => X"E4"
12885 
    )
12886 
    port map (
12887 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12888 
      I1 => fax4_ins_FIFO2_multi_read_ins_data2_o(3),
12889 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(3),
12890 
      O => fax4_ins_fifo_out2_x(3)
12891 
    );
12892 
  fax4_ins_fifo_out2_x_2_1 : LUT3
12893 
    generic map(
12894 
      INIT => X"E4"
12895 
    )
12896 
    port map (
12897 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12898 
      I1 => fax4_ins_FIFO2_multi_read_ins_data2_o(2),
12899 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(2),
12900 
      O => fax4_ins_fifo_out2_x(2)
12901 
    );
12902 
  fax4_ins_fifo_out2_x_1_1 : LUT3
12903 
    generic map(
12904 
      INIT => X"E4"
12905 
    )
12906 
    port map (
12907 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12908 
      I1 => fax4_ins_FIFO2_multi_read_ins_data2_o(1),
12909 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(1),
12910 
      O => fax4_ins_fifo_out2_x(1)
12911 
    );
12912 
  fax4_ins_fifo_out2_x_0_1 : LUT3
12913 
    generic map(
12914 
      INIT => X"E4"
12915 
    )
12916 
    port map (
12917 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12918 
      I1 => fax4_ins_FIFO2_multi_read_ins_data2_o(0),
12919 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(0),
12920 
      O => fax4_ins_fifo_out2_x(0)
12921 
    );
12922 
  fax4_ins_mux_b1_3_and0000_SW0 : LUT4
12923 
    generic map(
12924 
      INIT => X"A695"
12925 
    )
12926 
    port map (
12927 
      I0 => fax4_ins_a0_to_white_946,
12928 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
12929 
      I2 => fax4_ins_FIFO1_multi_read_ins_to_white2_o_442,
12930 
      I3 => fax4_ins_FIFO2_multi_read_ins_to_white2_o_684,
12931 
      O => N77
12932 
    );
12933 
  fax4_ins_b1_mux0004_8_12 : LUT4
12934 
    generic map(
12935 
      INIT => X"CCA0"
12936 
    )
12937 
    port map (
12938 
      I0 => fax4_ins_fifo_out2_x(8),
12939 
      I1 => fax4_ins_fifo_out1_x(8),
12940 
      I2 => N493,
12941 
      I3 => fax4_ins_mux_b1(2),
12942 
      O => fax4_ins_b1_mux0004_8_12_1049
12943 
    );
12944 
  fax4_ins_b1_mux0004_3_12 : LUT4
12945 
    generic map(
12946 
      INIT => X"CCA0"
12947 
    )
12948 
    port map (
12949 
      I0 => fax4_ins_fifo_out2_x(3),
12950 
      I1 => fax4_ins_fifo_out1_x(3),
12951 
      I2 => fax4_ins_mux_b1(3),
12952 
      I3 => fax4_ins_mux_b1(2),
12953 
      O => fax4_ins_b1_mux0004_3_12_1037
12954 
    );
12955 
  fax4_ins_b1_mux0004_2_12 : LUT4
12956 
    generic map(
12957 
      INIT => X"CCA0"
12958 
    )
12959 
    port map (
12960 
      I0 => fax4_ins_fifo_out2_x(2),
12961 
      I1 => fax4_ins_fifo_out1_x(2),
12962 
      I2 => fax4_ins_mux_b1(3),
12963 
      I3 => fax4_ins_mux_b1(2),
12964 
      O => fax4_ins_b1_mux0004_2_12_1033
12965 
    );
12966 
  fax4_ins_b1_mux0004_1_12 : LUT4
12967 
    generic map(
12968 
      INIT => X"CCA0"
12969 
    )
12970 
    port map (
12971 
      I0 => fax4_ins_fifo_out2_x(1),
12972 
      I1 => fax4_ins_fifo_out1_x(1),
12973 
      I2 => fax4_ins_mux_b1(3),
12974 
      I3 => fax4_ins_mux_b1(2),
12975 
      O => fax4_ins_b1_mux0004_1_12_1029
12976 
    );
12977 
  fax4_ins_FIFO2_multi_read_ins_mem_rd_SW0 : LUT4
12978 
    generic map(
12979 
      INIT => X"FEFF"
12980 
    )
12981 
    port map (
12982 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_668,
12983 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(1),
12984 
      I2 => fax4_ins_FIFO2_multi_read_ins_used(0),
12985 
      I3 => fax4_ins_FIFO2_multi_read_ins_used(2),
12986 
      O => N79
12987 
    );
12988 
  fax4_ins_FIFO2_multi_read_ins_mem_rd_SW1 : LUT4
12989 
    generic map(
12990 
      INIT => X"AAA2"
12991 
    )
12992 
    port map (
12993 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(2),
12994 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_668,
12995 
      I2 => fax4_ins_FIFO2_multi_read_ins_used(0),
12996 
      I3 => fax4_ins_FIFO2_multi_read_ins_used(1),
12997 
      O => N80
12998 
    );
12999 
  fax4_ins_FIFO2_multi_read_ins_mem_rd : LUT4
13000 
    generic map(
13001 
      INIT => X"FC05"
13002 
    )
13003 
    port map (
13004 
      I0 => N79,
13005 
      I1 => N80,
13006 
      I2 => fax4_ins_FIFO2_multi_read_ins_N4,
13007 
      I3 => N485,
13008 
      O => fax4_ins_FIFO2_multi_read_ins_mem_rd_628
13009 
    );
13010 
  fax4_ins_FIFO1_multi_read_ins_mem_rd_SW0 : LUT4
13011 
    generic map(
13012 
      INIT => X"FEFF"
13013 
    )
13014 
    port map (
13015 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_426,
13016 
      I1 => fax4_ins_FIFO1_multi_read_ins_used(1),
13017 
      I2 => fax4_ins_FIFO1_multi_read_ins_used(0),
13018 
      I3 => fax4_ins_FIFO1_multi_read_ins_used(2),
13019 
      O => N82
13020 
    );
13021 
  fax4_ins_FIFO1_multi_read_ins_mem_rd_SW1 : LUT4
13022 
    generic map(
13023 
      INIT => X"AAA2"
13024 
    )
13025 
    port map (
13026 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(2),
13027 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_426,
13028 
      I2 => fax4_ins_FIFO1_multi_read_ins_used(0),
13029 
      I3 => fax4_ins_FIFO1_multi_read_ins_used(1),
13030 
      O => N83
13031 
    );
13032 
  fax4_ins_FIFO1_multi_read_ins_mem_rd : LUT4
13033 
    generic map(
13034 
      INIT => X"FC05"
13035 
    )
13036 
    port map (
13037 
      I0 => N82,
13038 
      I1 => N83,
13039 
      I2 => fax4_ins_FIFO1_multi_read_ins_N4,
13040 
      I3 => N486,
13041 
      O => fax4_ins_FIFO1_multi_read_ins_mem_rd_387
13042 
    );
13043 
  fax4_ins_FIFO2_multi_read_ins_used_not0002_SW0 : LUT4
13044 
    generic map(
13045 
      INIT => X"FFFE"
13046 
    )
13047 
    port map (
13048 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(1),
13049 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(0),
13050 
      I2 => fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_668,
13051 
      I3 => fax4_ins_FIFO2_multi_read_ins_N4,
13052 
      O => N85
13053 
    );
13054 
  fax4_ins_FIFO2_multi_read_ins_used_not0002 : LUT4
13055 
    generic map(
13056 
      INIT => X"FAF2"
13057 
    )
13058 
    port map (
13059 
      I0 => fax4_ins_FIFO2_multi_read_ins_N8,
13060 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(2),
13061 
      I2 => fax4_ins_fifo2_wr,
13062 
      I3 => N85,
13063 
      O => fax4_ins_FIFO2_multi_read_ins_used_not0002_696
13064 
    );
13065 
  fax4_ins_FIFO1_multi_read_ins_used_not0002_SW0 : LUT4
13066 
    generic map(
13067 
      INIT => X"FFFE"
13068 
    )
13069 
    port map (
13070 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(1),
13071 
      I1 => fax4_ins_FIFO1_multi_read_ins_used(0),
13072 
      I2 => fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_426,
13073 
      I3 => fax4_ins_FIFO1_multi_read_ins_N4,
13074 
      O => N87
13075 
    );
13076 
  fax4_ins_FIFO1_multi_read_ins_used_not0002 : LUT4
13077 
    generic map(
13078 
      INIT => X"FAF2"
13079 
    )
13080 
    port map (
13081 
      I0 => fax4_ins_FIFO1_multi_read_ins_N8,
13082 
      I1 => fax4_ins_FIFO1_multi_read_ins_used(2),
13083 
      I2 => fax4_ins_fifo1_wr,
13084 
      I3 => N87,
13085 
      O => fax4_ins_FIFO1_multi_read_ins_used_not0002_454
13086 
    );
13087 
  fax4_ins_load_mux_a0_SW0 : LUT4
13088 
    generic map(
13089 
      INIT => X"FFD5"
13090 
    )
13091 
    port map (
13092 
      I0 => fax4_ins_state_FSM_N7,
13093 
      I1 => fax4_ins_state_updated_1345,
13094 
      I2 => fax4_ins_state_FSM_FFd10_1323,
13095 
      I3 => fax4_ins_pass_mode,
13096 
      O => N89
13097 
    );
13098 
  fax4_ins_load_mux_a0 : LUT4
13099 
    generic map(
13100 
      INIT => X"FAF8"
13101 
    )
13102 
    port map (
13103 
      I0 => fax4_ins_pix_changed_1319,
13104 
      I1 => fax4_ins_state_FSM_FFd8_1338,
13105 
      I2 => N89,
13106 
      I3 => N471,
13107 
      O => fax4_ins_load_mux_a0_1284
13108 
    );
13109 
  fax4_ins_fifo_rd22 : LUT4
13110 
    generic map(
13111 
      INIT => X"0E04"
13112 
    )
13113 
    port map (
13114 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
13115 
      I1 => fax4_ins_FIFO2_multi_read_ins_valid1_o_698,
13116 
      I2 => fax4_ins_EOL,
13117 
      I3 => fax4_ins_FIFO1_multi_read_ins_valid1_o_456,
13118 
      O => fax4_ins_fifo_rd22_1267
13119 
    );
13120 
  fax4_ins_mode_indicator_o_mux0001_2_36 : LUT2
13121 
    generic map(
13122 
      INIT => X"8"
13123 
    )
13124 
    port map (
13125 
      I0 => N480,
13126 
      I1 => fax4_ins_a1b1(3),
13127 
      O => fax4_ins_mode_indicator_o_mux0001_2_36_1300
13128 
    );
13129 
  fax4_ins_counter_xy_v2_ins_EOL_o1 : LUT2
13130 
    generic map(
13131 
      INIT => X"7"
13132 
    )
13133 
    port map (
13134 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
13135 
      I1 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
13136 
      O => fax4_ins_EOL
13137 
    );
13138 
  fax4_ins_mode_indicator_o_mux0001_3_9 : LUT4
13139 
    generic map(
13140 
      INIT => X"2000"
13141 
    )
13142 
    port map (
13143 
      I0 => N497,
13144 
      I1 => fax4_ins_a1b1(0),
13145 
      I2 => fax4_ins_load_a1_or0001,
13146 
      I3 => fax4_ins_N15,
13147 
      O => fax4_ins_mode_indicator_o_mux0001_3_9_1302
13148 
    );
13149 
  fax4_ins_a0_mux0000_9_Q : LUT4
13150 
    generic map(
13151 
      INIT => X"FDF0"
13152 
    )
13153 
    port map (
13154 
      I0 => rsync_i,
13155 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
13156 
      I2 => N93,
13157 
      I3 => fax4_ins_mux_a0_1_Q,
13158 
      O => fax4_ins_a0_mux0000(9)
13159 
    );
13160 
  fax4_ins_a0_mux0000_5_Q : LUT4
13161 
    generic map(
13162 
      INIT => X"FDF0"
13163 
    )
13164 
    port map (
13165 
      I0 => rsync_i,
13166 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
13167 
      I2 => N95,
13168 
      I3 => fax4_ins_mux_a0_1_Q,
13169 
      O => fax4_ins_a0_mux0000(5)
13170 
    );
13171 
  fax4_ins_a0_mux0000_4_Q : LUT4
13172 
    generic map(
13173 
      INIT => X"FDF0"
13174 
    )
13175 
    port map (
13176 
      I0 => rsync_i,
13177 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
13178 
      I2 => N97,
13179 
      I3 => fax4_ins_mux_a0_1_Q,
13180 
      O => fax4_ins_a0_mux0000(4)
13181 
    );
13182 
  fax4_ins_a0_mux0000_3_Q : LUT4
13183 
    generic map(
13184 
      INIT => X"FDF0"
13185 
    )
13186 
    port map (
13187 
      I0 => rsync_i,
13188 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
13189 
      I2 => N99,
13190 
      I3 => fax4_ins_mux_a0_1_Q,
13191 
      O => fax4_ins_a0_mux0000(3)
13192 
    );
13193 
  fax4_ins_a0_mux0000_2_Q : LUT4
13194 
    generic map(
13195 
      INIT => X"FDF0"
13196 
    )
13197 
    port map (
13198 
      I0 => rsync_i,
13199 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
13200 
      I2 => N101,
13201 
      I3 => fax4_ins_mux_a0_1_Q,
13202 
      O => fax4_ins_a0_mux0000(2)
13203 
    );
13204 
  fax4_ins_a0_mux0000_0_Q : LUT4
13205 
    generic map(
13206 
      INIT => X"FDF0"
13207 
    )
13208 
    port map (
13209 
      I0 => rsync_i,
13210 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
13211 
      I2 => N103,
13212 
      I3 => fax4_ins_mux_a0_1_Q,
13213 
      O => fax4_ins_a0_mux0000(0)
13214 
    );
13215 
  fax4_ins_a0_to_white_mux00007 : LUT3
13216 
    generic map(
13217 
      INIT => X"E4"
13218 
    )
13219 
    port map (
13220 
      I0 => rsync_i,
13221 
      I1 => fax4_ins_pix_prev_1321,
13222 
      I2 => fax4_ins_to_white_1349,
13223 
      O => fax4_ins_a0_to_white_mux00007_949
13224 
    );
13225 
  fax4_ins_a0_mux0000_8_1 : LUT4
13226 
    generic map(
13227 
      INIT => X"ECA0"
13228 
    )
13229 
    port map (
13230 
      I0 => fax4_ins_b2(1),
13231 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
13232 
      I2 => N489,
13233 
      I3 => fax4_ins_N01,
13234 
      O => fax4_ins_a0_mux0000(8)
13235 
    );
13236 
  fax4_ins_a0_mux0000_7_1 : LUT4
13237 
    generic map(
13238 
      INIT => X"ECA0"
13239 
    )
13240 
    port map (
13241 
      I0 => fax4_ins_b2(2),
13242 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
13243 
      I2 => fax4_ins_mux_a0_3_Q,
13244 
      I3 => N490,
13245 
      O => fax4_ins_a0_mux0000(7)
13246 
    );
13247 
  fax4_ins_a0_mux0000_6_1 : LUT4
13248 
    generic map(
13249 
      INIT => X"ECA0"
13250 
    )
13251 
    port map (
13252 
      I0 => fax4_ins_b2(3),
13253 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
13254 
      I2 => fax4_ins_mux_a0_3_Q,
13255 
      I3 => fax4_ins_N01,
13256 
      O => fax4_ins_a0_mux0000(6)
13257 
    );
13258 
  fax4_ins_a0_mux0000_1_1 : LUT4
13259 
    generic map(
13260 
      INIT => X"ECA0"
13261 
    )
13262 
    port map (
13263 
      I0 => fax4_ins_b2(8),
13264 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
13265 
      I2 => fax4_ins_mux_a0_3_Q,
13266 
      I3 => fax4_ins_N01,
13267 
      O => fax4_ins_a0_mux0000(1)
13268 
    );
13269 
  fax4_ins_vertical_mode_cmp_le000020 : LUT2
13270 
    generic map(
13271 
      INIT => X"8"
13272 
    )
13273 
    port map (
13274 
      I0 => fax4_ins_a1b1(10),
13275 
      I1 => fax4_ins_vertical_mode_addsub0000(10),
13276 
      O => fax4_ins_vertical_mode_cmp_le000020_1361
13277 
    );
13278 
  fax4_ins_vertical_mode_cmp_le0000213 : LUT3
13279 
    generic map(
13280 
      INIT => X"57"
13281 
    )
13282 
    port map (
13283 
      I0 => fax4_ins_a1b1(10),
13284 
      I1 => fax4_ins_vertical_mode_addsub0000(8),
13285 
      I2 => fax4_ins_vertical_mode_addsub0000(9),
13286 
      O => fax4_ins_vertical_mode_cmp_le0000213_1363
13287 
    );
13288 
  fax4_ins_vertical_mode_cmp_le0000226 : LUT3
13289 
    generic map(
13290 
      INIT => X"57"
13291 
    )
13292 
    port map (
13293 
      I0 => fax4_ins_a1b1(10),
13294 
      I1 => fax4_ins_vertical_mode_addsub0000(6),
13295 
      I2 => fax4_ins_vertical_mode_addsub0000(7),
13296 
      O => fax4_ins_vertical_mode_cmp_le0000226_1365
13297 
    );
13298 
  huffman_ins_v2_code_table_ins_makeup_white_6 : FDS
13299 
    generic map(
13300 
      INIT => '0'
13301 
    )
13302 
    port map (
13303 
      C => pclk_i,
13304 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000161,
13305 
      S => huffman_ins_v2_run_length_white(9),
13306 
      Q => huffman_ins_v2_code_table_ins_makeup_white(6)
13307 
    );
13308 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001611 : LUT3
13309 
    generic map(
13310 
      INIT => X"80"
13311 
    )
13312 
    port map (
13313 
      I0 => huffman_ins_v2_run_length_white(8),
13314 
      I1 => huffman_ins_v2_run_length_white(6),
13315 
      I2 => huffman_ins_v2_run_length_white(7),
13316 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000161
13317 
    );
13318 
  huffman_ins_v2_code_table_ins_makeup_white_8 : FDR
13319 
    generic map(
13320 
      INIT => '0'
13321 
    )
13322 
    port map (
13323 
      C => pclk_i,
13324 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000181,
13325 
      R => huffman_ins_v2_run_length_white(8),
13326 
      Q => huffman_ins_v2_code_table_ins_makeup_white(8)
13327 
    );
13328 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001811 : LUT3
13329 
    generic map(
13330 
      INIT => X"01"
13331 
    )
13332 
    port map (
13333 
      I0 => huffman_ins_v2_run_length_white(9),
13334 
      I1 => huffman_ins_v2_run_length_white(6),
13335 
      I2 => huffman_ins_v2_run_length_white(7),
13336 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000181
13337 
    );
13338 
  huffman_ins_v2_code_table_ins_makeup_white_10 : FDR
13339 
    generic map(
13340 
      INIT => '0'
13341 
    )
13342 
    port map (
13343 
      C => pclk_i,
13344 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001101,
13345 
      R => huffman_ins_v2_run_length_white(9),
13346 
      Q => huffman_ins_v2_code_table_ins_makeup_white(10)
13347 
    );
13348 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00011011 : LUT3
13349 
    generic map(
13350 
      INIT => X"18"
13351 
    )
13352 
    port map (
13353 
      I0 => huffman_ins_v2_run_length_white(6),
13354 
      I1 => huffman_ins_v2_run_length_white(7),
13355 
      I2 => huffman_ins_v2_run_length_white(8),
13356 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001101
13357 
    );
13358 
  huffman_ins_v2_code_table_ins_makeup_white_11 : FDR
13359 
    generic map(
13360 
      INIT => '0'
13361 
    )
13362 
    port map (
13363 
      C => pclk_i,
13364 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00011111,
13365 
      R => huffman_ins_v2_run_length_white(9),
13366 
      Q => huffman_ins_v2_code_table_ins_makeup_white(11)
13367 
    );
13368 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux000111111 : LUT3
13369 
    generic map(
13370 
      INIT => X"36"
13371 
    )
13372 
    port map (
13373 
      I0 => huffman_ins_v2_run_length_white(7),
13374 
      I1 => huffman_ins_v2_run_length_white(8),
13375 
      I2 => huffman_ins_v2_run_length_white(6),
13376 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00011111
13377 
    );
13378 
  huffman_ins_v2_code_table_ins_makeup_white_12 : FDS
13379 
    generic map(
13380 
      INIT => '0'
13381 
    )
13382 
    port map (
13383 
      C => pclk_i,
13384 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001121,
13385 
      S => huffman_ins_v2_run_length_white(9),
13386 
      Q => huffman_ins_v2_code_table_ins_makeup_white(12)
13387 
    );
13388 
  huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux00011211 : LUT3
13389 
    generic map(
13390 
      INIT => X"C8"
13391 
    )
13392 
    port map (
13393 
      I0 => huffman_ins_v2_run_length_white(6),
13394 
      I1 => huffman_ins_v2_run_length_white(8),
13395 
      I2 => huffman_ins_v2_run_length_white(7),
13396 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_white_mux0001121
13397 
    );
13398 
  huffman_ins_v2_code_table_ins_makeup_black_0 : FDS
13399 
    generic map(
13400 
      INIT => '0'
13401 
    )
13402 
    port map (
13403 
      C => pclk_i,
13404 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000112,
13405 
      S => huffman_ins_v2_run_length_black(6),
13406 
      Q => huffman_ins_v2_code_table_ins_makeup_black_0_Q
13407 
    );
13408 
  huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux0001121 : LUT3
13409 
    generic map(
13410 
      INIT => X"10"
13411 
    )
13412 
    port map (
13413 
      I0 => huffman_ins_v2_run_length_black(9),
13414 
      I1 => huffman_ins_v2_run_length_black(7),
13415 
      I2 => huffman_ins_v2_run_length_black(8),
13416 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000112
13417 
    );
13418 
  huffman_ins_v2_code_table_ins_makeup_black_6 : FDS
13419 
    generic map(
13420 
      INIT => '0'
13421 
    )
13422 
    port map (
13423 
      C => pclk_i,
13424 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000161,
13425 
      S => huffman_ins_v2_run_length_black(9),
13426 
      Q => huffman_ins_v2_code_table_ins_makeup_black_6_Q
13427 
    );
13428 
  huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux0001611 : LUT3
13429 
    generic map(
13430 
      INIT => X"26"
13431 
    )
13432 
    port map (
13433 
      I0 => huffman_ins_v2_run_length_black(7),
13434 
      I1 => huffman_ins_v2_run_length_black(8),
13435 
      I2 => huffman_ins_v2_run_length_black(6),
13436 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000161
13437 
    );
13438 
  huffman_ins_v2_code_table_ins_makeup_black_7 : FDR
13439 
    generic map(
13440 
      INIT => '0'
13441 
    )
13442 
    port map (
13443 
      C => pclk_i,
13444 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000171,
13445 
      R => huffman_ins_v2_run_length_black(8),
13446 
      Q => huffman_ins_v2_code_table_ins_makeup_black_7_Q
13447 
    );
13448 
  huffman_ins_v2_code_table_ins_makeup_black_8 : FDR
13449 
    generic map(
13450 
      INIT => '0'
13451 
    )
13452 
    port map (
13453 
      C => pclk_i,
13454 
      D => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux0001101,
13455 
      R => huffman_ins_v2_run_length_black(6),
13456 
      Q => huffman_ins_v2_code_table_ins_makeup_black_8_Q
13457 
    );
13458 
  huffman_ins_v2_code_table_ins_makeup_black_14 : FDR
13459 
    generic map(
13460 
      INIT => '0'
13461 
    )
13462 
    port map (
13463 
      C => pclk_i,
13464 
      D => huffman_ins_v2_run_length_black(6),
13465 
      R => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000115,
13466 
      Q => huffman_ins_v2_code_table_ins_makeup_black_14_Q
13467 
    );
13468 
  huffman_ins_v2_code_table_ins_makeup_black_16 : FDS
13469 
    generic map(
13470 
      INIT => '0'
13471 
    )
13472 
    port map (
13473 
      C => pclk_i,
13474 
      D => huffman_ins_v2_run_length_black(6),
13475 
      S => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000115,
13476 
      Q => huffman_ins_v2_code_table_ins_makeup_black_16_Q
13477 
    );
13478 
  huffman_ins_v2_pass_vert_code_width_1_0 : FDR
13479 
    generic map(
13480 
      INIT => '0'
13481 
    )
13482 
    port map (
13483 
      C => pclk_i,
13484 
      D => huffman_ins_v2_Mrom_run_length_i_rom000012,
13485 
      R => fax4_ins_mode_indicator_o(3),
13486 
      Q => huffman_ins_v2_pass_vert_code_width_1_0_Q
13487 
    );
13488 
  huffman_ins_v2_Mrom_run_length_i_rom0000121 : LUT3
13489 
    generic map(
13490 
      INIT => X"67"
13491 
    )
13492 
    port map (
13493 
      I0 => fax4_ins_mode_indicator_o(0),
13494 
      I1 => fax4_ins_mode_indicator_o(2),
13495 
      I2 => fax4_ins_mode_indicator_o(1),
13496 
      O => huffman_ins_v2_Mrom_run_length_i_rom000012
13497 
    );
13498 
  huffman_ins_v2_pass_vert_code_1_1 : FDR
13499 
    generic map(
13500 
      INIT => '0'
13501 
    )
13502 
    port map (
13503 
      C => pclk_i,
13504 
      D => huffman_ins_v2_Mrom_run_length_i_rom0000111,
13505 
      R => fax4_ins_mode_indicator_o(3),
13506 
      Q => huffman_ins_v2_pass_vert_code_1(1)
13507 
    );
13508 
  huffman_ins_v2_Mrom_run_length_i_rom00001111 : LUT3
13509 
    generic map(
13510 
      INIT => X"7E"
13511 
    )
13512 
    port map (
13513 
      I0 => fax4_ins_mode_indicator_o(0),
13514 
      I1 => fax4_ins_mode_indicator_o(1),
13515 
      I2 => fax4_ins_mode_indicator_o(2),
13516 
      O => huffman_ins_v2_Mrom_run_length_i_rom0000111
13517 
    );
13518 
  huffman_ins_v2_code_white_7 : FDS
13519 
    generic map(
13520 
      INIT => '0'
13521 
    )
13522 
    port map (
13523 
      C => pclk_i,
13524 
      D => huffman_ins_v2_code_white_7_mux000021_1781,
13525 
      S => huffman_ins_v2_code_white_7_mux000010_1780,
13526 
      Q => huffman_ins_v2_code_white(7)
13527 
    );
13528 
  huffman_ins_v2_code_white_6 : FDS
13529 
    generic map(
13530 
      INIT => '0'
13531 
    )
13532 
    port map (
13533 
      C => pclk_i,
13534 
      D => huffman_ins_v2_code_white_6_mux000021_1777,
13535 
      S => huffman_ins_v2_code_white_6_mux000014_1776,
13536 
      Q => huffman_ins_v2_code_white(6)
13537 
    );
13538 
  huffman_ins_v2_code_white_4 : FDS
13539 
    generic map(
13540 
      INIT => '0'
13541 
    )
13542 
    port map (
13543 
      C => pclk_i,
13544 
      D => huffman_ins_v2_code_white_4_mux000039_1769,
13545 
      S => huffman_ins_v2_code_white_4_mux000028,
13546 
      Q => huffman_ins_v2_code_white(4)
13547 
    );
13548 
  huffman_ins_v2_code_white_5 : FDS
13549 
    generic map(
13550 
      INIT => '0'
13551 
    )
13552 
    port map (
13553 
      C => pclk_i,
13554 
      D => huffman_ins_v2_code_white_5_mux000039_1774,
13555 
      S => huffman_ins_v2_code_white_5_mux000028,
13556 
      Q => huffman_ins_v2_code_white(5)
13557 
    );
13558 
  huffman_ins_v2_hor_code_9 : FDS
13559 
    generic map(
13560 
      INIT => '0'
13561 
    )
13562 
    port map (
13563 
      C => pclk_i,
13564 
      D => huffman_ins_v2_hor_code_9_mux0003147,
13565 
      S => huffman_ins_v2_hor_code_9_mux000342_2045,
13566 
      Q => huffman_ins_v2_hor_code(9)
13567 
    );
13568 
  huffman_ins_v2_hor_code_8 : FDS
13569 
    generic map(
13570 
      INIT => '0'
13571 
    )
13572 
    port map (
13573 
      C => pclk_i,
13574 
      D => huffman_ins_v2_hor_code_8_mux0003165,
13575 
      S => huffman_ins_v2_hor_code_8_mux000392_2038,
13576 
      Q => huffman_ins_v2_hor_code(8)
13577 
    );
13578 
  huffman_ins_v2_hor_code_8_mux00031651 : LUT3
13579 
    generic map(
13580 
      INIT => X"EA"
13581 
    )
13582 
    port map (
13583 
      I0 => huffman_ins_v2_hor_code_8_mux0003151_2033,
13584 
      I1 => huffman_ins_v2_hor_code(8),
13585 
      I2 => huffman_ins_v2_hor_code_8_mux000341_2036,
13586 
      O => huffman_ins_v2_hor_code_8_mux0003165
13587 
    );
13588 
  huffman_ins_v2_code_black_23 : FDS
13589 
    generic map(
13590 
      INIT => '0'
13591 
    )
13592 
    port map (
13593 
      C => pclk_i,
13594 
      D => huffman_ins_v2_code_black_23_mux0000172,
13595 
      S => huffman_ins_v2_code_black_23_mux0000169_1615,
13596 
      Q => huffman_ins_v2_code_black(23)
13597 
    );
13598 
  huffman_ins_v2_code_black_23_mux00001721 : LUT3
13599 
    generic map(
13600 
      INIT => X"C8"
13601 
    )
13602 
    port map (
13603 
      I0 => huffman_ins_v2_code_black_23_mux0000112_1613,
13604 
      I1 => huffman_ins_v2_codetab_ter_black_width(3),
13605 
      I2 => huffman_ins_v2_code_black_23_mux0000128_1614,
13606 
      O => huffman_ins_v2_code_black_23_mux0000172
13607 
    );
13608 
  huffman_ins_v2_hor_code_7 : FDS
13609 
    generic map(
13610 
      INIT => '0'
13611 
    )
13612 
    port map (
13613 
      C => pclk_i,
13614 
      D => huffman_ins_v2_hor_code_7_mux000381,
13615 
      S => huffman_ins_v2_hor_code_7_mux000325_2023,
13616 
      Q => huffman_ins_v2_hor_code(7)
13617 
    );
13618 
  huffman_ins_v2_hor_code_7_mux0003811 : LUT3
13619 
    generic map(
13620 
      INIT => X"EA"
13621 
    )
13622 
    port map (
13623 
      I0 => huffman_ins_v2_hor_code_7_mux000370_2027,
13624 
      I1 => huffman_ins_v2_hor_code(7),
13625 
      I2 => huffman_ins_v2_hor_code_7_mux00035_2024,
13626 
      O => huffman_ins_v2_hor_code_7_mux000381
13627 
    );
13628 
  huffman_ins_v2_code_black_22 : FDS
13629 
    generic map(
13630 
      INIT => '0'
13631 
    )
13632 
    port map (
13633 
      C => pclk_i,
13634 
      D => huffman_ins_v2_code_black_22_mux0000172,
13635 
      S => huffman_ins_v2_code_black_22_mux0000169_1610,
13636 
      Q => huffman_ins_v2_code_black(22)
13637 
    );
13638 
  huffman_ins_v2_code_black_22_mux00001721 : LUT3
13639 
    generic map(
13640 
      INIT => X"C8"
13641 
    )
13642 
    port map (
13643 
      I0 => huffman_ins_v2_code_black_22_mux0000112_1607,
13644 
      I1 => huffman_ins_v2_codetab_ter_black_width(3),
13645 
      I2 => huffman_ins_v2_code_black_22_mux0000128_1609,
13646 
      O => huffman_ins_v2_code_black_22_mux0000172
13647 
    );
13648 
  huffman_ins_v2_hor_code_6 : FDS
13649 
    generic map(
13650 
      INIT => '0'
13651 
    )
13652 
    port map (
13653 
      C => pclk_i,
13654 
      D => huffman_ins_v2_hor_code_6_mux000371,
13655 
      S => huffman_ins_v2_hor_code_6_mux000329_2016,
13656 
      Q => huffman_ins_v2_hor_code(6)
13657 
    );
13658 
  huffman_ins_v2_hor_code_6_mux0003711 : LUT3
13659 
    generic map(
13660 
      INIT => X"EA"
13661 
    )
13662 
    port map (
13663 
      I0 => huffman_ins_v2_hor_code_6_mux000367_2019,
13664 
      I1 => huffman_ins_v2_code_white(6),
13665 
      I2 => huffman_ins_v2_hor_code_6_mux000343_2017,
13666 
      O => huffman_ins_v2_hor_code_6_mux000371
13667 
    );
13668 
  huffman_ins_v2_hor_code_5 : FDS
13669 
    generic map(
13670 
      INIT => '0'
13671 
    )
13672 
    port map (
13673 
      C => pclk_i,
13674 
      D => huffman_ins_v2_hor_code_5_mux0003102,
13675 
      S => huffman_ins_v2_hor_code_5_mux000327_2008,
13676 
      Q => huffman_ins_v2_hor_code(5)
13677 
    );
13678 
  huffman_ins_v2_hor_code_5_mux00031021 : LUT3
13679 
    generic map(
13680 
      INIT => X"EA"
13681 
    )
13682 
    port map (
13683 
      I0 => huffman_ins_v2_hor_code_5_mux000380_2012,
13684 
      I1 => huffman_ins_v2_N39,
13685 
      I2 => huffman_ins_v2_hor_code_5_mux000349_2009,
13686 
      O => huffman_ins_v2_hor_code_5_mux0003102
13687 
    );
13688 
  huffman_ins_v2_code_black_20 : FDS
13689 
    generic map(
13690 
      INIT => '0'
13691 
    )
13692 
    port map (
13693 
      C => pclk_i,
13694 
      D => huffman_ins_v2_code_black_20_mux0000187_1599,
13695 
      S => huffman_ins_v2_code_black_20_mux0000166_1598,
13696 
      Q => huffman_ins_v2_code_black(20)
13697 
    );
13698 
  huffman_ins_v2_hor_code_4 : FDS
13699 
    generic map(
13700 
      INIT => '0'
13701 
    )
13702 
    port map (
13703 
      C => pclk_i,
13704 
      D => huffman_ins_v2_hor_code_4_mux0003110,
13705 
      S => huffman_ins_v2_hor_code_4_mux000333_2001,
13706 
      Q => huffman_ins_v2_hor_code(4)
13707 
    );
13708 
  huffman_ins_v2_hor_code_4_mux00031101 : LUT3
13709 
    generic map(
13710 
      INIT => X"EA"
13711 
    )
13712 
    port map (
13713 
      I0 => huffman_ins_v2_hor_code_4_mux000388_2004,
13714 
      I1 => huffman_ins_v2_N40,
13715 
      I2 => huffman_ins_v2_hor_code_4_mux000358_2002,
13716 
      O => huffman_ins_v2_hor_code_4_mux0003110
13717 
    );
13718 
  huffman_ins_v2_hor_code_3 : FDS
13719 
    generic map(
13720 
      INIT => '0'
13721 
    )
13722 
    port map (
13723 
      C => pclk_i,
13724 
      D => huffman_ins_v2_hor_code_3_mux000397_1995,
13725 
      S => huffman_ins_v2_hor_code_3_mux000342_1994,
13726 
      Q => huffman_ins_v2_hor_code(3)
13727 
    );
13728 
  huffman_ins_v2_hor_code_2 : FDS
13729 
    generic map(
13730 
      INIT => '0'
13731 
    )
13732 
    port map (
13733 
      C => pclk_i,
13734 
      D => huffman_ins_v2_hor_code_2_mux0003129,
13735 
      S => huffman_ins_v2_hor_code_2_mux000385_1989,
13736 
      Q => huffman_ins_v2_hor_code(2)
13737 
    );
13738 
  huffman_ins_v2_hor_code_2_mux00031291 : LUT2
13739 
    generic map(
13740 
      INIT => X"8"
13741 
    )
13742 
    port map (
13743 
      I0 => huffman_ins_v2_hor_code_2_mux0003104_1983,
13744 
      I1 => huffman_ins_v2_hor_code_2_mux0003117_1984,
13745 
      O => huffman_ins_v2_hor_code_2_mux0003129
13746 
    );
13747 
  huffman_ins_v2_hor_code_1 : FDS
13748 
    generic map(
13749 
      INIT => '0'
13750 
    )
13751 
    port map (
13752 
      C => pclk_i,
13753 
      D => huffman_ins_v2_hor_code_1_mux0003120_1930,
13754 
      S => huffman_ins_v2_hor_code_1_mux000386_1935,
13755 
      Q => huffman_ins_v2_hor_code(1)
13756 
    );
13757 
  huffman_ins_v2_hor_code_0 : FDS
13758 
    generic map(
13759 
      INIT => '0'
13760 
    )
13761 
    port map (
13762 
      C => pclk_i,
13763 
      D => huffman_ins_v2_hor_code_0_mux000352_1819,
13764 
      S => huffman_ins_v2_hor_code_0_mux000324_1818,
13765 
      Q => huffman_ins_v2_hor_code(0)
13766 
    );
13767 
  huffman_ins_v2_hor_code_25 : FDS
13768 
    generic map(
13769 
      INIT => '0'
13770 
    )
13771 
    port map (
13772 
      C => pclk_i,
13773 
      D => huffman_ins_v2_hor_code_25_mux0003112,
13774 
      S => huffman_ins_v2_hor_code_25_mux00030_1979,
13775 
      Q => huffman_ins_v2_hor_code(25)
13776 
    );
13777 
  huffman_ins_v2_hor_code_25_mux00031121 : LUT2
13778 
    generic map(
13779 
      INIT => X"8"
13780 
    )
13781 
    port map (
13782 
      I0 => huffman_ins_v2_hor_code(25),
13783 
      I1 => huffman_ins_v2_hor_code_25_mux000380_1982,
13784 
      O => huffman_ins_v2_hor_code_25_mux0003112
13785 
    );
13786 
  huffman_ins_v2_hor_code_19 : FDS
13787 
    generic map(
13788 
      INIT => '0'
13789 
    )
13790 
    port map (
13791 
      C => pclk_i,
13792 
      D => huffman_ins_v2_hor_code_19_mux0003138_1925,
13793 
      S => huffman_ins_v2_hor_code_19_mux000380_1928,
13794 
      Q => huffman_ins_v2_hor_code(19)
13795 
    );
13796 
  huffman_ins_v2_hor_code_24 : FDS
13797 
    generic map(
13798 
      INIT => '0'
13799 
    )
13800 
    port map (
13801 
      C => pclk_i,
13802 
      D => huffman_ins_v2_hor_code_24_mux000371_1977,
13803 
      S => huffman_ins_v2_hor_code_24_mux000316_1974,
13804 
      Q => huffman_ins_v2_hor_code(24)
13805 
    );
13806 
  huffman_ins_v2_hor_code_23 : FDS
13807 
    generic map(
13808 
      INIT => '0'
13809 
    )
13810 
    port map (
13811 
      C => pclk_i,
13812 
      D => huffman_ins_v2_hor_code_23_mux000373,
13813 
      S => huffman_ins_v2_hor_code_23_mux00039_1971,
13814 
      Q => huffman_ins_v2_hor_code(23)
13815 
    );
13816 
  huffman_ins_v2_hor_code_23_mux0003731 : LUT3
13817 
    generic map(
13818 
      INIT => X"EA"
13819 
    )
13820 
    port map (
13821 
      I0 => huffman_ins_v2_hor_code_23_mux000322_1968,
13822 
      I1 => huffman_ins_v2_hor_code(23),
13823 
      I2 => huffman_ins_v2_hor_code_23_mux000356_1969,
13824 
      O => huffman_ins_v2_hor_code_23_mux000373
13825 
    );
13826 
  huffman_ins_v2_hor_code_18 : FDS
13827 
    generic map(
13828 
      INIT => '0'
13829 
    )
13830 
    port map (
13831 
      C => pclk_i,
13832 
      D => huffman_ins_v2_hor_code_18_mux0003230_1920,
13833 
      S => huffman_ins_v2_hor_code_18_mux0003130_1916,
13834 
      Q => huffman_ins_v2_hor_code(18)
13835 
    );
13836 
  huffman_ins_v2_hor_code_22 : FDS
13837 
    generic map(
13838 
      INIT => '0'
13839 
    )
13840 
    port map (
13841 
      C => pclk_i,
13842 
      D => huffman_ins_v2_hor_code_22_mux0003135_1960,
13843 
      S => huffman_ins_v2_hor_code_22_mux000385_1965,
13844 
      Q => huffman_ins_v2_hor_code(22)
13845 
    );
13846 
  huffman_ins_v2_hor_code_17 : FDS
13847 
    generic map(
13848 
      INIT => '0'
13849 
    )
13850 
    port map (
13851 
      C => pclk_i,
13852 
      D => huffman_ins_v2_hor_code_17_mux0003153,
13853 
      S => huffman_ins_v2_hor_code_17_mux000353_1910,
13854 
      Q => huffman_ins_v2_hor_code(17)
13855 
    );
13856 
  huffman_ins_v2_hor_code_16 : FDS
13857 
    generic map(
13858 
      INIT => '0'
13859 
    )
13860 
    port map (
13861 
      C => pclk_i,
13862 
      D => huffman_ins_v2_hor_code_16_mux0003138_1899,
13863 
      S => huffman_ins_v2_hor_code_16_mux0003102_1896,
13864 
      Q => huffman_ins_v2_hor_code(16)
13865 
    );
13866 
  huffman_ins_v2_hor_code_21 : FDS
13867 
    generic map(
13868 
      INIT => '0'
13869 
    )
13870 
    port map (
13871 
      C => pclk_i,
13872 
      D => huffman_ins_v2_hor_code_21_mux0003179_1952,
13873 
      S => huffman_ins_v2_hor_code_21_mux000379_1956,
13874 
      Q => huffman_ins_v2_hor_code(21)
13875 
    );
13876 
  huffman_ins_v2_hor_code_20 : FDS
13877 
    generic map(
13878 
      INIT => '0'
13879 
    )
13880 
    port map (
13881 
      C => pclk_i,
13882 
      D => huffman_ins_v2_hor_code_20_mux0003171,
13883 
      S => huffman_ins_v2_hor_code_20_mux0003105_1939,
13884 
      Q => huffman_ins_v2_hor_code(20)
13885 
    );
13886 
  huffman_ins_v2_hor_code_20_mux00031711 : LUT3
13887 
    generic map(
13888 
      INIT => X"EA"
13889 
    )
13890 
    port map (
13891 
      I0 => huffman_ins_v2_hor_code_20_mux0003158_1943,
13892 
      I1 => huffman_ins_v2_hor_code(20),
13893 
      I2 => huffman_ins_v2_hor_code_20_mux000370_1947,
13894 
      O => huffman_ins_v2_hor_code_20_mux0003171
13895 
    );
13896 
  huffman_ins_v2_hor_code_15 : FDS
13897 
    generic map(
13898 
      INIT => '0'
13899 
    )
13900 
    port map (
13901 
      C => pclk_i,
13902 
      D => huffman_ins_v2_hor_code_15_mux0003157,
13903 
      S => huffman_ins_v2_hor_code_15_mux000326_1887,
13904 
      Q => huffman_ins_v2_hor_code(15)
13905 
    );
13906 
  huffman_ins_v2_hor_code_15_mux00031571 : LUT3
13907 
    generic map(
13908 
      INIT => X"32"
13909 
    )
13910 
    port map (
13911 
      I0 => huffman_ins_v2_hor_code_15_mux0003122_1884,
13912 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
13913 
      I2 => huffman_ins_v2_hor_code_15_mux000380_1894,
13914 
      O => huffman_ins_v2_hor_code_15_mux0003157
13915 
    );
13916 
  huffman_ins_v2_hor_code_14 : FDS
13917 
    generic map(
13918 
      INIT => '0'
13919 
    )
13920 
    port map (
13921 
      C => pclk_i,
13922 
      D => huffman_ins_v2_hor_code_14_mux0003301_1878,
13923 
      S => huffman_ins_v2_hor_code_14_mux0003139_1867,
13924 
      Q => huffman_ins_v2_hor_code(14)
13925 
    );
13926 
  huffman_ins_v2_code_white_14 : FDS
13927 
    generic map(
13928 
      INIT => '0'
13929 
    )
13930 
    port map (
13931 
      C => pclk_i,
13932 
      D => huffman_ins_v2_code_white_14_mux000014,
13933 
      S => huffman_ins_v2_code_white_14_mux00004_1754,
13934 
      Q => huffman_ins_v2_code_white(14)
13935 
    );
13936 
  huffman_ins_v2_code_white_15 : FDS
13937 
    generic map(
13938 
      INIT => '0'
13939 
    )
13940 
    port map (
13941 
      C => pclk_i,
13942 
      D => huffman_ins_v2_code_white_15_mux00001_1756,
13943 
      S => N7,
13944 
      Q => huffman_ins_v2_code_white(15)
13945 
    );
13946 
  huffman_ins_v2_code_white_13 : FDS
13947 
    generic map(
13948 
      INIT => '0'
13949 
    )
13950 
    port map (
13951 
      C => pclk_i,
13952 
      D => huffman_ins_v2_code_white_13_mux000015_1750,
13953 
      S => huffman_ins_v2_code_white_13_mux00006_1751,
13954 
      Q => huffman_ins_v2_code_white(13)
13955 
    );
13956 
  huffman_ins_v2_hor_code_12 : FDS
13957 
    generic map(
13958 
      INIT => '0'
13959 
    )
13960 
    port map (
13961 
      C => pclk_i,
13962 
      D => huffman_ins_v2_hor_code_12_mux0003249_1847,
13963 
      S => huffman_ins_v2_hor_code_12_mux0003219_1845,
13964 
      Q => huffman_ins_v2_hor_code(12)
13965 
    );
13966 
  huffman_ins_v2_hor_code_13 : FDS
13967 
    generic map(
13968 
      INIT => '0'
13969 
    )
13970 
    port map (
13971 
      C => pclk_i,
13972 
      D => huffman_ins_v2_hor_code_13_mux0003198,
13973 
      S => huffman_ins_v2_hor_code_13_mux000389_1860,
13974 
      Q => huffman_ins_v2_hor_code(13)
13975 
    );
13976 
  huffman_ins_v2_hor_code_13_mux00031981 : LUT3
13977 
    generic map(
13978 
      INIT => X"EA"
13979 
    )
13980 
    port map (
13981 
      I0 => huffman_ins_v2_hor_code_13_mux0003181_1854,
13982 
      I1 => huffman_ins_v2_hor_code(13),
13983 
      I2 => huffman_ins_v2_hor_code_13_mux000350_1858,
13984 
      O => huffman_ins_v2_hor_code_13_mux0003198
13985 
    );
13986 
  huffman_ins_v2_hor_code_11 : FDS
13987 
    generic map(
13988 
      INIT => '0'
13989 
    )
13990 
    port map (
13991 
      C => pclk_i,
13992 
      D => huffman_ins_v2_hor_code_11_mux0003141,
13993 
      S => huffman_ins_v2_hor_code_11_mux000374_1836,
13994 
      Q => huffman_ins_v2_hor_code(11)
13995 
    );
13996 
  huffman_ins_v2_hor_code_11_mux00031411 : LUT3
13997 
    generic map(
13998 
      INIT => X"EA"
13999 
    )
14000 
    port map (
14001 
      I0 => huffman_ins_v2_hor_code_11_mux0003129_1831,
14002 
      I1 => huffman_ins_v2_hor_code(11),
14003 
      I2 => huffman_ins_v2_hor_code_11_mux000338_1834,
14004 
      O => huffman_ins_v2_hor_code_11_mux0003141
14005 
    );
14006 
  huffman_ins_v2_code_white_12 : FDS
14007 
    generic map(
14008 
      INIT => '0'
14009 
    )
14010 
    port map (
14011 
      C => pclk_i,
14012 
      D => huffman_ins_v2_code_white_12_mux000021_1746,
14013 
      S => huffman_ins_v2_code_white_12_mux000010_1745,
14014 
      Q => huffman_ins_v2_code_white(12)
14015 
    );
14016 
  huffman_ins_v2_code_white_11 : FDS
14017 
    generic map(
14018 
      INIT => '0'
14019 
    )
14020 
    port map (
14021 
      C => pclk_i,
14022 
      D => huffman_ins_v2_code_white_11_mux000021_1741,
14023 
      S => huffman_ins_v2_code_white_11_mux000010_1740,
14024 
      Q => huffman_ins_v2_code_white(11)
14025 
    );
14026 
  huffman_ins_v2_code_white_10 : FDS
14027 
    generic map(
14028 
      INIT => '0'
14029 
    )
14030 
    port map (
14031 
      C => pclk_i,
14032 
      D => huffman_ins_v2_code_white_10_mux000021_1736,
14033 
      S => huffman_ins_v2_code_white_10_mux000010_1735,
14034 
      Q => huffman_ins_v2_code_white(10)
14035 
    );
14036 
  huffman_ins_v2_code_white_9 : FDS
14037 
    generic map(
14038 
      INIT => '0'
14039 
    )
14040 
    port map (
14041 
      C => pclk_i,
14042 
      D => huffman_ins_v2_code_white_9_mux000021_1795,
14043 
      S => huffman_ins_v2_code_white_9_mux000010_1794,
14044 
      Q => huffman_ins_v2_code_white(9)
14045 
    );
14046 
  huffman_ins_v2_hor_code_10 : FDS
14047 
    generic map(
14048 
      INIT => '0'
14049 
    )
14050 
    port map (
14051 
      C => pclk_i,
14052 
      D => huffman_ins_v2_hor_code_10_mux0003112_1822,
14053 
      S => huffman_ins_v2_hor_code_10_mux000369_1826,
14054 
      Q => huffman_ins_v2_hor_code(10)
14055 
    );
14056 
  huffman_ins_v2_code_white_8 : FDS
14057 
    generic map(
14058 
      INIT => '0'
14059 
    )
14060 
    port map (
14061 
      C => pclk_i,
14062 
      D => huffman_ins_v2_code_white_8_mux000021_1789,
14063 
      S => huffman_ins_v2_code_white_8_mux000010_1788,
14064 
      Q => huffman_ins_v2_code_white(8)
14065 
    );
14066 
  fax4_ins_state_FSM_FFd11 : FDS
14067 
    generic map(
14068 
      INIT => '1'
14069 
    )
14070 
    port map (
14071 
      C => pclk_i,
14072 
      D => fax4_ins_state_FSM_FFd11_In1,
14073 
      S => fax4_ins_state_FSM_FFd1_1322,
14074 
      Q => fax4_ins_state_FSM_FFd11_1325
14075 
    );
14076 
  fax4_ins_state_FSM_FFd11_In11 : LUT3
14077 
    generic map(
14078 
      INIT => X"EA"
14079 
    )
14080 
    port map (
14081 
      I0 => fax4_ins_state_FSM_FFd4_1331,
14082 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14083 
      I2 => fax4_ins_state_FSM_FFd11_1325,
14084 
      O => fax4_ins_state_FSM_FFd11_In1
14085 
    );
14086 
  fax4_ins_state_FSM_FFd8 : FDS
14087 
    generic map(
14088 
      INIT => '0'
14089 
    )
14090 
    port map (
14091 
      C => pclk_i,
14092 
      D => fax4_ins_state_FSM_FFd8_In25,
14093 
      S => fax4_ins_state_FSM_FFd8_In7_1340,
14094 
      Q => fax4_ins_state_FSM_FFd8_1338
14095 
    );
14096 
  fax4_ins_state_FSM_FFd9 : FDR
14097 
    generic map(
14098 
      INIT => '0'
14099 
    )
14100 
    port map (
14101 
      C => pclk_i,
14102 
      D => fax4_ins_state_FSM_FFd9_In1,
14103 
      R => fax4_ins_state_FSM_N7,
14104 
      Q => fax4_ins_state_FSM_FFd9_1341
14105 
    );
14106 
  fax4_ins_state_FSM_FFd1 : FDR
14107 
    generic map(
14108 
      INIT => '0'
14109 
    )
14110 
    port map (
14111 
      C => pclk_i,
14112 
      D => fax4_ins_state_FSM_FFd9_1341,
14113 
      R => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14114 
      Q => fax4_ins_state_FSM_FFd1_1322
14115 
    );
14116 
  fax4_ins_EOF_prev : FDR
14117 
    generic map(
14118 
      INIT => '0'
14119 
    )
14120 
    port map (
14121 
      C => pclk_i,
14122 
      D => N1,
14123 
      R => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14124 
      Q => fax4_ins_EOF_prev_228
14125 
    );
14126 
  fax4_ins_output_valid_o : FDS_1
14127 
    generic map(
14128 
      INIT => '0'
14129 
    )
14130 
    port map (
14131 
      C => pclk_i,
14132 
      D => fax4_ins_output_valid_o_mux000336,
14133 
      S => fax4_ins_output_valid_o_mux000315,
14134 
      Q => fax4_ins_output_valid_o_1311
14135 
    );
14136 
  fax4_ins_state_updated : FDS
14137 
    generic map(
14138 
      INIT => '0'
14139 
    )
14140 
    port map (
14141 
      C => pclk_i,
14142 
      D => fax4_ins_output_valid_o_mux000336,
14143 
      S => fax4_ins_state_updated_mux000854_1348,
14144 
      Q => fax4_ins_state_updated_1345
14145 
    );
14146 
  fax4_ins_state_FSM_FFd4 : FDRS
14147 
    generic map(
14148 
      INIT => '0'
14149 
    )
14150 
    port map (
14151 
      C => pclk_i,
14152 
      D => fax4_ins_state_FSM_FFd4_In11,
14153 
      R => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14154 
      S => fax4_ins_state_FSM_FFd3_1329,
14155 
      Q => fax4_ins_state_FSM_FFd4_1331
14156 
    );
14157 
  fax4_ins_state_FSM_FFd4_In111 : LUT2
14158 
    generic map(
14159 
      INIT => X"2"
14160 
    )
14161 
    port map (
14162 
      I0 => fax4_ins_state_FSM_N12,
14163 
      I1 => fax4_ins_EOF_prev_228,
14164 
      O => fax4_ins_state_FSM_FFd4_In11
14165 
    );
14166 
  huffman_ins_v2_Msub_run_length_white_addsub0000_cy_0_rt : LUT1
14167 
    generic map(
14168 
      INIT => X"2"
14169 
    )
14170 
    port map (
14171 
      I0 => fax4_ins_a1_o(0),
14172 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_cy_0_rt_1404
14173 
    );
14174 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_8_rt : LUT1
14175 
    generic map(
14176 
      INIT => X"2"
14177 
    )
14178 
    port map (
14179 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
14180 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_8_rt_1123
14181 
    );
14182 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_7_rt : LUT1
14183 
    generic map(
14184 
      INIT => X"2"
14185 
    )
14186 
    port map (
14187 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
14188 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_7_rt_1121
14189 
    );
14190 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_6_rt : LUT1
14191 
    generic map(
14192 
      INIT => X"2"
14193 
    )
14194 
    port map (
14195 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
14196 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_6_rt_1119
14197 
    );
14198 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_5_rt : LUT1
14199 
    generic map(
14200 
      INIT => X"2"
14201 
    )
14202 
    port map (
14203 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
14204 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_5_rt_1117
14205 
    );
14206 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_4_rt : LUT1
14207 
    generic map(
14208 
      INIT => X"2"
14209 
    )
14210 
    port map (
14211 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
14212 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_4_rt_1115
14213 
    );
14214 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_3_rt : LUT1
14215 
    generic map(
14216 
      INIT => X"2"
14217 
    )
14218 
    port map (
14219 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
14220 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_3_rt_1113
14221 
    );
14222 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_2_rt : LUT1
14223 
    generic map(
14224 
      INIT => X"2"
14225 
    )
14226 
    port map (
14227 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
14228 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_2_rt_1111
14229 
    );
14230 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_1_rt : LUT1
14231 
    generic map(
14232 
      INIT => X"2"
14233 
    )
14234 
    port map (
14235 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
14236 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_cy_1_rt_1109
14237 
    );
14238 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_7_rt : LUT1
14239 
    generic map(
14240 
      INIT => X"2"
14241 
    )
14242 
    port map (
14243 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(7),
14244 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_7_rt_1173
14245 
    );
14246 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_6_rt : LUT1
14247 
    generic map(
14248 
      INIT => X"2"
14249 
    )
14250 
    port map (
14251 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(6),
14252 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_6_rt_1171
14253 
    );
14254 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_5_rt : LUT1
14255 
    generic map(
14256 
      INIT => X"2"
14257 
    )
14258 
    port map (
14259 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(5),
14260 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_5_rt_1169
14261 
    );
14262 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_4_rt : LUT1
14263 
    generic map(
14264 
      INIT => X"2"
14265 
    )
14266 
    port map (
14267 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(4),
14268 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_4_rt_1167
14269 
    );
14270 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_3_rt : LUT1
14271 
    generic map(
14272 
      INIT => X"2"
14273 
    )
14274 
    port map (
14275 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(3),
14276 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_3_rt_1165
14277 
    );
14278 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_2_rt : LUT1
14279 
    generic map(
14280 
      INIT => X"2"
14281 
    )
14282 
    port map (
14283 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(2),
14284 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_2_rt_1163
14285 
    );
14286 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_1_rt : LUT1
14287 
    generic map(
14288 
      INIT => X"2"
14289 
    )
14290 
    port map (
14291 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(1),
14292 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_cy_1_rt_1161
14293 
    );
14294 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_1_rt : LUT1
14295 
    generic map(
14296 
      INIT => X"2"
14297 
    )
14298 
    port map (
14299 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(1),
14300 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_1_rt_234
14301 
    );
14302 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_2_rt : LUT1
14303 
    generic map(
14304 
      INIT => X"2"
14305 
    )
14306 
    port map (
14307 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(2),
14308 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_2_rt_236
14309 
    );
14310 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_3_rt : LUT1
14311 
    generic map(
14312 
      INIT => X"2"
14313 
    )
14314 
    port map (
14315 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(3),
14316 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_3_rt_238
14317 
    );
14318 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_4_rt : LUT1
14319 
    generic map(
14320 
      INIT => X"2"
14321 
    )
14322 
    port map (
14323 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(4),
14324 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_4_rt_240
14325 
    );
14326 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_5_rt : LUT1
14327 
    generic map(
14328 
      INIT => X"2"
14329 
    )
14330 
    port map (
14331 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(5),
14332 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_5_rt_242
14333 
    );
14334 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_6_rt : LUT1
14335 
    generic map(
14336 
      INIT => X"2"
14337 
    )
14338 
    port map (
14339 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(6),
14340 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_6_rt_244
14341 
    );
14342 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_7_rt : LUT1
14343 
    generic map(
14344 
      INIT => X"2"
14345 
    )
14346 
    port map (
14347 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(7),
14348 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_7_rt_246
14349 
    );
14350 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_8_rt : LUT1
14351 
    generic map(
14352 
      INIT => X"2"
14353 
    )
14354 
    port map (
14355 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(8),
14356 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_cy_8_rt_248
14357 
    );
14358 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_1_rt : LUT1
14359 
    generic map(
14360 
      INIT => X"2"
14361 
    )
14362 
    port map (
14363 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(1),
14364 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_1_rt_282
14365 
    );
14366 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_2_rt : LUT1
14367 
    generic map(
14368 
      INIT => X"2"
14369 
    )
14370 
    port map (
14371 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(2),
14372 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_2_rt_284
14373 
    );
14374 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_3_rt : LUT1
14375 
    generic map(
14376 
      INIT => X"2"
14377 
    )
14378 
    port map (
14379 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(3),
14380 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_3_rt_286
14381 
    );
14382 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_4_rt : LUT1
14383 
    generic map(
14384 
      INIT => X"2"
14385 
    )
14386 
    port map (
14387 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(4),
14388 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_4_rt_288
14389 
    );
14390 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_5_rt : LUT1
14391 
    generic map(
14392 
      INIT => X"2"
14393 
    )
14394 
    port map (
14395 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(5),
14396 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_5_rt_290
14397 
    );
14398 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_6_rt : LUT1
14399 
    generic map(
14400 
      INIT => X"2"
14401 
    )
14402 
    port map (
14403 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(6),
14404 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_6_rt_292
14405 
    );
14406 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_7_rt : LUT1
14407 
    generic map(
14408 
      INIT => X"2"
14409 
    )
14410 
    port map (
14411 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(7),
14412 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_7_rt_294
14413 
    );
14414 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_8_rt : LUT1
14415 
    generic map(
14416 
      INIT => X"2"
14417 
    )
14418 
    port map (
14419 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(8),
14420 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_cy_8_rt_296
14421 
    );
14422 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_1_rt : LUT1
14423 
    generic map(
14424 
      INIT => X"2"
14425 
    )
14426 
    port map (
14427 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(1),
14428 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_1_rt_475
14429 
    );
14430 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_2_rt : LUT1
14431 
    generic map(
14432 
      INIT => X"2"
14433 
    )
14434 
    port map (
14435 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(2),
14436 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_2_rt_477
14437 
    );
14438 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_3_rt : LUT1
14439 
    generic map(
14440 
      INIT => X"2"
14441 
    )
14442 
    port map (
14443 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(3),
14444 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_3_rt_479
14445 
    );
14446 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_4_rt : LUT1
14447 
    generic map(
14448 
      INIT => X"2"
14449 
    )
14450 
    port map (
14451 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(4),
14452 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_4_rt_481
14453 
    );
14454 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_5_rt : LUT1
14455 
    generic map(
14456 
      INIT => X"2"
14457 
    )
14458 
    port map (
14459 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(5),
14460 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_5_rt_483
14461 
    );
14462 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_6_rt : LUT1
14463 
    generic map(
14464 
      INIT => X"2"
14465 
    )
14466 
    port map (
14467 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(6),
14468 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_6_rt_485
14469 
    );
14470 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_7_rt : LUT1
14471 
    generic map(
14472 
      INIT => X"2"
14473 
    )
14474 
    port map (
14475 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(7),
14476 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_7_rt_487
14477 
    );
14478 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_8_rt : LUT1
14479 
    generic map(
14480 
      INIT => X"2"
14481 
    )
14482 
    port map (
14483 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(8),
14484 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_cy_8_rt_489
14485 
    );
14486 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_1_rt : LUT1
14487 
    generic map(
14488 
      INIT => X"2"
14489 
    )
14490 
    port map (
14491 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(1),
14492 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_1_rt_523
14493 
    );
14494 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_2_rt : LUT1
14495 
    generic map(
14496 
      INIT => X"2"
14497 
    )
14498 
    port map (
14499 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(2),
14500 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_2_rt_525
14501 
    );
14502 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_3_rt : LUT1
14503 
    generic map(
14504 
      INIT => X"2"
14505 
    )
14506 
    port map (
14507 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(3),
14508 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_3_rt_527
14509 
    );
14510 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_4_rt : LUT1
14511 
    generic map(
14512 
      INIT => X"2"
14513 
    )
14514 
    port map (
14515 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(4),
14516 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_4_rt_529
14517 
    );
14518 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_5_rt : LUT1
14519 
    generic map(
14520 
      INIT => X"2"
14521 
    )
14522 
    port map (
14523 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(5),
14524 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_5_rt_531
14525 
    );
14526 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_6_rt : LUT1
14527 
    generic map(
14528 
      INIT => X"2"
14529 
    )
14530 
    port map (
14531 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(6),
14532 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_6_rt_533
14533 
    );
14534 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_7_rt : LUT1
14535 
    generic map(
14536 
      INIT => X"2"
14537 
    )
14538 
    port map (
14539 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(7),
14540 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_7_rt_535
14541 
    );
14542 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_8_rt : LUT1
14543 
    generic map(
14544 
      INIT => X"2"
14545 
    )
14546 
    port map (
14547 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(8),
14548 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_cy_8_rt_537
14549 
    );
14550 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_8_rt : LUT1
14551 
    generic map(
14552 
      INIT => X"2"
14553 
    )
14554 
    port map (
14555 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
14556 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy_8_rt_747
14557 
    );
14558 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_7_rt : LUT1
14559 
    generic map(
14560 
      INIT => X"2"
14561 
    )
14562 
    port map (
14563 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
14564 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy_7_rt_745
14565 
    );
14566 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_6_rt : LUT1
14567 
    generic map(
14568 
      INIT => X"2"
14569 
    )
14570 
    port map (
14571 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
14572 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy_6_rt_743
14573 
    );
14574 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_5_rt : LUT1
14575 
    generic map(
14576 
      INIT => X"2"
14577 
    )
14578 
    port map (
14579 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
14580 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy_5_rt_741
14581 
    );
14582 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_4_rt : LUT1
14583 
    generic map(
14584 
      INIT => X"2"
14585 
    )
14586 
    port map (
14587 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
14588 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy_4_rt_739
14589 
    );
14590 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_3_rt : LUT1
14591 
    generic map(
14592 
      INIT => X"2"
14593 
    )
14594 
    port map (
14595 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
14596 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy_3_rt_737
14597 
    );
14598 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_2_rt : LUT1
14599 
    generic map(
14600 
      INIT => X"2"
14601 
    )
14602 
    port map (
14603 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
14604 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy_2_rt_735
14605 
    );
14606 
  fax4_ins_Madd_fifo_rd_addsub0000_cy_1_rt : LUT1
14607 
    generic map(
14608 
      INIT => X"2"
14609 
    )
14610 
    port map (
14611 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
14612 
      O => fax4_ins_Madd_fifo_rd_addsub0000_cy_1_rt_733
14613 
    );
14614 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_9_rt : LUT1
14615 
    generic map(
14616 
      INIT => X"2"
14617 
    )
14618 
    port map (
14619 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
14620 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_xor_9_rt_1125
14621 
    );
14622 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_8_rt : LUT1
14623 
    generic map(
14624 
      INIT => X"2"
14625 
    )
14626 
    port map (
14627 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(8),
14628 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_xor_8_rt_1175
14629 
    );
14630 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_9_rt : LUT1
14631 
    generic map(
14632 
      INIT => X"2"
14633 
    )
14634 
    port map (
14635 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(9),
14636 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_xor_9_rt_260
14637 
    );
14638 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_9_rt : LUT1
14639 
    generic map(
14640 
      INIT => X"2"
14641 
    )
14642 
    port map (
14643 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(9),
14644 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_xor_9_rt_308
14645 
    );
14646 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_9_rt : LUT1
14647 
    generic map(
14648 
      INIT => X"2"
14649 
    )
14650 
    port map (
14651 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(9),
14652 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_xor_9_rt_501
14653 
    );
14654 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_9_rt : LUT1
14655 
    generic map(
14656 
      INIT => X"2"
14657 
    )
14658 
    port map (
14659 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(9),
14660 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_xor_9_rt_549
14661 
    );
14662 
  fax4_ins_Madd_fifo_rd_addsub0000_xor_9_rt : LUT1
14663 
    generic map(
14664 
      INIT => X"2"
14665 
    )
14666 
    port map (
14667 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
14668 
      O => fax4_ins_Madd_fifo_rd_addsub0000_xor_9_rt_749
14669 
    );
14670 
  huffman_ins_v2_code_black_19_mux00001_f5_rt : LUT1
14671 
    generic map(
14672 
      INIT => X"2"
14673 
    )
14674 
    port map (
14675 
      I0 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
14676 
      O => huffman_ins_v2_code_black_19_mux00001_f5_rt_1594
14677 
    );
14678 
  fax4_ins_vertical_mode_cmp_le00002169_SW0 : LUT4
14679 
    generic map(
14680 
      INIT => X"AAA8"
14681 
    )
14682 
    port map (
14683 
      I0 => N481,
14684 
      I1 => fax4_ins_vertical_mode_addsub0000(2),
14685 
      I2 => fax4_ins_vertical_mode_addsub0000(4),
14686 
      I3 => fax4_ins_vertical_mode_addsub0000(5),
14687 
      O => N105
14688 
    );
14689 
  fax4_ins_vertical_mode_cmp_le00002169 : LUT4
14690 
    generic map(
14691 
      INIT => X"0080"
14692 
    )
14693 
    port map (
14694 
      I0 => fax4_ins_vertical_mode_cmp_le00002114_1362,
14695 
      I1 => fax4_ins_vertical_mode_cmp_le0000245_1366,
14696 
      I2 => fax4_ins_vertical_mode_cmp_le0000281_1367,
14697 
      I3 => N105,
14698 
      O => fax4_ins_vertical_mode_cmp_le00002169_1364
14699 
    );
14700 
  fax4_ins_vertical_mode_cmp_le00002114 : LUT4
14701 
    generic map(
14702 
      INIT => X"F0F1"
14703 
    )
14704 
    port map (
14705 
      I0 => fax4_ins_a1b1(4),
14706 
      I1 => fax4_ins_a1b1(5),
14707 
      I2 => fax4_ins_a1b1(10),
14708 
      I3 => N111,
14709 
      O => fax4_ins_vertical_mode_cmp_le00002114_1362
14710 
    );
14711 
  fax4_ins_a1b1_0_1 : LUT4
14712 
    generic map(
14713 
      INIT => X"D515"
14714 
    )
14715 
    port map (
14716 
      I0 => fax4_ins_b1(0),
14717 
      I1 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
14718 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14719 
      I3 => fax4_ins_a1b1_addsub0000(0),
14720 
      O => fax4_ins_a1b1(0)
14721 
    );
14722 
  fax4_ins_vertical_mode_cmp_le0000245 : LUT4
14723 
    generic map(
14724 
      INIT => X"27FF"
14725 
    )
14726 
    port map (
14727 
      I0 => fax4_ins_EOL,
14728 
      I1 => fax4_ins_a1b1_addsub0001(10),
14729 
      I2 => fax4_ins_a1b1_addsub0000(10),
14730 
      I3 => fax4_ins_vertical_mode_addsub0000(3),
14731 
      O => fax4_ins_vertical_mode_cmp_le0000245_1366
14732 
    );
14733 
  fax4_ins_fifo_rd36 : LUT4
14734 
    generic map(
14735 
      INIT => X"00E0"
14736 
    )
14737 
    port map (
14738 
      I0 => fax4_ins_fifo_rd0_1266,
14739 
      I1 => fax4_ins_fifo_rd3_1268,
14740 
      I2 => fax4_ins_fifo_rd22_1267,
14741 
      I3 => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(9),
14742 
      O => fax4_ins_fifo_rd
14743 
    );
14744 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut_0_Q : LUT3
14745 
    generic map(
14746 
      INIT => X"65"
14747 
    )
14748 
    port map (
14749 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(0),
14750 
      I1 => fax4_ins_fifo1_wr,
14751 
      I2 => fax4_ins_FIFO1_multi_read_ins_N8,
14752 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(0)
14753 
    );
14754 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut_0_Q : LUT3
14755 
    generic map(
14756 
      INIT => X"65"
14757 
    )
14758 
    port map (
14759 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(0),
14760 
      I1 => fax4_ins_fifo2_wr,
14761 
      I2 => fax4_ins_FIFO2_multi_read_ins_N8,
14762 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(0)
14763 
    );
14764 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut_9_Q : LUT3
14765 
    generic map(
14766 
      INIT => X"9A"
14767 
    )
14768 
    port map (
14769 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(9),
14770 
      I1 => fax4_ins_fifo1_wr,
14771 
      I2 => fax4_ins_FIFO1_multi_read_ins_N8,
14772 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(9)
14773 
    );
14774 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut_9_Q : LUT3
14775 
    generic map(
14776 
      INIT => X"9A"
14777 
    )
14778 
    port map (
14779 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(9),
14780 
      I1 => fax4_ins_fifo2_wr,
14781 
      I2 => fax4_ins_FIFO2_multi_read_ins_N8,
14782 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(9)
14783 
    );
14784 
  fax4_ins_vertical_mode_cmp_le0000281_SW0 : LUT4
14785 
    generic map(
14786 
      INIT => X"FFE2"
14787 
    )
14788 
    port map (
14789 
      I0 => fax4_ins_a1b1_addsub0000(7),
14790 
      I1 => fax4_ins_EOL,
14791 
      I2 => fax4_ins_a1b1_addsub0001(7),
14792 
      I3 => N478,
14793 
      O => N113
14794 
    );
14795 
  fax4_ins_Madd_vertical_mode_not0000_1_1 : LUT4
14796 
    generic map(
14797 
      INIT => X"13B3"
14798 
    )
14799 
    port map (
14800 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
14801 
      I1 => fax4_ins_a1b1_addsub0001(1),
14802 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14803 
      I3 => fax4_ins_a1b1_addsub0000(1),
14804 
      O => fax4_ins_Madd_vertical_mode_not0000(1)
14805 
    );
14806 
  fax4_ins_Madd_vertical_mode_not0000_2_1 : LUT4
14807 
    generic map(
14808 
      INIT => X"13B3"
14809 
    )
14810 
    port map (
14811 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
14812 
      I1 => fax4_ins_a1b1_addsub0001(2),
14813 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14814 
      I3 => fax4_ins_a1b1_addsub0000(2),
14815 
      O => fax4_ins_Madd_vertical_mode_not0000(2)
14816 
    );
14817 
  fax4_ins_Madd_vertical_mode_not0000_3_1 : LUT4
14818 
    generic map(
14819 
      INIT => X"13B3"
14820 
    )
14821 
    port map (
14822 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
14823 
      I1 => fax4_ins_a1b1_addsub0001(3),
14824 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14825 
      I3 => fax4_ins_a1b1_addsub0000(3),
14826 
      O => fax4_ins_Madd_vertical_mode_not0000(3)
14827 
    );
14828 
  fax4_ins_Madd_vertical_mode_not0000_4_1 : LUT4
14829 
    generic map(
14830 
      INIT => X"13B3"
14831 
    )
14832 
    port map (
14833 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
14834 
      I1 => fax4_ins_a1b1_addsub0001(4),
14835 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14836 
      I3 => fax4_ins_a1b1_addsub0000(4),
14837 
      O => fax4_ins_Madd_vertical_mode_not0000(4)
14838 
    );
14839 
  fax4_ins_Madd_vertical_mode_not0000_5_1 : LUT4
14840 
    generic map(
14841 
      INIT => X"13B3"
14842 
    )
14843 
    port map (
14844 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
14845 
      I1 => fax4_ins_a1b1_addsub0001(5),
14846 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14847 
      I3 => fax4_ins_a1b1_addsub0000(5),
14848 
      O => fax4_ins_Madd_vertical_mode_not0000(5)
14849 
    );
14850 
  fax4_ins_Madd_vertical_mode_not0000_6_1 : LUT4
14851 
    generic map(
14852 
      INIT => X"13B3"
14853 
    )
14854 
    port map (
14855 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
14856 
      I1 => fax4_ins_a1b1_addsub0001(6),
14857 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14858 
      I3 => fax4_ins_a1b1_addsub0000(6),
14859 
      O => fax4_ins_Madd_vertical_mode_not0000(6)
14860 
    );
14861 
  fax4_ins_Madd_vertical_mode_not0000_7_1 : LUT4
14862 
    generic map(
14863 
      INIT => X"13B3"
14864 
    )
14865 
    port map (
14866 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
14867 
      I1 => fax4_ins_a1b1_addsub0001(7),
14868 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14869 
      I3 => fax4_ins_a1b1_addsub0000(7),
14870 
      O => fax4_ins_Madd_vertical_mode_not0000(7)
14871 
    );
14872 
  fax4_ins_Madd_vertical_mode_not0000_8_1 : LUT4
14873 
    generic map(
14874 
      INIT => X"13B3"
14875 
    )
14876 
    port map (
14877 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
14878 
      I1 => fax4_ins_a1b1_addsub0001(8),
14879 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14880 
      I3 => fax4_ins_a1b1_addsub0000(8),
14881 
      O => fax4_ins_Madd_vertical_mode_not0000(8)
14882 
    );
14883 
  fax4_ins_Madd_vertical_mode_not0000_9_1 : LUT4
14884 
    generic map(
14885 
      INIT => X"13B3"
14886 
    )
14887 
    port map (
14888 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
14889 
      I1 => fax4_ins_a1b1_addsub0001(9),
14890 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14891 
      I3 => fax4_ins_a1b1_addsub0000(9),
14892 
      O => fax4_ins_Madd_vertical_mode_not0000(9)
14893 
    );
14894 
  fax4_ins_a1b1_9_1 : LUT4
14895 
    generic map(
14896 
      INIT => X"EC4C"
14897 
    )
14898 
    port map (
14899 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
14900 
      I1 => fax4_ins_a1b1_addsub0001(9),
14901 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
14902 
      I3 => fax4_ins_a1b1_addsub0000(9),
14903 
      O => fax4_ins_a1b1(9)
14904 
    );
14905 
  fax4_ins_mode_indicator_o_or00001_SW0 : LUT2
14906 
    generic map(
14907 
      INIT => X"2"
14908 
    )
14909 
    port map (
14910 
      I0 => fax4_ins_EOL_prev_230,
14911 
      I1 => fax4_ins_EOL_prev_prev_231,
14912 
      O => N142
14913 
    );
14914 
  fax4_ins_mux_a0_and00011_SW1 : LUT4
14915 
    generic map(
14916 
      INIT => X"A2AE"
14917 
    )
14918 
    port map (
14919 
      I0 => N496,
14920 
      I1 => fax4_ins_pix_changed_1319,
14921 
      I2 => fax4_ins_state_FSM_FFd8_1338,
14922 
      I3 => rsync_i,
14923 
      O => N146
14924 
    );
14925 
  fax4_ins_mux_a0_and00011_SW2 : LUT2
14926 
    generic map(
14927 
      INIT => X"2"
14928 
    )
14929 
    port map (
14930 
      I0 => fax4_ins_pix_changed_1319,
14931 
      I1 => fax4_ins_state_FSM_FFd8_1338,
14932 
      O => N148
14933 
    );
14934 
  fax4_ins_mode_indicator_o_3 : FD_1
14935 
    generic map(
14936 
      INIT => '0'
14937 
    )
14938 
    port map (
14939 
      C => pclk_i,
14940 
      D => fax4_ins_mode_indicator_o_3_rstpot_1295,
14941 
      Q => fax4_ins_mode_indicator_o(3)
14942 
    );
14943 
  fax4_ins_mode_indicator_o_2 : FD_1
14944 
    generic map(
14945 
      INIT => '0'
14946 
    )
14947 
    port map (
14948 
      C => pclk_i,
14949 
      D => fax4_ins_mode_indicator_o_2_rstpot_1291,
14950 
      Q => fax4_ins_mode_indicator_o(2)
14951 
    );
14952 
  fax4_ins_mode_indicator_o_1 : FD_1
14953 
    generic map(
14954 
      INIT => '0'
14955 
    )
14956 
    port map (
14957 
      C => pclk_i,
14958 
      D => fax4_ins_mode_indicator_o_1_rstpot_1289,
14959 
      Q => fax4_ins_mode_indicator_o(1)
14960 
    );
14961 
  fax4_ins_mode_indicator_o_0 : FD_1
14962 
    generic map(
14963 
      INIT => '0'
14964 
    )
14965 
    port map (
14966 
      C => pclk_i,
14967 
      D => fax4_ins_mode_indicator_o_0_rstpot_1287,
14968 
      Q => fax4_ins_mode_indicator_o(0)
14969 
    );
14970 
  fax4_ins_mux_a0_and00011_SW8 : LUT4
14971 
    generic map(
14972 
      INIT => X"FB40"
14973 
    )
14974 
    port map (
14975 
      I0 => fax4_ins_state_FSM_FFd8_1338,
14976 
      I1 => fax4_ins_pix_changed_1319,
14977 
      I2 => fax4_ins_a0_to_white_mux00007_949,
14978 
      I3 => N479,
14979 
      O => N165
14980 
    );
14981 
  fax4_ins_a0_to_white_mux000047 : LUT4
14982 
    generic map(
14983 
      INIT => X"FAEE"
14984 
    )
14985 
    port map (
14986 
      I0 => fax4_ins_mux_a0_0_Q,
14987 
      I1 => N133,
14988 
      I2 => N165,
14989 
      I3 => fax4_ins_vertical_mode_cmp_le0000,
14990 
      O => fax4_ins_a0_to_white_mux0000
14991 
    );
14992 
  fax4_ins_vertical_mode1_SW1 : LUT2
14993 
    generic map(
14994 
      INIT => X"E"
14995 
    )
14996 
    port map (
14997 
      I0 => fax4_ins_pass_mode,
14998 
      I1 => fax4_ins_load_a1_or0001,
14999 
      O => N167
15000 
    );
15001 
  fax4_ins_mode_indicator_o_mux0001_2_35_SW2_SW0 : LUT4
15002 
    generic map(
15003 
      INIT => X"D555"
15004 
    )
15005 
    port map (
15006 
      I0 => fax4_ins_load_a1_or0001,
15007 
      I1 => N469,
15008 
      I2 => fax4_ins_mode_indicator_o_mux0001_2_261_1297,
15009 
      I3 => fax4_ins_mode_indicator_o_mux0001_2_3111_1298,
15010 
      O => N172
15011 
    );
15012 
  fax4_ins_mode_indicator_o_mux0001_3_41_SW2 : LUT4
15013 
    generic map(
15014 
      INIT => X"ECCC"
15015 
    )
15016 
    port map (
15017 
      I0 => fax4_ins_a1b1(0),
15018 
      I1 => N174,
15019 
      I2 => fax4_ins_mode_indicator_o_mux0001_2_341_1299,
15020 
      I3 => N470,
15021 
      O => N161
15022 
    );
15023 
  fax4_ins_mode_indicator_o_2_rstpot : LUT4
15024 
    generic map(
15025 
      INIT => X"2733"
15026 
    )
15027 
    port map (
15028 
      I0 => fax4_ins_state_FSM_FFd8_1338,
15029 
      I1 => N176,
15030 
      I2 => N177,
15031 
      I3 => fax4_ins_vertical_mode_cmp_le0000,
15032 
      O => fax4_ins_mode_indicator_o_2_rstpot_1291
15033 
    );
15034 
  fax4_ins_mode_indicator_o_3_rstpot : LUT4
15035 
    generic map(
15036 
      INIT => X"D8CC"
15037 
    )
15038 
    port map (
15039 
      I0 => fax4_ins_state_FSM_FFd8_1338,
15040 
      I1 => N179,
15041 
      I2 => N180,
15042 
      I3 => fax4_ins_vertical_mode_cmp_le0000,
15043 
      O => fax4_ins_mode_indicator_o_3_rstpot_1295
15044 
    );
15045 
  fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_and0000111_SW0 : LUT3
15046 
    generic map(
15047 
      INIT => X"5D"
15048 
    )
15049 
    port map (
15050 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15051 
      I1 => fax4_ins_FIFO1_multi_read_ins_N7,
15052 
      I2 => fax4_ins_FIFO1_multi_read_ins_used(0),
15053 
      O => N182
15054 
    );
15055 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut_1_Q : LUT4
15056 
    generic map(
15057 
      INIT => X"A9AA"
15058 
    )
15059 
    port map (
15060 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(1),
15061 
      I1 => N182,
15062 
      I2 => fax4_ins_fifo1_wr,
15063 
      I3 => fax4_ins_fifo_rd,
15064 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(1)
15065 
    );
15066 
  fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_and0000111_SW0 : LUT3
15067 
    generic map(
15068 
      INIT => X"31"
15069 
    )
15070 
    port map (
15071 
      I0 => fax4_ins_FIFO2_multi_read_ins_N7,
15072 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15073 
      I2 => fax4_ins_FIFO2_multi_read_ins_used(0),
15074 
      O => N184
15075 
    );
15076 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut_1_Q : LUT4
15077 
    generic map(
15078 
      INIT => X"A6AA"
15079 
    )
15080 
    port map (
15081 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(1),
15082 
      I1 => N184,
15083 
      I2 => fax4_ins_fifo2_wr,
15084 
      I3 => fax4_ins_fifo_rd,
15085 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(1)
15086 
    );
15087 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut_2_Q : LUT4
15088 
    generic map(
15089 
      INIT => X"A9AA"
15090 
    )
15091 
    port map (
15092 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(2),
15093 
      I1 => N182,
15094 
      I2 => fax4_ins_fifo1_wr,
15095 
      I3 => fax4_ins_fifo_rd,
15096 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(2)
15097 
    );
15098 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut_2_Q : LUT4
15099 
    generic map(
15100 
      INIT => X"A6AA"
15101 
    )
15102 
    port map (
15103 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(2),
15104 
      I1 => N184,
15105 
      I2 => fax4_ins_fifo2_wr,
15106 
      I3 => fax4_ins_fifo_rd,
15107 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(2)
15108 
    );
15109 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut_3_Q : LUT4
15110 
    generic map(
15111 
      INIT => X"A9AA"
15112 
    )
15113 
    port map (
15114 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(3),
15115 
      I1 => N182,
15116 
      I2 => fax4_ins_fifo1_wr,
15117 
      I3 => fax4_ins_fifo_rd,
15118 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(3)
15119 
    );
15120 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut_3_Q : LUT4
15121 
    generic map(
15122 
      INIT => X"A6AA"
15123 
    )
15124 
    port map (
15125 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(3),
15126 
      I1 => N184,
15127 
      I2 => fax4_ins_fifo2_wr,
15128 
      I3 => fax4_ins_fifo_rd,
15129 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(3)
15130 
    );
15131 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut_4_Q : LUT4
15132 
    generic map(
15133 
      INIT => X"A9AA"
15134 
    )
15135 
    port map (
15136 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(4),
15137 
      I1 => N182,
15138 
      I2 => fax4_ins_fifo1_wr,
15139 
      I3 => fax4_ins_fifo_rd,
15140 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(4)
15141 
    );
15142 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut_4_Q : LUT4
15143 
    generic map(
15144 
      INIT => X"A6AA"
15145 
    )
15146 
    port map (
15147 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(4),
15148 
      I1 => N184,
15149 
      I2 => fax4_ins_fifo2_wr,
15150 
      I3 => fax4_ins_fifo_rd,
15151 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(4)
15152 
    );
15153 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut_5_Q : LUT4
15154 
    generic map(
15155 
      INIT => X"A9AA"
15156 
    )
15157 
    port map (
15158 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(5),
15159 
      I1 => N182,
15160 
      I2 => fax4_ins_fifo1_wr,
15161 
      I3 => fax4_ins_fifo_rd,
15162 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(5)
15163 
    );
15164 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut_5_Q : LUT4
15165 
    generic map(
15166 
      INIT => X"A6AA"
15167 
    )
15168 
    port map (
15169 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(5),
15170 
      I1 => N184,
15171 
      I2 => fax4_ins_fifo2_wr,
15172 
      I3 => fax4_ins_fifo_rd,
15173 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(5)
15174 
    );
15175 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut_6_Q : LUT4
15176 
    generic map(
15177 
      INIT => X"A9AA"
15178 
    )
15179 
    port map (
15180 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(6),
15181 
      I1 => N182,
15182 
      I2 => fax4_ins_fifo1_wr,
15183 
      I3 => fax4_ins_fifo_rd,
15184 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(6)
15185 
    );
15186 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut_6_Q : LUT4
15187 
    generic map(
15188 
      INIT => X"A6AA"
15189 
    )
15190 
    port map (
15191 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(6),
15192 
      I1 => N184,
15193 
      I2 => fax4_ins_fifo2_wr,
15194 
      I3 => fax4_ins_fifo_rd,
15195 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(6)
15196 
    );
15197 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut_7_Q : LUT4
15198 
    generic map(
15199 
      INIT => X"A9AA"
15200 
    )
15201 
    port map (
15202 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(7),
15203 
      I1 => N182,
15204 
      I2 => fax4_ins_fifo1_wr,
15205 
      I3 => fax4_ins_fifo_rd,
15206 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(7)
15207 
    );
15208 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut_7_Q : LUT4
15209 
    generic map(
15210 
      INIT => X"A6AA"
15211 
    )
15212 
    port map (
15213 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(7),
15214 
      I1 => N184,
15215 
      I2 => fax4_ins_fifo2_wr,
15216 
      I3 => fax4_ins_fifo_rd,
15217 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(7)
15218 
    );
15219 
  fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut_8_Q : LUT4
15220 
    generic map(
15221 
      INIT => X"A9AA"
15222 
    )
15223 
    port map (
15224 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(8),
15225 
      I1 => N182,
15226 
      I2 => fax4_ins_fifo1_wr,
15227 
      I3 => fax4_ins_fifo_rd,
15228 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_used_lut(8)
15229 
    );
15230 
  fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut_8_Q : LUT4
15231 
    generic map(
15232 
      INIT => X"A6AA"
15233 
    )
15234 
    port map (
15235 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(8),
15236 
      I1 => N184,
15237 
      I2 => fax4_ins_fifo2_wr,
15238 
      I3 => fax4_ins_fifo_rd,
15239 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_used_lut(8)
15240 
    );
15241 
  fax4_ins_FIFO1_multi_read_ins_read_as_last_operation : FD
15242 
    generic map(
15243 
      INIT => '0'
15244 
    )
15245 
    port map (
15246 
      C => fax4_ins_pclk_not,
15247 
      D => fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_rstpot_427,
15248 
      Q => fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_426
15249 
    );
15250 
  fax4_ins_FIFO2_multi_read_ins_read_as_last_operation : FD
15251 
    generic map(
15252 
      INIT => '0'
15253 
    )
15254 
    port map (
15255 
      C => fax4_ins_pclk_not,
15256 
      D => fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_rstpot_669,
15257 
      Q => fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_668
15258 
    );
15259 
  fax4_ins_a1b1_5_1 : LUT4
15260 
    generic map(
15261 
      INIT => X"EC4C"
15262 
    )
15263 
    port map (
15264 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
15265 
      I1 => fax4_ins_a1b1_addsub0001(5),
15266 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
15267 
      I3 => fax4_ins_a1b1_addsub0000(5),
15268 
      O => fax4_ins_a1b1(5)
15269 
    );
15270 
  fax4_ins_a1b1_4_1 : LUT4
15271 
    generic map(
15272 
      INIT => X"EC4C"
15273 
    )
15274 
    port map (
15275 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
15276 
      I1 => fax4_ins_a1b1_addsub0001(4),
15277 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
15278 
      I3 => fax4_ins_a1b1_addsub0000(4),
15279 
      O => fax4_ins_a1b1(4)
15280 
    );
15281 
  fax4_ins_a1b1_3_1 : LUT4
15282 
    generic map(
15283 
      INIT => X"EC4C"
15284 
    )
15285 
    port map (
15286 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
15287 
      I1 => fax4_ins_a1b1_addsub0001(3),
15288 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
15289 
      I3 => fax4_ins_a1b1_addsub0000(3),
15290 
      O => fax4_ins_a1b1(3)
15291 
    );
15292 
  fax4_ins_mode_indicator_o_mux0001_2_28_SW0 : LUT3
15293 
    generic map(
15294 
      INIT => X"FE"
15295 
    )
15296 
    port map (
15297 
      I0 => fax4_ins_a1b1(2),
15298 
      I1 => fax4_ins_a1b1(3),
15299 
      I2 => N482,
15300 
      O => N218
15301 
    );
15302 
  fax4_ins_mode_indicator_o_1_rstpot : LUT4
15303 
    generic map(
15304 
      INIT => X"2733"
15305 
    )
15306 
    port map (
15307 
      I0 => fax4_ins_state_FSM_FFd8_1338,
15308 
      I1 => N220,
15309 
      I2 => N221,
15310 
      I3 => fax4_ins_vertical_mode_cmp_le0000,
15311 
      O => fax4_ins_mode_indicator_o_1_rstpot_1289
15312 
    );
15313 
  fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_rstpot_SW0 : LUT3
15314 
    generic map(
15315 
      INIT => X"32"
15316 
    )
15317 
    port map (
15318 
      I0 => N487,
15319 
      I1 => fax4_ins_fifo1_wr,
15320 
      I2 => fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_426,
15321 
      O => N223
15322 
    );
15323 
  fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_rstpot : LUT4
15324 
    generic map(
15325 
      INIT => X"BBB8"
15326 
    )
15327 
    port map (
15328 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_426,
15329 
      I1 => frame_finished_wire,
15330 
      I2 => N223,
15331 
      I3 => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
15332 
      O => fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_rstpot_427
15333 
    );
15334 
  fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_rstpot_SW0 : LUT3
15335 
    generic map(
15336 
      INIT => X"32"
15337 
    )
15338 
    port map (
15339 
      I0 => N488,
15340 
      I1 => fax4_ins_fifo2_wr,
15341 
      I2 => fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_668,
15342 
      O => N225
15343 
    );
15344 
  fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_rstpot : LUT4
15345 
    generic map(
15346 
      INIT => X"BBB8"
15347 
    )
15348 
    port map (
15349 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_668,
15350 
      I1 => frame_finished_wire,
15351 
      I2 => N225,
15352 
      I3 => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
15353 
      O => fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_rstpot_669
15354 
    );
15355 
  fax4_ins_fifo_rd36_SW2 : LUT4
15356 
    generic map(
15357 
      INIT => X"AF8C"
15358 
    )
15359 
    port map (
15360 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(0),
15361 
      I1 => fax4_ins_fifo_rd3_1268,
15362 
      I2 => fax4_ins_FIFO1_multi_read_ins_N7,
15363 
      I3 => N467,
15364 
      O => N231
15365 
    );
15366 
  fax4_ins_fifo_rd36_SW3 : LUT4
15367 
    generic map(
15368 
      INIT => X"222F"
15369 
    )
15370 
    port map (
15371 
      I0 => fax4_ins_FIFO2_multi_read_ins_N7,
15372 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(0),
15373 
      I2 => N468,
15374 
      I3 => fax4_ins_fifo_rd0_1266,
15375 
      O => N233
15376 
    );
15377 
  fax4_ins_mode_indicator_o_mux0001_2_35_SW2_SW1 : LUT3
15378 
    generic map(
15379 
      INIT => X"80"
15380 
    )
15381 
    port map (
15382 
      I0 => fax4_ins_a1b1(0),
15383 
      I1 => fax4_ins_a1b1(1),
15384 
      I2 => N484,
15385 
      O => N235
15386 
    );
15387 
  fax4_ins_mode_indicator_o_0_rstpot : LUT4
15388 
    generic map(
15389 
      INIT => X"FE02"
15390 
    )
15391 
    port map (
15392 
      I0 => fax4_ins_mode_indicator_o(0),
15393 
      I1 => N167,
15394 
      I2 => N237,
15395 
      I3 => fax4_ins_mode_indicator_o_mux0001(3),
15396 
      O => fax4_ins_mode_indicator_o_0_rstpot_1287
15397 
    );
15398 
  fax4_ins_mode_indicator_o_not00011_SW0 : LUT4
15399 
    generic map(
15400 
      INIT => X"EC4C"
15401 
    )
15402 
    port map (
15403 
      I0 => fax4_ins_vertical_mode_cmp_le00002169_1364,
15404 
      I1 => N239,
15405 
      I2 => fax4_ins_vertical_mode_cmp_le0000213_1363,
15406 
      I3 => N240,
15407 
      O => N237
15408 
    );
15409 
  fax4_ins_vertical_mode_cmp_le00002199_SW0 : LUT4
15410 
    generic map(
15411 
      INIT => X"AA2A"
15412 
    )
15413 
    port map (
15414 
      I0 => N142,
15415 
      I1 => fax4_ins_a1b1(10),
15416 
      I2 => fax4_ins_vertical_mode_addsub0000(10),
15417 
      I3 => fax4_ins_state_FSM_FFd8_1338,
15418 
      O => N239
15419 
    );
15420 
  fax4_ins_vertical_mode_cmp_le00002199_SW2 : LUT3
15421 
    generic map(
15422 
      INIT => X"FD"
15423 
    )
15424 
    port map (
15425 
      I0 => fax4_ins_pix_changed_1319,
15426 
      I1 => fax4_ins_state_FSM_FFd8_1338,
15427 
      I2 => fax4_ins_mux_a0_0_Q,
15428 
      O => N242
15429 
    );
15430 
  fax4_ins_mux_a0_1_1 : LUT4
15431 
    generic map(
15432 
      INIT => X"4474"
15433 
    )
15434 
    port map (
15435 
      I0 => N242,
15436 
      I1 => fax4_ins_vertical_mode_cmp_le000020_1361,
15437 
      I2 => fax4_ins_vertical_mode_cmp_le00002169_1364,
15438 
      I3 => N243,
15439 
      O => fax4_ins_mux_a0_1_Q
15440 
    );
15441 
  fax4_ins_vertical_mode_cmp_le00002199_SW4 : LUT4
15442 
    generic map(
15443 
      INIT => X"F2F0"
15444 
    )
15445 
    port map (
15446 
      I0 => fax4_ins_pix_changed_1319,
15447 
      I1 => fax4_ins_state_FSM_FFd8_1338,
15448 
      I2 => N144,
15449 
      I3 => fax4_ins_vertical_mode_cmp_le000020_1361,
15450 
      O => N245
15451 
    );
15452 
  fax4_ins_vertical_mode_cmp_le00002199_SW6 : LUT4
15453 
    generic map(
15454 
      INIT => X"FCFA"
15455 
    )
15456 
    port map (
15457 
      I0 => N115,
15458 
      I1 => N146,
15459 
      I2 => fax4_ins_mux_a0_0_Q,
15460 
      I3 => fax4_ins_vertical_mode_cmp_le000020_1361,
15461 
      O => N248
15462 
    );
15463 
  fax4_ins_vertical_mode_cmp_le00002199_SW8 : LUT4
15464 
    generic map(
15465 
      INIT => X"FEFC"
15466 
    )
15467 
    port map (
15468 
      I0 => N148,
15469 
      I1 => fax4_ins_mux_a0_0_Q,
15470 
      I2 => N117,
15471 
      I3 => fax4_ins_vertical_mode_cmp_le000020_1361,
15472 
      O => N251
15473 
    );
15474 
  fax4_ins_vertical_mode_cmp_le00002199_SW10 : LUT4
15475 
    generic map(
15476 
      INIT => X"FEFC"
15477 
    )
15478 
    port map (
15479 
      I0 => N148,
15480 
      I1 => fax4_ins_mux_a0_0_Q,
15481 
      I2 => N119,
15482 
      I3 => fax4_ins_vertical_mode_cmp_le000020_1361,
15483 
      O => N254
15484 
    );
15485 
  fax4_ins_vertical_mode_cmp_le00002199_SW12 : LUT4
15486 
    generic map(
15487 
      INIT => X"FEFC"
15488 
    )
15489 
    port map (
15490 
      I0 => N148,
15491 
      I1 => fax4_ins_mux_a0_0_Q,
15492 
      I2 => N121,
15493 
      I3 => fax4_ins_vertical_mode_cmp_le000020_1361,
15494 
      O => N257
15495 
    );
15496 
  fax4_ins_vertical_mode_cmp_le00002199_SW14 : LUT4
15497 
    generic map(
15498 
      INIT => X"FEFC"
15499 
    )
15500 
    port map (
15501 
      I0 => N148,
15502 
      I1 => fax4_ins_mux_a0_0_Q,
15503 
      I2 => N123,
15504 
      I3 => fax4_ins_vertical_mode_cmp_le000020_1361,
15505 
      O => N260
15506 
    );
15507 
  fax4_ins_vertical_mode_cmp_le00002199_SW16 : LUT4
15508 
    generic map(
15509 
      INIT => X"FEFC"
15510 
    )
15511 
    port map (
15512 
      I0 => N148,
15513 
      I1 => fax4_ins_mux_a0_0_Q,
15514 
      I2 => N125,
15515 
      I3 => fax4_ins_vertical_mode_cmp_le000020_1361,
15516 
      O => N263
15517 
    );
15518 
  fax4_ins_vertical_mode_cmp_le00002199_SW18 : LUT4
15519 
    generic map(
15520 
      INIT => X"FEFC"
15521 
    )
15522 
    port map (
15523 
      I0 => N148,
15524 
      I1 => fax4_ins_mux_a0_0_Q,
15525 
      I2 => N127,
15526 
      I3 => fax4_ins_vertical_mode_cmp_le000020_1361,
15527 
      O => N266
15528 
    );
15529 
  fax4_ins_mux_b1_1_and0000 : LUT4
15530 
    generic map(
15531 
      INIT => X"0060"
15532 
    )
15533 
    port map (
15534 
      I0 => fax4_ins_fifo_out_prev1_to_white_1239,
15535 
      I1 => fax4_ins_a0_to_white_946,
15536 
      I2 => N73,
15537 
      I3 => fax4_ins_Mcompar_mux_b1_1_cmp_gt0000_cy(9),
15538 
      O => fax4_ins_mux_b1(1)
15539 
    );
15540 
  fax4_ins_b2_mux0004_9_42 : LUT4
15541 
    generic map(
15542 
      INIT => X"FFEA"
15543 
    )
15544 
    port map (
15545 
      I0 => fax4_ins_b2_mux0004_9_10_1092,
15546 
      I1 => fax4_ins_fifo_out2_x(9),
15547 
      I2 => fax4_ins_N13,
15548 
      I3 => fax4_ins_b2_mux0004_9_36_1093,
15549 
      O => fax4_ins_b2_mux0004(9)
15550 
    );
15551 
  fax4_ins_b2_mux0004_8_39 : LUT4
15552 
    generic map(
15553 
      INIT => X"FFEA"
15554 
    )
15555 
    port map (
15556 
      I0 => fax4_ins_b2_mux0004_8_10_1089,
15557 
      I1 => fax4_ins_fifo_out2_x(8),
15558 
      I2 => fax4_ins_N13,
15559 
      I3 => fax4_ins_b2_mux0004_8_33_1090,
15560 
      O => fax4_ins_b2_mux0004(8)
15561 
    );
15562 
  fax4_ins_b2_mux0004_7_42 : LUT4
15563 
    generic map(
15564 
      INIT => X"FFEA"
15565 
    )
15566 
    port map (
15567 
      I0 => fax4_ins_b2_mux0004_7_10_1086,
15568 
      I1 => fax4_ins_fifo_out2_x(7),
15569 
      I2 => fax4_ins_N13,
15570 
      I3 => fax4_ins_b2_mux0004_7_36_1087,
15571 
      O => fax4_ins_b2_mux0004(7)
15572 
    );
15573 
  fax4_ins_b2_mux0004_6_42 : LUT4
15574 
    generic map(
15575 
      INIT => X"FFEA"
15576 
    )
15577 
    port map (
15578 
      I0 => fax4_ins_b2_mux0004_6_10_1083,
15579 
      I1 => fax4_ins_fifo_out2_x(6),
15580 
      I2 => fax4_ins_N13,
15581 
      I3 => fax4_ins_b2_mux0004_6_36_1084,
15582 
      O => fax4_ins_b2_mux0004(6)
15583 
    );
15584 
  fax4_ins_b2_mux0004_5_42 : LUT4
15585 
    generic map(
15586 
      INIT => X"FFEA"
15587 
    )
15588 
    port map (
15589 
      I0 => fax4_ins_b2_mux0004_5_10_1080,
15590 
      I1 => fax4_ins_fifo_out2_x(5),
15591 
      I2 => fax4_ins_N13,
15592 
      I3 => fax4_ins_b2_mux0004_5_36_1081,
15593 
      O => fax4_ins_b2_mux0004(5)
15594 
    );
15595 
  fax4_ins_b2_mux0004_4_42 : LUT4
15596 
    generic map(
15597 
      INIT => X"FFEA"
15598 
    )
15599 
    port map (
15600 
      I0 => fax4_ins_b2_mux0004_4_10_1077,
15601 
      I1 => fax4_ins_fifo_out2_x(4),
15602 
      I2 => fax4_ins_N13,
15603 
      I3 => fax4_ins_b2_mux0004_4_36_1078,
15604 
      O => fax4_ins_b2_mux0004(4)
15605 
    );
15606 
  fax4_ins_b2_mux0004_3_39 : LUT4
15607 
    generic map(
15608 
      INIT => X"FFEA"
15609 
    )
15610 
    port map (
15611 
      I0 => fax4_ins_b2_mux0004_3_10_1074,
15612 
      I1 => fax4_ins_fifo_out2_x(3),
15613 
      I2 => fax4_ins_N13,
15614 
      I3 => fax4_ins_b2_mux0004_3_33_1075,
15615 
      O => fax4_ins_b2_mux0004(3)
15616 
    );
15617 
  fax4_ins_b2_mux0004_2_39 : LUT4
15618 
    generic map(
15619 
      INIT => X"FFEA"
15620 
    )
15621 
    port map (
15622 
      I0 => fax4_ins_b2_mux0004_2_10_1071,
15623 
      I1 => fax4_ins_fifo_out2_x(2),
15624 
      I2 => fax4_ins_N13,
15625 
      I3 => fax4_ins_b2_mux0004_2_33_1072,
15626 
      O => fax4_ins_b2_mux0004(2)
15627 
    );
15628 
  fax4_ins_b2_mux0004_1_39 : LUT4
15629 
    generic map(
15630 
      INIT => X"FFEA"
15631 
    )
15632 
    port map (
15633 
      I0 => fax4_ins_b2_mux0004_1_10_1068,
15634 
      I1 => fax4_ins_fifo_out2_x(1),
15635 
      I2 => fax4_ins_N13,
15636 
      I3 => fax4_ins_b2_mux0004_1_33_1069,
15637 
      O => fax4_ins_b2_mux0004(1)
15638 
    );
15639 
  fax4_ins_b2_mux0004_0_42 : LUT4
15640 
    generic map(
15641 
      INIT => X"FFEA"
15642 
    )
15643 
    port map (
15644 
      I0 => fax4_ins_b2_mux0004_0_10_1065,
15645 
      I1 => fax4_ins_fifo_out2_x(0),
15646 
      I2 => fax4_ins_N13,
15647 
      I3 => fax4_ins_b2_mux0004_0_36_1066,
15648 
      O => fax4_ins_b2_mux0004(0)
15649 
    );
15650 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut_0_Q : LUT4
15651 
    generic map(
15652 
      INIT => X"A695"
15653 
    )
15654 
    port map (
15655 
      I0 => fax4_ins_a0(0),
15656 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15657 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(0),
15658 
      I3 => fax4_ins_FIFO2_multi_read_ins_data2_o(0),
15659 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(0)
15660 
    );
15661 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut_1_Q : LUT4
15662 
    generic map(
15663 
      INIT => X"A695"
15664 
    )
15665 
    port map (
15666 
      I0 => fax4_ins_a0(1),
15667 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15668 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(1),
15669 
      I3 => fax4_ins_FIFO2_multi_read_ins_data2_o(1),
15670 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(1)
15671 
    );
15672 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut_1_Q : LUT4
15673 
    generic map(
15674 
      INIT => X"E41B"
15675 
    )
15676 
    port map (
15677 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15678 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(1),
15679 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(1),
15680 
      I3 => fax4_ins_a0(1),
15681 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(1)
15682 
    );
15683 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut_2_Q : LUT4
15684 
    generic map(
15685 
      INIT => X"A695"
15686 
    )
15687 
    port map (
15688 
      I0 => fax4_ins_a0(2),
15689 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15690 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(2),
15691 
      I3 => fax4_ins_FIFO2_multi_read_ins_data2_o(2),
15692 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(2)
15693 
    );
15694 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut_2_Q : LUT4
15695 
    generic map(
15696 
      INIT => X"E41B"
15697 
    )
15698 
    port map (
15699 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15700 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(2),
15701 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(2),
15702 
      I3 => fax4_ins_a0(2),
15703 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(2)
15704 
    );
15705 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut_3_Q : LUT4
15706 
    generic map(
15707 
      INIT => X"A695"
15708 
    )
15709 
    port map (
15710 
      I0 => fax4_ins_a0(3),
15711 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15712 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(3),
15713 
      I3 => fax4_ins_FIFO2_multi_read_ins_data2_o(3),
15714 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(3)
15715 
    );
15716 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut_3_Q : LUT4
15717 
    generic map(
15718 
      INIT => X"E41B"
15719 
    )
15720 
    port map (
15721 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15722 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(3),
15723 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(3),
15724 
      I3 => fax4_ins_a0(3),
15725 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(3)
15726 
    );
15727 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut_4_Q : LUT4
15728 
    generic map(
15729 
      INIT => X"A695"
15730 
    )
15731 
    port map (
15732 
      I0 => fax4_ins_a0(4),
15733 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15734 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(4),
15735 
      I3 => fax4_ins_FIFO2_multi_read_ins_data2_o(4),
15736 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(4)
15737 
    );
15738 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut_4_Q : LUT4
15739 
    generic map(
15740 
      INIT => X"E41B"
15741 
    )
15742 
    port map (
15743 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15744 
      I1 => fax4_ins_FIFO2_multi_read_ins_data1_o(4),
15745 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(4),
15746 
      I3 => fax4_ins_a0(4),
15747 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(4)
15748 
    );
15749 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut_5_Q : LUT4
15750 
    generic map(
15751 
      INIT => X"A695"
15752 
    )
15753 
    port map (
15754 
      I0 => fax4_ins_a0(5),
15755 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15756 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(5),
15757 
      I3 => fax4_ins_FIFO2_multi_read_ins_data2_o(5),
15758 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(5)
15759 
    );
15760 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut_5_Q : LUT4
15761 
    generic map(
15762 
      INIT => X"A695"
15763 
    )
15764 
    port map (
15765 
      I0 => fax4_ins_a0(5),
15766 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15767 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(5),
15768 
      I3 => fax4_ins_FIFO2_multi_read_ins_data1_o(5),
15769 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(5)
15770 
    );
15771 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut_6_Q : LUT4
15772 
    generic map(
15773 
      INIT => X"A695"
15774 
    )
15775 
    port map (
15776 
      I0 => fax4_ins_a0(6),
15777 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15778 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(6),
15779 
      I3 => fax4_ins_FIFO2_multi_read_ins_data2_o(6),
15780 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(6)
15781 
    );
15782 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut_6_Q : LUT4
15783 
    generic map(
15784 
      INIT => X"A695"
15785 
    )
15786 
    port map (
15787 
      I0 => fax4_ins_a0(6),
15788 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15789 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(6),
15790 
      I3 => fax4_ins_FIFO2_multi_read_ins_data1_o(6),
15791 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(6)
15792 
    );
15793 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut_7_Q : LUT4
15794 
    generic map(
15795 
      INIT => X"A695"
15796 
    )
15797 
    port map (
15798 
      I0 => fax4_ins_a0(7),
15799 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15800 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(7),
15801 
      I3 => fax4_ins_FIFO2_multi_read_ins_data2_o(7),
15802 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(7)
15803 
    );
15804 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut_7_Q : LUT4
15805 
    generic map(
15806 
      INIT => X"A695"
15807 
    )
15808 
    port map (
15809 
      I0 => fax4_ins_a0(7),
15810 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15811 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(7),
15812 
      I3 => fax4_ins_FIFO2_multi_read_ins_data1_o(7),
15813 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(7)
15814 
    );
15815 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut_8_Q : LUT4
15816 
    generic map(
15817 
      INIT => X"A695"
15818 
    )
15819 
    port map (
15820 
      I0 => fax4_ins_a0(8),
15821 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15822 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(8),
15823 
      I3 => fax4_ins_FIFO2_multi_read_ins_data2_o(8),
15824 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(8)
15825 
    );
15826 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut_8_Q : LUT4
15827 
    generic map(
15828 
      INIT => X"A695"
15829 
    )
15830 
    port map (
15831 
      I0 => fax4_ins_a0(8),
15832 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15833 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(8),
15834 
      I3 => fax4_ins_FIFO2_multi_read_ins_data1_o(8),
15835 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(8)
15836 
    );
15837 
  fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut_9_Q : LUT4
15838 
    generic map(
15839 
      INIT => X"A695"
15840 
    )
15841 
    port map (
15842 
      I0 => fax4_ins_a0(9),
15843 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15844 
      I2 => fax4_ins_FIFO1_multi_read_ins_data2_o(9),
15845 
      I3 => fax4_ins_FIFO2_multi_read_ins_data2_o(9),
15846 
      O => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_lut(9)
15847 
    );
15848 
  fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut_9_Q : LUT4
15849 
    generic map(
15850 
      INIT => X"A695"
15851 
    )
15852 
    port map (
15853 
      I0 => fax4_ins_a0(9),
15854 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15855 
      I2 => fax4_ins_FIFO1_multi_read_ins_data1_o(9),
15856 
      I3 => fax4_ins_FIFO2_multi_read_ins_data1_o(9),
15857 
      O => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_lut(9)
15858 
    );
15859 
  fax4_ins_vertical_mode_cmp_le0000226_SW0 : LUT4
15860 
    generic map(
15861 
      INIT => X"DDD5"
15862 
    )
15863 
    port map (
15864 
      I0 => fax4_ins_pix_changed_1319,
15865 
      I1 => fax4_ins_a1b1(10),
15866 
      I2 => fax4_ins_vertical_mode_addsub0000(6),
15867 
      I3 => fax4_ins_vertical_mode_addsub0000(7),
15868 
      O => N269
15869 
    );
15870 
  fax4_ins_Madd_vertical_mode_not0000_10_1 : LUT4
15871 
    generic map(
15872 
      INIT => X"13B3"
15873 
    )
15874 
    port map (
15875 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
15876 
      I1 => fax4_ins_a1b1_addsub0001(10),
15877 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
15878 
      I3 => fax4_ins_a1b1_addsub0000(10),
15879 
      O => fax4_ins_Madd_vertical_mode_not0000(10)
15880 
    );
15881 
  fax4_ins_vertical_mode_cmp_le00002199_SW9 : LUT4
15882 
    generic map(
15883 
      INIT => X"FEFC"
15884 
    )
15885 
    port map (
15886 
      I0 => N148,
15887 
      I1 => fax4_ins_mux_a0_0_Q,
15888 
      I2 => N472,
15889 
      I3 => N271,
15890 
      O => N252
15891 
    );
15892 
  fax4_ins_vertical_mode_cmp_le00002199_SW11 : LUT4
15893 
    generic map(
15894 
      INIT => X"FEFC"
15895 
    )
15896 
    port map (
15897 
      I0 => N148,
15898 
      I1 => fax4_ins_mux_a0_0_Q,
15899 
      I2 => N473,
15900 
      I3 => N271,
15901 
      O => N255
15902 
    );
15903 
  fax4_ins_vertical_mode_cmp_le00002199_SW13 : LUT4
15904 
    generic map(
15905 
      INIT => X"FEFC"
15906 
    )
15907 
    port map (
15908 
      I0 => N148,
15909 
      I1 => fax4_ins_mux_a0_0_Q,
15910 
      I2 => N474,
15911 
      I3 => N271,
15912 
      O => N258
15913 
    );
15914 
  fax4_ins_vertical_mode_cmp_le00002199_SW15 : LUT4
15915 
    generic map(
15916 
      INIT => X"FEFC"
15917 
    )
15918 
    port map (
15919 
      I0 => N148,
15920 
      I1 => fax4_ins_mux_a0_0_Q,
15921 
      I2 => N475,
15922 
      I3 => N271,
15923 
      O => N261
15924 
    );
15925 
  fax4_ins_vertical_mode_cmp_le00002199_SW17 : LUT4
15926 
    generic map(
15927 
      INIT => X"FEFC"
15928 
    )
15929 
    port map (
15930 
      I0 => N148,
15931 
      I1 => fax4_ins_mux_a0_0_Q,
15932 
      I2 => N476,
15933 
      I3 => N271,
15934 
      O => N264
15935 
    );
15936 
  fax4_ins_vertical_mode_cmp_le00002199_SW19 : LUT4
15937 
    generic map(
15938 
      INIT => X"FEFC"
15939 
    )
15940 
    port map (
15941 
      I0 => N148,
15942 
      I1 => fax4_ins_mux_a0_0_Q,
15943 
      I2 => N477,
15944 
      I3 => N271,
15945 
      O => N267
15946 
    );
15947 
  fax4_ins_vertical_mode_cmp_le00002199_SW5 : LUT4
15948 
    generic map(
15949 
      INIT => X"AEAA"
15950 
    )
15951 
    port map (
15952 
      I0 => N144,
15953 
      I1 => fax4_ins_pix_changed_1319,
15954 
      I2 => fax4_ins_state_FSM_FFd8_1338,
15955 
      I3 => N494,
15956 
      O => N246
15957 
    );
15958 
  fax4_ins_b2_to_white_mux000423_SW0 : LUT3
15959 
    generic map(
15960 
      INIT => X"E4"
15961 
    )
15962 
    port map (
15963 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15964 
      I1 => fax4_ins_FIFO2_multi_read_ins_to_white2_o_684,
15965 
      I2 => fax4_ins_FIFO1_multi_read_ins_to_white2_o_442,
15966 
      O => N285
15967 
    );
15968 
  fax4_ins_b2_to_white_mux000458 : LUT4
15969 
    generic map(
15970 
      INIT => X"FFEA"
15971 
    )
15972 
    port map (
15973 
      I0 => fax4_ins_b2_to_white_mux000410_1098,
15974 
      I1 => N466,
15975 
      I2 => N285,
15976 
      I3 => fax4_ins_b2_to_white_mux000452_1099,
15977 
      O => fax4_ins_b2_to_white_mux0004
15978 
    );
15979 
  fax4_ins_FIFO2_multi_read_ins_used_not0003_inv2 : LUT4
15980 
    generic map(
15981 
      INIT => X"4500"
15982 
    )
15983 
    port map (
15984 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
15985 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(0),
15986 
      I2 => fax4_ins_FIFO2_multi_read_ins_N7,
15987 
      I3 => fax4_ins_fifo_rd,
15988 
      O => fax4_ins_FIFO2_multi_read_ins_used_not0003_inv
15989 
    );
15990 
  fax4_ins_vertical_mode_cmp_le00002199_SW7 : MUXF5
15991 
    port map (
15992 
      I0 => N287,
15993 
      I1 => N288,
15994 
      S => fax4_ins_vertical_mode_cmp_le000020_1361,
15995 
      O => N249
15996 
    );
15997 
  fax4_ins_vertical_mode_cmp_le00002199_SW7_F : LUT4
15998 
    generic map(
15999 
      INIT => X"FCFA"
16000 
    )
16001 
    port map (
16002 
      I0 => N115,
16003 
      I1 => N146,
16004 
      I2 => fax4_ins_mux_a0_0_Q,
16005 
      I3 => fax4_ins_vertical_mode_cmp_le0000226_1365,
16006 
      O => N287
16007 
    );
16008 
  fax4_ins_vertical_mode_cmp_le00002199_SW7_G : LUT2
16009 
    generic map(
16010 
      INIT => X"E"
16011 
    )
16012 
    port map (
16013 
      I0 => fax4_ins_mux_a0_0_Q,
16014 
      I1 => N146,
16015 
      O => N288
16016 
    );
16017 
  fax4_ins_output_valid_o_mux0003361 : LUT4
16018 
    generic map(
16019 
      INIT => X"AAA2"
16020 
    )
16021 
    port map (
16022 
      I0 => fax4_ins_load_a1_or0000,
16023 
      I1 => fax4_ins_state_FSM_N7,
16024 
      I2 => fax4_ins_pass_mode,
16025 
      I3 => fax4_ins_pix_changed_1319,
16026 
      O => fax4_ins_output_valid_o_mux000336
16027 
    );
16028 
  huffman_ins_v2_hor_code_9_mux00031471 : LUT4
16029 
    generic map(
16030 
      INIT => X"F3F2"
16031 
    )
16032 
    port map (
16033 
      I0 => huffman_ins_v2_hor_code_9_mux0003114_2041,
16034 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
16035 
      I2 => huffman_ins_v2_hor_code_9_mux000366,
16036 
      I3 => huffman_ins_v2_hor_code_9_mux000398_2049,
16037 
      O => huffman_ins_v2_hor_code_9_mux0003147
16038 
    );
16039 
  fax4_ins_state_FSM_FFd8_In251 : LUT4
16040 
    generic map(
16041 
      INIT => X"C040"
16042 
    )
16043 
    port map (
16044 
      I0 => fax4_ins_vertical_mode_cmp_le0000,
16045 
      I1 => fax4_ins_load_a1_or0001,
16046 
      I2 => fax4_ins_load_a1_or0000,
16047 
      I3 => fax4_ins_state_FSM_FFd8_1338,
16048 
      O => fax4_ins_state_FSM_FFd8_In25
16049 
    );
16050 
  huffman_ins_v2_hor_code_1_mux000354 : LUT4
16051 
    generic map(
16052 
      INIT => X"AEAA"
16053 
    )
16054 
    port map (
16055 
      I0 => huffman_ins_v2_hor_code_1_mux000347_1932,
16056 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
16057 
      I2 => huffman_ins_v2_N59,
16058 
      I3 => huffman_ins_v2_N100,
16059 
      O => huffman_ins_v2_hor_code_1_mux000354_1933
16060 
    );
16061 
  huffman_ins_v2_hor_code_15_mux000326 : LUT4
16062 
    generic map(
16063 
      INIT => X"EAAA"
16064 
    )
16065 
    port map (
16066 
      I0 => huffman_ins_v2_hor_code_15_mux000321,
16067 
      I1 => huffman_ins_v2_N65,
16068 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
16069 
      I3 => huffman_ins_v2_hor_code(15),
16070 
      O => huffman_ins_v2_hor_code_15_mux000326_1887
16071 
    );
16072 
  huffman_ins_v2_hor_code_5_mux000327 : LUT4
16073 
    generic map(
16074 
      INIT => X"F888"
16075 
    )
16076 
    port map (
16077 
      I0 => huffman_ins_v2_hor_code_13_cmp_eq0000,
16078 
      I1 => huffman_ins_v2_N100,
16079 
      I2 => huffman_ins_v2_hor_code(5),
16080 
      I3 => huffman_ins_v2_hor_code_5_mux000315_2007,
16081 
      O => huffman_ins_v2_hor_code_5_mux000327_2008
16082 
    );
16083 
  huffman_ins_v2_hor_code_2_mux000385 : LUT4
16084 
    generic map(
16085 
      INIT => X"FFEA"
16086 
    )
16087 
    port map (
16088 
      I0 => huffman_ins_v2_hor_code_2_mux000335_1987,
16089 
      I1 => huffman_ins_v2_N100,
16090 
      I2 => huffman_ins_v2_N232,
16091 
      I3 => huffman_ins_v2_hor_code_2_mux000379_1988,
16092 
      O => huffman_ins_v2_hor_code_2_mux000385_1989
16093 
    );
16094 
  fax4_ins_state_FSM_FFd5_In14 : LUT4
16095 
    generic map(
16096 
      INIT => X"0C08"
16097 
    )
16098 
    port map (
16099 
      I0 => fax4_ins_state_FSM_FFd5_1333,
16100 
      I1 => fax4_ins_state_FSM_N7,
16101 
      I2 => fax4_ins_pix_changed_1319,
16102 
      I3 => fax4_ins_state_FSM_FFd5_In5_1335,
16103 
      O => fax4_ins_state_FSM_FFd5_In
16104 
    );
16105 
  huffman_ins_v2_hor_code_22_mux0003135 : LUT4
16106 
    generic map(
16107 
      INIT => X"A820"
16108 
    )
16109 
    port map (
16110 
      I0 => huffman_ins_v2_hor_code(22),
16111 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
16112 
      I2 => huffman_ins_v2_N3,
16113 
      I3 => huffman_ins_v2_hor_code_22_mux0003112_1959,
16114 
      O => huffman_ins_v2_hor_code_22_mux0003135_1960
16115 
    );
16116 
  fax4_ins_state_updated_mux000854 : LUT4
16117 
    generic map(
16118 
      INIT => X"FFA8"
16119 
    )
16120 
    port map (
16121 
      I0 => fax4_ins_state_FSM_FFd8_1338,
16122 
      I1 => fax4_ins_EOL,
16123 
      I2 => fax4_ins_pix_changed_1319,
16124 
      I3 => fax4_ins_state_updated_mux000840_1347,
16125 
      O => fax4_ins_state_updated_mux000854_1348
16126 
    );
16127 
  huffman_ins_v2_hor_code_14_mux0003126 : LUT4
16128 
    generic map(
16129 
      INIT => X"1000"
16130 
    )
16131 
    port map (
16132 
      I0 => huffman_ins_v2_code_black_width(4),
16133 
      I1 => huffman_ins_v2_N203,
16134 
      I2 => huffman_ins_v2_hor_code_14_mux0003117_1865,
16135 
      I3 => huffman_ins_v2_code_black_width(1),
16136 
      O => huffman_ins_v2_hor_code_14_mux0003126_1866
16137 
    );
16138 
  fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq000023 : LUT4
16139 
    generic map(
16140 
      INIT => X"2000"
16141 
    )
16142 
    port map (
16143 
      I0 => fax4_ins_FIFO2_multi_read_ins_write_pos(9),
16144 
      I1 => fax4_ins_FIFO2_multi_read_ins_write_pos(8),
16145 
      I2 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq00007_715,
16146 
      I3 => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq000015_714,
16147 
      O => fax4_ins_FIFO2_multi_read_ins_write_pos_cmp_eq0000
16148 
    );
16149 
  fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq000023 : LUT4
16150 
    generic map(
16151 
      INIT => X"2000"
16152 
    )
16153 
    port map (
16154 
      I0 => fax4_ins_FIFO2_multi_read_ins_read_pos(9),
16155 
      I1 => fax4_ins_FIFO2_multi_read_ins_read_pos(8),
16156 
      I2 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq00007_682,
16157 
      I3 => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq000015_681,
16158 
      O => fax4_ins_FIFO2_multi_read_ins_read_pos_cmp_eq0000
16159 
    );
16160 
  fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq000023 : LUT4
16161 
    generic map(
16162 
      INIT => X"2000"
16163 
    )
16164 
    port map (
16165 
      I0 => fax4_ins_FIFO1_multi_read_ins_write_pos(9),
16166 
      I1 => fax4_ins_FIFO1_multi_read_ins_write_pos(8),
16167 
      I2 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq00007_472,
16168 
      I3 => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq000015_471,
16169 
      O => fax4_ins_FIFO1_multi_read_ins_write_pos_cmp_eq0000
16170 
    );
16171 
  fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq000023 : LUT4
16172 
    generic map(
16173 
      INIT => X"2000"
16174 
    )
16175 
    port map (
16176 
      I0 => fax4_ins_FIFO1_multi_read_ins_read_pos(9),
16177 
      I1 => fax4_ins_FIFO1_multi_read_ins_read_pos(8),
16178 
      I2 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq00007_440,
16179 
      I3 => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq000015_439,
16180 
      O => fax4_ins_FIFO1_multi_read_ins_read_pos_cmp_eq0000
16181 
    );
16182 
  fax4_ins_mode_indicator_o_mux0001_3_41_SW1 : LUT4
16183 
    generic map(
16184 
      INIT => X"F3F1"
16185 
    )
16186 
    port map (
16187 
      I0 => fax4_ins_EOL_prev_230,
16188 
      I1 => fax4_ins_load_a1_or0001,
16189 
      I2 => fax4_ins_state_FSM_FFd8_1338,
16190 
      I3 => fax4_ins_EOL_prev_prev_231,
16191 
      O => N160
16192 
    );
16193 
  huffman_ins_v2_hor_code_16_mux0003138 : LUT4
16194 
    generic map(
16195 
      INIT => X"EAAA"
16196 
    )
16197 
    port map (
16198 
      I0 => huffman_ins_v2_hor_code_16_mux0003136_1898,
16199 
      I1 => huffman_ins_v2_hor_code_16_mux0003117_1897,
16200 
      I2 => huffman_ins_v2_code_black_width(4),
16201 
      I3 => huffman_ins_v2_code_black(16),
16202 
      O => huffman_ins_v2_hor_code_16_mux0003138_1899
16203 
    );
16204 
  huffman_ins_v2_hor_code_18_mux000381 : LUT4
16205 
    generic map(
16206 
      INIT => X"0133"
16207 
    )
16208 
    port map (
16209 
      I0 => N305,
16210 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
16211 
      I2 => huffman_ins_v2_N246,
16212 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
16213 
      O => huffman_ins_v2_hor_code_18_mux000381_1923
16214 
    );
16215 
  huffman_ins_v2_code_white_13_mux00006_SW0 : LUT4
16216 
    generic map(
16217 
      INIT => X"F888"
16218 
    )
16219 
    port map (
16220 
      I0 => huffman_ins_v2_code_table_ins_makeup_white(8),
16221 
      I1 => huffman_ins_v2_code_white_8_cmp_eq0001,
16222 
      I2 => huffman_ins_v2_code_white(13),
16223 
      I3 => huffman_ins_v2_code_white_8_or0000,
16224 
      O => N315
16225 
    );
16226 
  huffman_ins_v2_code_white_13_mux00006 : LUT3
16227 
    generic map(
16228 
      INIT => X"EA"
16229 
    )
16230 
    port map (
16231 
      I0 => N315,
16232 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(5),
16233 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0004,
16234 
      O => huffman_ins_v2_code_white_13_mux00006_1751
16235 
    );
16236 
  fax4_ins_state_FSM_FFd6_In_SW2 : LUT4
16237 
    generic map(
16238 
      INIT => X"F7FF"
16239 
    )
16240 
    port map (
16241 
      I0 => fax4_ins_vertical_mode_cmp_le0000,
16242 
      I1 => fax4_ins_load_a1_or0000,
16243 
      I2 => fax4_ins_state_FSM_FFd8_1338,
16244 
      I3 => fax4_ins_pix_changed_1319,
16245 
      O => N317
16246 
    );
16247 
  fax4_ins_state_FSM_FFd6_In : LUT4
16248 
    generic map(
16249 
      INIT => X"22A2"
16250 
    )
16251 
    port map (
16252 
      I0 => fax4_ins_state_FSM_N7,
16253 
      I1 => N317,
16254 
      I2 => fax4_ins_state_FSM_FFd6_1336,
16255 
      I3 => fax4_ins_N53,
16256 
      O => fax4_ins_state_FSM_FFd6_In_1337
16257 
    );
16258 
  huffman_ins_v2_code_black_6_mux0000250_SW0 : LUT2
16259 
    generic map(
16260 
      INIT => X"E"
16261 
    )
16262 
    port map (
16263 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
16264 
      I1 => huffman_ins_v2_codetab_ter_black_width(0),
16265 
      O => N319
16266 
    );
16267 
  huffman_ins_v2_hor_code_width_mux0001_4_Q : LUT4
16268 
    generic map(
16269 
      INIT => X"EB41"
16270 
    )
16271 
    port map (
16272 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
16273 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
16274 
      I2 => N305,
16275 
      I3 => huffman_ins_v2_mux_code_black_width(4),
16276 
      O => huffman_ins_v2_hor_code_width_mux0001(4)
16277 
    );
16278 
  fax4_ins_state_updated_mux000840_SW0 : LUT4
16279 
    generic map(
16280 
      INIT => X"2232"
16281 
    )
16282 
    port map (
16283 
      I0 => fax4_ins_state_FSM_FFd11_1325,
16284 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
16285 
      I2 => fax4_ins_state_FSM_FFd10_1323,
16286 
      I3 => fax4_ins_EOF_prev_228,
16287 
      O => N333
16288 
    );
16289 
  fax4_ins_state_updated_mux000840 : LUT4
16290 
    generic map(
16291 
      INIT => X"FF04"
16292 
    )
16293 
    port map (
16294 
      I0 => fax4_ins_state_FSM_FFd2_1327,
16295 
      I1 => fax4_ins_state_updated_mux000824_1346,
16296 
      I2 => fax4_ins_state_FSM_FFd6_1336,
16297 
      I3 => N333,
16298 
      O => fax4_ins_state_updated_mux000840_1347
16299 
    );
16300 
  huffman_ins_v2_hor_code_19_mux000380 : LUT4
16301 
    generic map(
16302 
      INIT => X"EAAA"
16303 
    )
16304 
    port map (
16305 
      I0 => huffman_ins_v2_hor_code_19_mux00036_1927,
16306 
      I1 => huffman_ins_v2_code_black(19),
16307 
      I2 => huffman_ins_v2_code_black_width(4),
16308 
      I3 => N337,
16309 
      O => huffman_ins_v2_hor_code_19_mux000380_1928
16310 
    );
16311 
  huffman_ins_v2_hor_code_24_mux000316 : LUT4
16312 
    generic map(
16313 
      INIT => X"EAAA"
16314 
    )
16315 
    port map (
16316 
      I0 => huffman_ins_v2_hor_code_24_mux000312_1973,
16317 
      I1 => huffman_ins_v2_N228,
16318 
      I2 => huffman_ins_v2_mux_code_black_width(0),
16319 
      I3 => huffman_ins_v2_code_black(24),
16320 
      O => huffman_ins_v2_hor_code_24_mux000316_1974
16321 
    );
16322 
  huffman_ins_v2_code_black_20_mux0000166_SW0 : LUT4
16323 
    generic map(
16324 
      INIT => X"ABA8"
16325 
    )
16326 
    port map (
16327 
      I0 => huffman_ins_v2_code_black(20),
16328 
      I1 => huffman_ins_v2_codetab_ter_black_width(0),
16329 
      I2 => huffman_ins_v2_codetab_ter_black_width(1),
16330 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
16331 
      O => N339
16332 
    );
16333 
  huffman_ins_v2_code_black_20_mux0000166 : LUT4
16334 
    generic map(
16335 
      INIT => X"A820"
16336 
    )
16337 
    port map (
16338 
      I0 => huffman_ins_v2_codetab_ter_black_width(3),
16339 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
16340 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
16341 
      I3 => N339,
16342 
      O => huffman_ins_v2_code_black_20_mux0000166_1598
16343 
    );
16344 
  fax4_ins_FIFO2_multi_read_ins_mux1_valid1 : LUT4
16345 
    generic map(
16346 
      INIT => X"AEAA"
16347 
    )
16348 
    port map (
16349 
      I0 => fax4_ins_FIFO2_multi_read_ins_valid2_o_699,
16350 
      I1 => fax4_ins_FIFO2_multi_read_ins_N7,
16351 
      I2 => fax4_ins_FIFO2_multi_read_ins_used(0),
16352 
      I3 => fax4_ins_fifo2_wr,
16353 
      O => fax4_ins_FIFO2_multi_read_ins_mux1_valid
16354 
    );
16355 
  fax4_ins_FIFO1_multi_read_ins_mux1_valid1 : LUT4
16356 
    generic map(
16357 
      INIT => X"AEAA"
16358 
    )
16359 
    port map (
16360 
      I0 => fax4_ins_FIFO1_multi_read_ins_valid2_o_457,
16361 
      I1 => fax4_ins_FIFO1_multi_read_ins_N7,
16362 
      I2 => fax4_ins_FIFO1_multi_read_ins_used(0),
16363 
      I3 => fax4_ins_fifo1_wr,
16364 
      O => fax4_ins_FIFO1_multi_read_ins_mux1_valid
16365 
    );
16366 
  huffman_ins_v2_hor_code_6_mux000361 : LUT4
16367 
    generic map(
16368 
      INIT => X"AA02"
16369 
    )
16370 
    port map (
16371 
      I0 => huffman_ins_v2_N107,
16372 
      I1 => huffman_ins_v2_mux_code_black_width(4),
16373 
      I2 => huffman_ins_v2_N67,
16374 
      I3 => huffman_ins_v2_N48,
16375 
      O => huffman_ins_v2_hor_code_6_mux000361_2018
16376 
    );
16377 
  huffman_ins_v2_hor_code_11_mux000374 : LUT4
16378 
    generic map(
16379 
      INIT => X"8A02"
16380 
    )
16381 
    port map (
16382 
      I0 => huffman_ins_v2_hor_code_11_mux000373_1835,
16383 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
16384 
      I2 => huffman_ins_v2_N98,
16385 
      I3 => huffman_ins_v2_N14,
16386 
      O => huffman_ins_v2_hor_code_11_mux000374_1836
16387 
    );
16388 
  huffman_ins_v2_hor_code_17_mux000316 : LUT4
16389 
    generic map(
16390 
      INIT => X"1400"
16391 
    )
16392 
    port map (
16393 
      I0 => huffman_ins_v2_a0_value_2_1510,
16394 
      I1 => huffman_ins_v2_code_black_width(3),
16395 
      I2 => huffman_ins_v2_N59,
16396 
      I3 => huffman_ins_v2_N102,
16397 
      O => huffman_ins_v2_hor_code_17_mux000316_1907
16398 
    );
16399 
  fax4_ins_FIFO2_multi_read_ins_mux2_valid1 : LUT4
16400 
    generic map(
16401 
      INIT => X"EAAA"
16402 
    )
16403 
    port map (
16404 
      I0 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
16405 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(0),
16406 
      I2 => fax4_ins_fifo2_wr,
16407 
      I3 => fax4_ins_FIFO2_multi_read_ins_N7,
16408 
      O => fax4_ins_FIFO2_multi_read_ins_mux2_valid
16409 
    );
16410 
  fax4_ins_FIFO1_multi_read_ins_mux2_valid1 : LUT4
16411 
    generic map(
16412 
      INIT => X"EAAA"
16413 
    )
16414 
    port map (
16415 
      I0 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
16416 
      I1 => fax4_ins_FIFO1_multi_read_ins_used(0),
16417 
      I2 => fax4_ins_fifo1_wr,
16418 
      I3 => fax4_ins_FIFO1_multi_read_ins_N7,
16419 
      O => fax4_ins_FIFO1_multi_read_ins_mux2_valid
16420 
    );
16421 
  huffman_ins_v2_hor_code_5_mux00037 : LUT4
16422 
    generic map(
16423 
      INIT => X"1000"
16424 
    )
16425 
    port map (
16426 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
16427 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
16428 
      I2 => huffman_ins_v2_N70,
16429 
      I3 => huffman_ins_v2_N109,
16430 
      O => huffman_ins_v2_hor_code_5_mux00037_2010
16431 
    );
16432 
  fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_and0000111_SW6 : LUT4
16433 
    generic map(
16434 
      INIT => X"FFFE"
16435 
    )
16436 
    port map (
16437 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(2),
16438 
      I1 => fax4_ins_FIFO1_multi_read_ins_used(1),
16439 
      I2 => fax4_ins_FIFO1_multi_read_ins_N4,
16440 
      I3 => fax4_ins_FIFO1_multi_read_ins_used(0),
16441 
      O => N208
16442 
    );
16443 
  huffman_ins_v2_hor_code_0_mux000311 : LUT4
16444 
    generic map(
16445 
      INIT => X"72FA"
16446 
    )
16447 
    port map (
16448 
      I0 => huffman_ins_v2_mux_code_black_width(4),
16449 
      I1 => huffman_ins_v2_mux_code_black_width(3),
16450 
      I2 => huffman_ins_v2_N89,
16451 
      I3 => huffman_ins_v2_N99,
16452 
      O => huffman_ins_v2_N16
16453 
    );
16454 
  huffman_ins_v2_hor_code_17_mux000319 : LUT4
16455 
    generic map(
16456 
      INIT => X"2800"
16457 
    )
16458 
    port map (
16459 
      I0 => huffman_ins_v2_N107,
16460 
      I1 => huffman_ins_v2_mux_code_black_width(3),
16461 
      I2 => huffman_ins_v2_N99,
16462 
      I3 => huffman_ins_v2_code_black_width(4),
16463 
      O => huffman_ins_v2_hor_code_17_mux000319_1908
16464 
    );
16465 
  huffman_ins_v2_hor_code_21_mux000376 : LUT4
16466 
    generic map(
16467 
      INIT => X"1000"
16468 
    )
16469 
    port map (
16470 
      I0 => huffman_ins_v2_mux_code_white_width(1),
16471 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
16472 
      I2 => huffman_ins_v2_N102,
16473 
      I3 => huffman_ins_v2_N248,
16474 
      O => huffman_ins_v2_hor_code_21_mux000376_1955
16475 
    );
16476 
  huffman_ins_v2_code_white_6_mux000021 : LUT4
16477 
    generic map(
16478 
      INIT => X"AA80"
16479 
    )
16480 
    port map (
16481 
      I0 => huffman_ins_v2_ter_white_code(6),
16482 
      I1 => huffman_ins_v2_codetab_ter_white_width(0),
16483 
      I2 => huffman_ins_v2_N239,
16484 
      I3 => huffman_ins_v2_code_white_8_cmp_eq0004,
16485 
      O => huffman_ins_v2_code_white_6_mux000021_1777
16486 
    );
16487 
  fax4_ins_fifo2_wr1 : LUT4
16488 
    generic map(
16489 
      INIT => X"8000"
16490 
    )
16491 
    port map (
16492 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
16493 
      I1 => fax4_ins_pix_changed_1319,
16494 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
16495 
      I3 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
16496 
      O => fax4_ins_fifo2_wr
16497 
    );
16498 
  fax4_ins_state_FSM_FFd9_In11 : LUT3
16499 
    generic map(
16500 
      INIT => X"08"
16501 
    )
16502 
    port map (
16503 
      I0 => fax4_ins_load_a1_or0000,
16504 
      I1 => fax4_ins_vertical_mode_cmp_le0000,
16505 
      I2 => fax4_ins_state_FSM_FFd8_1338,
16506 
      O => fax4_ins_state_FSM_FFd9_In1
16507 
    );
16508 
  huffman_ins_v2_hor_code_12_mux000351 : LUT4
16509 
    generic map(
16510 
      INIT => X"7A2A"
16511 
    )
16512 
    port map (
16513 
      I0 => huffman_ins_v2_mux_code_black_width(4),
16514 
      I1 => huffman_ins_v2_N99,
16515 
      I2 => huffman_ins_v2_mux_code_black_width(3),
16516 
      I3 => huffman_ins_v2_N251,
16517 
      O => huffman_ins_v2_N60
16518 
    );
16519 
  huffman_ins_v2_hor_code_17_mux000371 : LUT4
16520 
    generic map(
16521 
      INIT => X"FF8D"
16522 
    )
16523 
    port map (
16524 
      I0 => huffman_ins_v2_mux_code_black_width(3),
16525 
      I1 => huffman_ins_v2_N251,
16526 
      I2 => huffman_ins_v2_N99,
16527 
      I3 => N12,
16528 
      O => huffman_ins_v2_hor_code_17_mux000371_1911
16529 
    );
16530 
  huffman_ins_v2_hor_code_7_mux000368 : LUT4
16531 
    generic map(
16532 
      INIT => X"1000"
16533 
    )
16534 
    port map (
16535 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
16536 
      I1 => huffman_ins_v2_N70,
16537 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
16538 
      I3 => huffman_ins_v2_N109,
16539 
      O => huffman_ins_v2_hor_code_7_mux000368_2026
16540 
    );
16541 
  huffman_ins_v2_code_white_15_mux00001 : LUT3
16542 
    generic map(
16543 
      INIT => X"80"
16544 
    )
16545 
    port map (
16546 
      I0 => huffman_ins_v2_codetab_ter_white_width(0),
16547 
      I1 => huffman_ins_v2_N239,
16548 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(8),
16549 
      O => huffman_ins_v2_code_white_15_mux00001_1756
16550 
    );
16551 
  huffman_ins_v2_hor_code_25_mux00030 : LUT4
16552 
    generic map(
16553 
      INIT => X"2000"
16554 
    )
16555 
    port map (
16556 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
16557 
      I1 => huffman_ins_v2_N59,
16558 
      I2 => huffman_ins_v2_N102,
16559 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
16560 
      O => huffman_ins_v2_hor_code_25_mux00030_1979
16561 
    );
16562 
  fax4_ins_mode_indicator_o_3_rstpot_SW1 : LUT4
16563 
    generic map(
16564 
      INIT => X"0C08"
16565 
    )
16566 
    port map (
16567 
      I0 => fax4_ins_pass_mode,
16568 
      I1 => fax4_ins_state_FSM_N7,
16569 
      I2 => fax4_ins_pix_changed_1319,
16570 
      I3 => fax4_ins_mode_indicator_o(3),
16571 
      O => N180
16572 
    );
16573 
  fax4_ins_load_a2_or00001 : LUT4
16574 
    generic map(
16575 
      INIT => X"F444"
16576 
    )
16577 
    port map (
16578 
      I0 => fax4_ins_EOL_prev_230,
16579 
      I1 => fax4_ins_EOL,
16580 
      I2 => fax4_ins_pix_changed_1319,
16581 
      I3 => fax4_ins_state_FSM_FFd8_1338,
16582 
      O => fax4_ins_load_a2
16583 
    );
16584 
  huffman_ins_v2_Madd_code_white_width_add0000_cy_1_11 : LUT4
16585 
    generic map(
16586 
      INIT => X"EA80"
16587 
    )
16588 
    port map (
16589 
      I0 => huffman_ins_v2_code_table_ins_makeup_white(10),
16590 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(9),
16591 
      I2 => huffman_ins_v2_codetab_ter_white_width(0),
16592 
      I3 => huffman_ins_v2_codetab_ter_white_width(1),
16593 
      O => huffman_ins_v2_Madd_code_white_width_add0000_cy_1_Q
16594 
    );
16595 
  huffman_ins_v2_Madd_code_black_width_add0000_cy_1_11 : LUT4
16596 
    generic map(
16597 
      INIT => X"EA80"
16598 
    )
16599 
    port map (
16600 
      I0 => huffman_ins_v2_code_table_ins_makeup_black_14_Q,
16601 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_13_Q,
16602 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
16603 
      I3 => huffman_ins_v2_codetab_ter_black_width(1),
16604 
      O => huffman_ins_v2_Madd_code_black_width_add0000_cy_1_Q
16605 
    );
16606 
  huffman_ins_v2_hor_code_12_mux0003175 : LUT4
16607 
    generic map(
16608 
      INIT => X"0103"
16609 
    )
16610 
    port map (
16611 
      I0 => huffman_ins_v2_N59,
16612 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
16613 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
16614 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
16615 
      O => huffman_ins_v2_hor_code_12_mux0003175_1843
16616 
    );
16617 
  huffman_ins_v2_hor_code_20_mux000315 : LUT4
16618 
    generic map(
16619 
      INIT => X"9993"
16620 
    )
16621 
    port map (
16622 
      I0 => huffman_ins_v2_mux_code_black_width(2),
16623 
      I1 => huffman_ins_v2_mux_code_black_width(3),
16624 
      I2 => huffman_ins_v2_mux_code_black_width(0),
16625 
      I3 => huffman_ins_v2_mux_code_black_width(1),
16626 
      O => huffman_ins_v2_hor_code_20_mux000315_1942
16627 
    );
16628 
  huffman_ins_v2_hor_code_21_mux000341 : LUT3
16629 
    generic map(
16630 
      INIT => X"80"
16631 
    )
16632 
    port map (
16633 
      I0 => huffman_ins_v2_a0_value_2_1510,
16634 
      I1 => huffman_ins_v2_code_black_width(4),
16635 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
16636 
      O => huffman_ins_v2_N95
16637 
    );
16638 
  huffman_ins_v2_Madd_code_white_width_add0000_xor_1_11 : LUT4
16639 
    generic map(
16640 
      INIT => X"9666"
16641 
    )
16642 
    port map (
16643 
      I0 => huffman_ins_v2_code_table_ins_makeup_white(10),
16644 
      I1 => huffman_ins_v2_codetab_ter_white_width(1),
16645 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(9),
16646 
      I3 => huffman_ins_v2_codetab_ter_white_width(0),
16647 
      O => huffman_ins_v2_code_white_width_add0000(1)
16648 
    );
16649 
  huffman_ins_v2_Madd_code_black_width_add0000_xor_1_11 : LUT4
16650 
    generic map(
16651 
      INIT => X"9666"
16652 
    )
16653 
    port map (
16654 
      I0 => huffman_ins_v2_code_table_ins_makeup_black_14_Q,
16655 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
16656 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_13_Q,
16657 
      I3 => huffman_ins_v2_codetab_ter_black_width(0),
16658 
      O => huffman_ins_v2_code_black_width_add0000(1)
16659 
    );
16660 
  huffman_ins_v2_hor_code_18_mux0003199 : LUT4
16661 
    generic map(
16662 
      INIT => X"5562"
16663 
    )
16664 
    port map (
16665 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
16666 
      I1 => huffman_ins_v2_mux_code_white_width(1),
16667 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
16668 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
16669 
      O => huffman_ins_v2_hor_code_18_mux0003199_1919
16670 
    );
16671 
  fax4_ins_FIFO1_multi_read_ins_mux3_and0000_SW1 : LUT4
16672 
    generic map(
16673 
      INIT => X"FDFF"
16674 
    )
16675 
    port map (
16676 
      I0 => fax4_ins_FIFO1_multi_read_ins_used(1),
16677 
      I1 => fax4_ins_FIFO1_multi_read_ins_used(2),
16678 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
16679 
      I3 => fax4_ins_pix_changed_1319,
16680 
      O => N341
16681 
    );
16682 
  huffman_ins_v2_code_white_13_mux000015 : LUT4
16683 
    generic map(
16684 
      INIT => X"A820"
16685 
    )
16686 
    port map (
16687 
      I0 => huffman_ins_v2_N239,
16688 
      I1 => huffman_ins_v2_codetab_ter_white_width(0),
16689 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(7),
16690 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(6),
16691 
      O => huffman_ins_v2_code_white_13_mux000015_1750
16692 
    );
16693 
  huffman_ins_v2_code_white_9_mux000021 : LUT4
16694 
    generic map(
16695 
      INIT => X"A820"
16696 
    )
16697 
    port map (
16698 
      I0 => huffman_ins_v2_N239,
16699 
      I1 => huffman_ins_v2_codetab_ter_white_width(0),
16700 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(3),
16701 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(2),
16702 
      O => huffman_ins_v2_code_white_9_mux000021_1795
16703 
    );
16704 
  huffman_ins_v2_code_white_8_mux000021 : LUT4
16705 
    generic map(
16706 
      INIT => X"A820"
16707 
    )
16708 
    port map (
16709 
      I0 => huffman_ins_v2_N239,
16710 
      I1 => huffman_ins_v2_codetab_ter_white_width(0),
16711 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(2),
16712 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(1),
16713 
      O => huffman_ins_v2_code_white_8_mux000021_1789
16714 
    );
16715 
  huffman_ins_v2_code_white_7_mux000021 : LUT4
16716 
    generic map(
16717 
      INIT => X"A820"
16718 
    )
16719 
    port map (
16720 
      I0 => huffman_ins_v2_N239,
16721 
      I1 => huffman_ins_v2_codetab_ter_white_width(0),
16722 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(1),
16723 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(0),
16724 
      O => huffman_ins_v2_code_white_7_mux000021_1781
16725 
    );
16726 
  huffman_ins_v2_code_white_12_mux000021 : LUT4
16727 
    generic map(
16728 
      INIT => X"A820"
16729 
    )
16730 
    port map (
16731 
      I0 => huffman_ins_v2_N239,
16732 
      I1 => huffman_ins_v2_codetab_ter_white_width(0),
16733 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(6),
16734 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(5),
16735 
      O => huffman_ins_v2_code_white_12_mux000021_1746
16736 
    );
16737 
  huffman_ins_v2_code_white_11_mux000021 : LUT4
16738 
    generic map(
16739 
      INIT => X"A820"
16740 
    )
16741 
    port map (
16742 
      I0 => huffman_ins_v2_N239,
16743 
      I1 => huffman_ins_v2_codetab_ter_white_width(0),
16744 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(5),
16745 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(4),
16746 
      O => huffman_ins_v2_code_white_11_mux000021_1741
16747 
    );
16748 
  huffman_ins_v2_code_white_10_mux000021 : LUT4
16749 
    generic map(
16750 
      INIT => X"A820"
16751 
    )
16752 
    port map (
16753 
      I0 => huffman_ins_v2_N239,
16754 
      I1 => huffman_ins_v2_codetab_ter_white_width(0),
16755 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(4),
16756 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(3),
16757 
      O => huffman_ins_v2_code_white_10_mux000021_1736
16758 
    );
16759 
  huffman_ins_v2_hor_code_14_mux0003117 : LUT4
16760 
    generic map(
16761 
      INIT => X"9011"
16762 
    )
16763 
    port map (
16764 
      I0 => huffman_ins_v2_a0_value_2_1510,
16765 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
16766 
      I2 => huffman_ins_v2_code_black(14),
16767 
      I3 => huffman_ins_v2_code_black_width(0),
16768 
      O => huffman_ins_v2_hor_code_14_mux0003117_1865
16769 
    );
16770 
  huffman_ins_v2_hor_code_14_mux0003203 : LUT4
16771 
    generic map(
16772 
      INIT => X"4602"
16773 
    )
16774 
    port map (
16775 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
16776 
      I1 => huffman_ins_v2_a0_value_2_1510,
16777 
      I2 => huffman_ins_v2_code_white_width(1),
16778 
      I3 => huffman_ins_v2_code_white_width(4),
16779 
      O => huffman_ins_v2_hor_code_14_mux0003203_1871
16780 
    );
16781 
  huffman_ins_v2_hor_code_14_mux0003256 : LUT4
16782 
    generic map(
16783 
      INIT => X"1908"
16784 
    )
16785 
    port map (
16786 
      I0 => huffman_ins_v2_a0_value_2_1510,
16787 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
16788 
      I2 => huffman_ins_v2_code_black_width(1),
16789 
      I3 => huffman_ins_v2_code_black_width(4),
16790 
      O => huffman_ins_v2_hor_code_14_mux0003256_1874
16791 
    );
16792 
  huffman_ins_v2_hor_code_14_mux000371 : LUT4
16793 
    generic map(
16794 
      INIT => X"6022"
16795 
    )
16796 
    port map (
16797 
      I0 => huffman_ins_v2_a0_value_2_1510,
16798 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
16799 
      I2 => huffman_ins_v2_code_white(14),
16800 
      I3 => huffman_ins_v2_code_white_width(0),
16801 
      O => huffman_ins_v2_hor_code_14_mux000371_1880
16802 
    );
16803 
  huffman_ins_v2_hor_code_13_mux000386 : LUT4
16804 
    generic map(
16805 
      INIT => X"A820"
16806 
    )
16807 
    port map (
16808 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
16809 
      I1 => huffman_ins_v2_a0_value_2_1510,
16810 
      I2 => huffman_ins_v2_code_white(13),
16811 
      I3 => huffman_ins_v2_code_black(13),
16812 
      O => huffman_ins_v2_hor_code_13_mux000386_1859
16813 
    );
16814 
  huffman_ins_v2_hor_code_width_mux0001_0_1 : LUT4
16815 
    generic map(
16816 
      INIT => X"A3C5"
16817 
    )
16818 
    port map (
16819 
      I0 => huffman_ins_v2_code_black_width(0),
16820 
      I1 => huffman_ins_v2_code_white_width(0),
16821 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
16822 
      I3 => huffman_ins_v2_a0_value_2_1510,
16823 
      O => huffman_ins_v2_hor_code_width_mux0001(0)
16824 
    );
16825 
  fax4_ins_FIFO1_multi_read_ins_wr_SW1 : LUT4
16826 
    generic map(
16827 
      INIT => X"FFEA"
16828 
    )
16829 
    port map (
16830 
      I0 => fax4_ins_FIFO1_multi_read_ins_N4,
16831 
      I1 => fax4_ins_FIFO1_multi_read_ins_used(0),
16832 
      I2 => fax4_ins_FIFO1_multi_read_ins_used(1),
16833 
      I3 => fax4_ins_FIFO1_multi_read_ins_used(2),
16834 
      O => N343
16835 
    );
16836 
  fax4_ins_FIFO1_multi_read_ins_wr : LUT4
16837 
    generic map(
16838 
      INIT => X"1000"
16839 
    )
16840 
    port map (
16841 
      I0 => fax4_ins_EOL,
16842 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
16843 
      I2 => fax4_ins_pix_changed_1319,
16844 
      I3 => N343,
16845 
      O => fax4_ins_FIFO1_multi_read_ins_wr_459
16846 
    );
16847 
  fax4_ins_a1_o_mux0000_9_1 : LUT3
16848 
    generic map(
16849 
      INIT => X"F7"
16850 
    )
16851 
    port map (
16852 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
16853 
      I1 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
16854 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
16855 
      O => fax4_ins_a1_o_mux0000(9)
16856 
    );
16857 
  fax4_ins_a1_o_mux0000_5_1 : LUT3
16858 
    generic map(
16859 
      INIT => X"F7"
16860 
    )
16861 
    port map (
16862 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
16863 
      I1 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
16864 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
16865 
      O => fax4_ins_a1_o_mux0000(5)
16866 
    );
16867 
  fax4_ins_a1_o_mux0000_4_1 : LUT3
16868 
    generic map(
16869 
      INIT => X"F7"
16870 
    )
16871 
    port map (
16872 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
16873 
      I1 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
16874 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
16875 
      O => fax4_ins_a1_o_mux0000(4)
16876 
    );
16877 
  fax4_ins_a1_o_mux0000_3_1 : LUT3
16878 
    generic map(
16879 
      INIT => X"F7"
16880 
    )
16881 
    port map (
16882 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
16883 
      I1 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
16884 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
16885 
      O => fax4_ins_a1_o_mux0000(3)
16886 
    );
16887 
  fax4_ins_a1_o_mux0000_2_1 : LUT3
16888 
    generic map(
16889 
      INIT => X"F7"
16890 
    )
16891 
    port map (
16892 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
16893 
      I1 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
16894 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
16895 
      O => fax4_ins_a1_o_mux0000(2)
16896 
    );
16897 
  fax4_ins_a1_o_mux0000_0_1 : LUT3
16898 
    generic map(
16899 
      INIT => X"F7"
16900 
    )
16901 
    port map (
16902 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
16903 
      I1 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
16904 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
16905 
      O => fax4_ins_a1_o_mux0000(0)
16906 
    );
16907 
  huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux00011011 : LUT3
16908 
    generic map(
16909 
      INIT => X"01"
16910 
    )
16911 
    port map (
16912 
      I0 => huffman_ins_v2_run_length_black(9),
16913 
      I1 => huffman_ins_v2_run_length_black(7),
16914 
      I2 => huffman_ins_v2_run_length_black(8),
16915 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux0001101
16916 
    );
16917 
  fax4_ins_a0_to_white_mux000026 : LUT4
16918 
    generic map(
16919 
      INIT => X"EC4C"
16920 
    )
16921 
    port map (
16922 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
16923 
      I1 => fax4_ins_pix_prev_1321,
16924 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
16925 
      I3 => fax4_ins_to_white_1349,
16926 
      O => fax4_ins_a0_to_white_mux000026_948
16927 
    );
16928 
  fax4_ins_state_FSM_FFd10_In41 : LUT4
16929 
    generic map(
16930 
      INIT => X"1000"
16931 
    )
16932 
    port map (
16933 
      I0 => fax4_ins_pass_mode,
16934 
      I1 => fax4_ins_pix_changed_1319,
16935 
      I2 => fax4_ins_state_FSM_N7,
16936 
      I3 => fax4_ins_state_FSM_FFd10_1323,
16937 
      O => fax4_ins_state_FSM_N12
16938 
    );
16939 
  huffman_ins_v2_hor_code_20_mux000346 : LUT4
16940 
    generic map(
16941 
      INIT => X"C080"
16942 
    )
16943 
    port map (
16944 
      I0 => huffman_ins_v2_mux_code_white_width(1),
16945 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
16946 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
16947 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
16948 
      O => huffman_ins_v2_hor_code_20_mux000346_1945
16949 
    );
16950 
  huffman_ins_v2_hor_code_17_mux000361 : LUT4
16951 
    generic map(
16952 
      INIT => X"0E04"
16953 
    )
16954 
    port map (
16955 
      I0 => huffman_ins_v2_a0_value_2_1510,
16956 
      I1 => huffman_ins_v2_code_black_width(4),
16957 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
16958 
      I3 => huffman_ins_v2_code_white_width(4),
16959 
      O => huffman_ins_v2_N102
16960 
    );
16961 
  huffman_ins_v2_hor_code_21_mux000395 : LUT3
16962 
    generic map(
16963 
      INIT => X"08"
16964 
    )
16965 
    port map (
16966 
      I0 => huffman_ins_v2_mux_code_black_width(2),
16967 
      I1 => huffman_ins_v2_mux_code_black_width(0),
16968 
      I2 => huffman_ins_v2_mux_code_black_width(1),
16969 
      O => huffman_ins_v2_hor_code_21_mux000395_1957
16970 
    );
16971 
  huffman_ins_v2_hor_code_19_mux00036 : LUT4
16972 
    generic map(
16973 
      INIT => X"1000"
16974 
    )
16975 
    port map (
16976 
      I0 => huffman_ins_v2_N70,
16977 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
16978 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
16979 
      I3 => huffman_ins_v2_N246,
16980 
      O => huffman_ins_v2_hor_code_19_mux00036_1927
16981 
    );
16982 
  huffman_ins_v2_hor_code_3_mux00033 : LUT3
16983 
    generic map(
16984 
      INIT => X"01"
16985 
    )
16986 
    port map (
16987 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
16988 
      I1 => huffman_ins_v2_mux_code_white_width(1),
16989 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
16990 
      O => huffman_ins_v2_hor_code_3_mux00033_1992
16991 
    );
16992 
  huffman_ins_v2_hor_code_0_mux000322 : LUT4
16993 
    generic map(
16994 
      INIT => X"0010"
16995 
    )
16996 
    port map (
16997 
      I0 => huffman_ins_v2_N59,
16998 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
16999 
      I2 => huffman_ins_v2_N109,
17000 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17001 
      O => huffman_ins_v2_hor_code_0_mux000322_1817
17002 
    );
17003 
  huffman_ins_v2_code_black_21_mux000012 : LUT3
17004 
    generic map(
17005 
      INIT => X"C8"
17006 
    )
17007 
    port map (
17008 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
17009 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
17010 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
17011 
      O => huffman_ins_v2_code_black_21_mux000011_1603
17012 
    );
17013 
  huffman_ins_v2_code_black_18_mux000012 : LUT4
17014 
    generic map(
17015 
      INIT => X"EC4C"
17016 
    )
17017 
    port map (
17018 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
17019 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
17020 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
17021 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_7_Q,
17022 
      O => huffman_ins_v2_code_black_18_mux000011_1586
17023 
    );
17024 
  huffman_ins_v2_horizontal_mode_1_cmp_eq00012 : LUT4
17025 
    generic map(
17026 
      INIT => X"1000"
17027 
    )
17028 
    port map (
17029 
      I0 => fax4_ins_mode_indicator_o(1),
17030 
      I1 => fax4_ins_mode_indicator_o(2),
17031 
      I2 => fax4_ins_mode_indicator_o(0),
17032 
      I3 => fax4_ins_mode_indicator_o(3),
17033 
      O => huffman_ins_v2_horizontal_mode_1_cmp_eq0001
17034 
    );
17035 
  fax4_ins_a1_o_mux0000_8_1 : LUT3
17036 
    generic map(
17037 
      INIT => X"80"
17038 
    )
17039 
    port map (
17040 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
17041 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
17042 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
17043 
      O => fax4_ins_a1_o_mux0000(8)
17044 
    );
17045 
  fax4_ins_a1_o_mux0000_7_1 : LUT3
17046 
    generic map(
17047 
      INIT => X"80"
17048 
    )
17049 
    port map (
17050 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
17051 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
17052 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
17053 
      O => fax4_ins_a1_o_mux0000(7)
17054 
    );
17055 
  fax4_ins_a1_o_mux0000_6_1 : LUT3
17056 
    generic map(
17057 
      INIT => X"80"
17058 
    )
17059 
    port map (
17060 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
17061 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
17062 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
17063 
      O => fax4_ins_a1_o_mux0000(6)
17064 
    );
17065 
  fax4_ins_a1_o_mux0000_1_1 : LUT3
17066 
    generic map(
17067 
      INIT => X"80"
17068 
    )
17069 
    port map (
17070 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
17071 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
17072 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
17073 
      O => fax4_ins_a1_o_mux0000(1)
17074 
    );
17075 
  huffman_ins_v2_hor_code_0_mux000321 : LUT4
17076 
    generic map(
17077 
      INIT => X"777F"
17078 
    )
17079 
    port map (
17080 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
17081 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17082 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17083 
      I3 => huffman_ins_v2_mux_code_white_width(1),
17084 
      O => huffman_ins_v2_N45
17085 
    );
17086 
  huffman_ins_v2_hor_code_19_mux000323 : LUT4
17087 
    generic map(
17088 
      INIT => X"2028"
17089 
    )
17090 
    port map (
17091 
      I0 => huffman_ins_v2_N107,
17092 
      I1 => huffman_ins_v2_mux_code_black_width(3),
17093 
      I2 => huffman_ins_v2_mux_code_black_width(2),
17094 
      I3 => huffman_ins_v2_mux_code_black_width(1),
17095 
      O => huffman_ins_v2_hor_code_19_mux000323_1926
17096 
    );
17097 
  huffman_ins_v2_hor_code_15_mux00035 : LUT4
17098 
    generic map(
17099 
      INIT => X"8000"
17100 
    )
17101 
    port map (
17102 
      I0 => huffman_ins_v2_a0_value_2_1510,
17103 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
17104 
      I2 => huffman_ins_v2_code_black_width(4),
17105 
      I3 => huffman_ins_v2_code_black(15),
17106 
      O => huffman_ins_v2_hor_code_15_mux00035_1888
17107 
    );
17108 
  huffman_ins_v2_hor_code_15_mux00038 : LUT4
17109 
    generic map(
17110 
      INIT => X"2000"
17111 
    )
17112 
    port map (
17113 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
17114 
      I1 => huffman_ins_v2_a0_value_2_1510,
17115 
      I2 => huffman_ins_v2_code_white_width(4),
17116 
      I3 => huffman_ins_v2_code_white(15),
17117 
      O => huffman_ins_v2_hor_code_15_mux00038_1893
17118 
    );
17119 
  huffman_ins_v2_hor_code_14_mux0003213 : LUT4
17120 
    generic map(
17121 
      INIT => X"2800"
17122 
    )
17123 
    port map (
17124 
      I0 => huffman_ins_v2_code_white_width(4),
17125 
      I1 => huffman_ins_v2_a0_value_2_1510,
17126 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
17127 
      I3 => huffman_ins_v2_code_white_width(1),
17128 
      O => huffman_ins_v2_hor_code_14_mux0003213_1872
17129 
    );
17130 
  huffman_ins_v2_hor_code_14_mux0003264 : LUT4
17131 
    generic map(
17132 
      INIT => X"9000"
17133 
    )
17134 
    port map (
17135 
      I0 => huffman_ins_v2_a0_value_2_1510,
17136 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
17137 
      I2 => huffman_ins_v2_code_black_width(4),
17138 
      I3 => huffman_ins_v2_code_black_width(1),
17139 
      O => huffman_ins_v2_hor_code_14_mux0003264_1875
17140 
    );
17141 
  huffman_ins_v2_hor_code_14_mux000379 : LUT4
17142 
    generic map(
17143 
      INIT => X"2000"
17144 
    )
17145 
    port map (
17146 
      I0 => huffman_ins_v2_code_white_width(2),
17147 
      I1 => huffman_ins_v2_code_white_width(4),
17148 
      I2 => huffman_ins_v2_code_white_width(3),
17149 
      I3 => huffman_ins_v2_code_white_width(1),
17150 
      O => huffman_ins_v2_hor_code_14_mux000379_1881
17151 
    );
17152 
  fax4_ins_state_FSM_FFd8_In7 : LUT4
17153 
    generic map(
17154 
      INIT => X"2000"
17155 
    )
17156 
    port map (
17157 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
17158 
      I1 => fax4_ins_pix_changed_1319,
17159 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
17160 
      I3 => fax4_ins_state_FSM_FFd8_1338,
17161 
      O => fax4_ins_state_FSM_FFd8_In7_1340
17162 
    );
17163 
  fax4_ins_pix_change_detector_reset_inv1 : LUT3
17164 
    generic map(
17165 
      INIT => X"01"
17166 
    )
17167 
    port map (
17168 
      I0 => fax4_ins_state_FSM_FFd11_1325,
17169 
      I1 => fax4_ins_state_FSM_FFd3_1329,
17170 
      I2 => fax4_ins_state_FSM_FFd9_1341,
17171 
      O => fax4_ins_pix_change_detector_reset_inv
17172 
    );
17173 
  fax4_ins_state_FSM_FFd3_In1 : LUT3
17174 
    generic map(
17175 
      INIT => X"2A"
17176 
    )
17177 
    port map (
17178 
      I0 => fax4_ins_state_FSM_FFd8_1338,
17179 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
17180 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
17181 
      O => fax4_ins_state_FSM_FFd3_In
17182 
    );
17183 
  fax4_ins_mode_indicator_o_mux0001_2_261 : LUT4
17184 
    generic map(
17185 
      INIT => X"569A"
17186 
    )
17187 
    port map (
17188 
      I0 => fax4_ins_a1b1(0),
17189 
      I1 => fax4_ins_EOL,
17190 
      I2 => fax4_ins_a1b1_addsub0000(1),
17191 
      I3 => fax4_ins_a1b1_addsub0001(1),
17192 
      O => fax4_ins_mode_indicator_o_mux0001_2_261_1297
17193 
    );
17194 
  fax4_ins_fifo_rd36_SW0 : LUT4
17195 
    generic map(
17196 
      INIT => X"0001"
17197 
    )
17198 
    port map (
17199 
      I0 => fax4_ins_state_FSM_FFd8_1338,
17200 
      I1 => fax4_ins_state_FSM_FFd5_1333,
17201 
      I2 => fax4_ins_state_FSM_FFd6_1336,
17202 
      I3 => fax4_ins_fifo_rd0_1266,
17203 
      O => N227
17204 
    );
17205 
  fax4_ins_fifo_rd36_SW1 : LUT4
17206 
    generic map(
17207 
      INIT => X"FFFE"
17208 
    )
17209 
    port map (
17210 
      I0 => fax4_ins_state_FSM_FFd8_1338,
17211 
      I1 => fax4_ins_state_FSM_FFd5_1333,
17212 
      I2 => fax4_ins_state_FSM_FFd6_1336,
17213 
      I3 => fax4_ins_fifo_rd0_1266,
17214 
      O => N229
17215 
    );
17216 
  huffman_ins_v2_hor_code_9_mux000320 : LUT4
17217 
    generic map(
17218 
      INIT => X"020A"
17219 
    )
17220 
    port map (
17221 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
17222 
      I1 => huffman_ins_v2_mux_code_black_width(3),
17223 
      I2 => huffman_ins_v2_mux_code_black_width(4),
17224 
      I3 => huffman_ins_v2_N99,
17225 
      O => huffman_ins_v2_hor_code_9_mux000320_2044
17226 
    );
17227 
  huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux0001711 : LUT4
17228 
    generic map(
17229 
      INIT => X"0E04"
17230 
    )
17231 
    port map (
17232 
      I0 => fax4_ins_a0_value_o_950,
17233 
      I1 => huffman_ins_v2_run_length_white_sub0000(7),
17234 
      I2 => huffman_ins_v2_run_length_black(9),
17235 
      I3 => huffman_ins_v2_run_length_white_sub0001(7),
17236 
      O => huffman_ins_v2_code_table_ins_Mrom_makeup_black_mux000171
17237 
    );
17238 
  huffman_ins_v2_hor_code_12_mux000339 : LUT4
17239 
    generic map(
17240 
      INIT => X"1FBF"
17241 
    )
17242 
    port map (
17243 
      I0 => huffman_ins_v2_a0_value_2_1510,
17244 
      I1 => huffman_ins_v2_code_white_width(2),
17245 
      I2 => huffman_ins_v2_mux_code_black_width(3),
17246 
      I3 => huffman_ins_v2_code_black_width(2),
17247 
      O => huffman_ins_v2_hor_code_12_mux000339_1848
17248 
    );
17249 
  huffman_ins_v2_hor_code_24_mux000351 : LUT4
17250 
    generic map(
17251 
      INIT => X"1000"
17252 
    )
17253 
    port map (
17254 
      I0 => huffman_ins_v2_mux_code_black_width(1),
17255 
      I1 => huffman_ins_v2_mux_code_black_width(2),
17256 
      I2 => huffman_ins_v2_hor_code_23_and0000,
17257 
      I3 => huffman_ins_v2_N107,
17258 
      O => huffman_ins_v2_N228
17259 
    );
17260 
  huffman_ins_v2_Madd_code_white_width_add0000_xor_2_11 : LUT3
17261 
    generic map(
17262 
      INIT => X"96"
17263 
    )
17264 
    port map (
17265 
      I0 => huffman_ins_v2_code_table_ins_makeup_white(11),
17266 
      I1 => huffman_ins_v2_codetab_ter_white_width(2),
17267 
      I2 => huffman_ins_v2_Madd_code_white_width_add0000_cy_1_Q,
17268 
      O => huffman_ins_v2_code_white_width_add0000(2)
17269 
    );
17270 
  huffman_ins_v2_Madd_code_black_width_add0000_xor_2_11 : LUT3
17271 
    generic map(
17272 
      INIT => X"96"
17273 
    )
17274 
    port map (
17275 
      I0 => huffman_ins_v2_code_table_ins_makeup_black_15_Q,
17276 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
17277 
      I2 => huffman_ins_v2_Madd_code_black_width_add0000_cy_1_Q,
17278 
      O => huffman_ins_v2_code_black_width_add0000(2)
17279 
    );
17280 
  huffman_ins_v2_hor_code_17_mux000378 : LUT4
17281 
    generic map(
17282 
      INIT => X"8000"
17283 
    )
17284 
    port map (
17285 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17286 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
17287 
      I2 => huffman_ins_v2_N102,
17288 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17289 
      O => huffman_ins_v2_hor_code_17_mux000378_1912
17290 
    );
17291 
  huffman_ins_v2_hor_code_9_mux0003104 : LUT4
17292 
    generic map(
17293 
      INIT => X"0E04"
17294 
    )
17295 
    port map (
17296 
      I0 => huffman_ins_v2_a0_value_2_1510,
17297 
      I1 => huffman_ins_v2_code_black_width(0),
17298 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17299 
      I3 => huffman_ins_v2_code_white_width(0),
17300 
      O => huffman_ins_v2_hor_code_9_mux0003104_2040
17301 
    );
17302 
  huffman_ins_v2_hor_code_8_mux000327 : LUT4
17303 
    generic map(
17304 
      INIT => X"0010"
17305 
    )
17306 
    port map (
17307 
      I0 => huffman_ins_v2_mux_code_black_width(0),
17308 
      I1 => huffman_ins_v2_mux_code_black_width(1),
17309 
      I2 => huffman_ins_v2_N110,
17310 
      I3 => huffman_ins_v2_mux_code_black_width(2),
17311 
      O => huffman_ins_v2_hor_code_8_mux000327_2035
17312 
    );
17313 
  huffman_ins_v2_hor_code_13_mux000325 : LUT4
17314 
    generic map(
17315 
      INIT => X"0C08"
17316 
    )
17317 
    port map (
17318 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
17319 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
17320 
      I2 => huffman_ins_v2_N98,
17321 
      I3 => huffman_ins_v2_mux_code_white_width(1),
17322 
      O => huffman_ins_v2_hor_code_13_mux000325_1857
17323 
    );
17324 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_mux00021 : LUT3
17325 
    generic map(
17326 
      INIT => X"80"
17327 
    )
17328 
    port map (
17329 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
17330 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
17331 
      I2 => fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt_cmp_ge0000,
17332 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_overflow_o_mux0002
17333 
    );
17334 
  huffman_ins_v2_hor_code_18_mux0003211 : LUT4
17335 
    generic map(
17336 
      INIT => X"0213"
17337 
    )
17338 
    port map (
17339 
      I0 => huffman_ins_v2_a0_value_2_1510,
17340 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17341 
      I2 => huffman_ins_v2_code_white_width(3),
17342 
      I3 => huffman_ins_v2_code_black_width(3),
17343 
      O => huffman_ins_v2_N246
17344 
    );
17345 
  huffman_ins_v2_hor_code_15_mux000378 : LUT4
17346 
    generic map(
17347 
      INIT => X"1000"
17348 
    )
17349 
    port map (
17350 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
17351 
      I1 => huffman_ins_v2_N98,
17352 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
17353 
      I3 => huffman_ins_v2_mux_code_white_width(1),
17354 
      O => huffman_ins_v2_hor_code_15_mux000378_1892
17355 
    );
17356 
  huffman_ins_v2_hor_code_15_mux000380 : LUT4
17357 
    generic map(
17358 
      INIT => X"FF4C"
17359 
    )
17360 
    port map (
17361 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17362 
      I1 => huffman_ins_v2_hor_code_15_mux000355,
17363 
      I2 => huffman_ins_v2_N59,
17364 
      I3 => huffman_ins_v2_hor_code_15_mux000378_1892,
17365 
      O => huffman_ins_v2_hor_code_15_mux000380_1894
17366 
    );
17367 
  huffman_ins_v2_hor_code_24_mux000335 : LUT4
17368 
    generic map(
17369 
      INIT => X"AF9F"
17370 
    )
17371 
    port map (
17372 
      I0 => huffman_ins_v2_mux_code_black_width(2),
17373 
      I1 => huffman_ins_v2_mux_code_black_width(1),
17374 
      I2 => huffman_ins_v2_hor_code_23_and0000,
17375 
      I3 => huffman_ins_v2_mux_code_black_width(0),
17376 
      O => huffman_ins_v2_hor_code_24_mux000335_1975
17377 
    );
17378 
  huffman_ins_v2_hor_code_18_mux0003164 : LUT4
17379 
    generic map(
17380 
      INIT => X"2A08"
17381 
    )
17382 
    port map (
17383 
      I0 => huffman_ins_v2_N95,
17384 
      I1 => huffman_ins_v2_mux_code_black_width(3),
17385 
      I2 => huffman_ins_v2_N99,
17386 
      I3 => N345,
17387 
      O => huffman_ins_v2_hor_code_18_mux0003164_1917
17388 
    );
17389 
  huffman_ins_v2_hor_code_14_mux0003155 : LUT4
17390 
    generic map(
17391 
      INIT => X"9908"
17392 
    )
17393 
    port map (
17394 
      I0 => huffman_ins_v2_a0_value_2_1510,
17395 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
17396 
      I2 => huffman_ins_v2_code_black_width(0),
17397 
      I3 => huffman_ins_v2_N203,
17398 
      O => huffman_ins_v2_hor_code_14_mux0003155_1868
17399 
    );
17400 
  huffman_ins_v2_hor_code_14_mux0003173 : LUT4
17401 
    generic map(
17402 
      INIT => X"6604"
17403 
    )
17404 
    port map (
17405 
      I0 => huffman_ins_v2_a0_value_2_1510,
17406 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
17407 
      I2 => huffman_ins_v2_code_white_width(0),
17408 
      I3 => huffman_ins_v2_N223,
17409 
      O => huffman_ins_v2_hor_code_14_mux0003173_1869
17410 
    );
17411 
  huffman_ins_v2_hor_code_16_mux000393 : LUT4
17412 
    generic map(
17413 
      INIT => X"6240"
17414 
    )
17415 
    port map (
17416 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
17417 
      I1 => huffman_ins_v2_a0_value_2_1510,
17418 
      I2 => huffman_ins_v2_N14,
17419 
      I3 => huffman_ins_v2_N34,
17420 
      O => huffman_ins_v2_hor_code_16_mux000393_1901
17421 
    );
17422 
  huffman_ins_v2_hor_code_6_mux000343 : LUT4
17423 
    generic map(
17424 
      INIT => X"6240"
17425 
    )
17426 
    port map (
17427 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
17428 
      I1 => huffman_ins_v2_a0_value_2_1510,
17429 
      I2 => huffman_ins_v2_N39,
17430 
      I3 => huffman_ins_v2_N55,
17431 
      O => huffman_ins_v2_hor_code_6_mux000343_2017
17432 
    );
17433 
  huffman_ins_v2_hor_code_16_mux0003117 : LUT4
17434 
    generic map(
17435 
      INIT => X"9810"
17436 
    )
17437 
    port map (
17438 
      I0 => huffman_ins_v2_a0_value_2_1510,
17439 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
17440 
      I2 => huffman_ins_v2_N14,
17441 
      I3 => huffman_ins_v2_N34,
17442 
      O => huffman_ins_v2_hor_code_16_mux0003117_1897
17443 
    );
17444 
  huffman_ins_v2_hor_code_10_mux000329_SW0 : LUT4
17445 
    generic map(
17446 
      INIT => X"15FF"
17447 
    )
17448 
    port map (
17449 
      I0 => huffman_ins_v2_mux_code_black_width(2),
17450 
      I1 => huffman_ins_v2_mux_code_black_width(1),
17451 
      I2 => huffman_ins_v2_mux_code_black_width(0),
17452 
      I3 => huffman_ins_v2_mux_code_black_width(3),
17453 
      O => N349
17454 
    );
17455 
  huffman_ins_v2_hor_code_10_mux000329 : LUT4
17456 
    generic map(
17457 
      INIT => X"FFEA"
17458 
    )
17459 
    port map (
17460 
      I0 => huffman_ins_v2_N166,
17461 
      I1 => huffman_ins_v2_N110,
17462 
      I2 => N349,
17463 
      I3 => huffman_ins_v2_N100,
17464 
      O => huffman_ins_v2_hor_code_10_mux000329_1823
17465 
    );
17466 
  huffman_ins_v2_hor_code_2_mux000379_SW0 : LUT4
17467 
    generic map(
17468 
      INIT => X"020A"
17469 
    )
17470 
    port map (
17471 
      I0 => huffman_ins_v2_N110,
17472 
      I1 => huffman_ins_v2_mux_code_black_width(1),
17473 
      I2 => huffman_ins_v2_mux_code_black_width(3),
17474 
      I3 => huffman_ins_v2_mux_code_black_width(0),
17475 
      O => N351
17476 
    );
17477 
  huffman_ins_v2_hor_code_2_mux000379 : LUT4
17478 
    generic map(
17479 
      INIT => X"F020"
17480 
    )
17481 
    port map (
17482 
      I0 => N351,
17483 
      I1 => huffman_ins_v2_mux_code_black_width(2),
17484 
      I2 => huffman_ins_v2_hor_code(2),
17485 
      I3 => huffman_ins_v2_N166,
17486 
      O => huffman_ins_v2_hor_code_2_mux000379_1988
17487 
    );
17488 
  fax4_ins_mux_a0_and00011_SW0 : LUT4
17489 
    generic map(
17490 
      INIT => X"F8FF"
17491 
    )
17492 
    port map (
17493 
      I0 => fax4_ins_pix_changed_1319,
17494 
      I1 => fax4_ins_state_FSM_FFd8_1338,
17495 
      I2 => fax4_ins_mux_a0_0_Q,
17496 
      I3 => N491,
17497 
      O => N144
17498 
    );
17499 
  fax4_ins_FIFO2_multi_read_ins_latch2_or00001 : LUT4
17500 
    generic map(
17501 
      INIT => X"EAAA"
17502 
    )
17503 
    port map (
17504 
      I0 => fax4_ins_fifo2_rd,
17505 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(0),
17506 
      I2 => fax4_ins_fifo2_wr,
17507 
      I3 => fax4_ins_FIFO2_multi_read_ins_N7,
17508 
      O => fax4_ins_FIFO2_multi_read_ins_latch2
17509 
    );
17510 
  fax4_ins_FIFO2_multi_read_ins_latch1_or00001 : LUT4
17511 
    generic map(
17512 
      INIT => X"AEAA"
17513 
    )
17514 
    port map (
17515 
      I0 => fax4_ins_fifo2_rd,
17516 
      I1 => fax4_ins_FIFO2_multi_read_ins_N7,
17517 
      I2 => fax4_ins_FIFO2_multi_read_ins_used(0),
17518 
      I3 => fax4_ins_fifo2_wr,
17519 
      O => fax4_ins_FIFO2_multi_read_ins_latch1
17520 
    );
17521 
  fax4_ins_FIFO1_multi_read_ins_latch2_or00001 : LUT4
17522 
    generic map(
17523 
      INIT => X"EAAA"
17524 
    )
17525 
    port map (
17526 
      I0 => fax4_ins_fifo1_rd,
17527 
      I1 => fax4_ins_FIFO1_multi_read_ins_used(0),
17528 
      I2 => fax4_ins_fifo1_wr,
17529 
      I3 => fax4_ins_FIFO1_multi_read_ins_N7,
17530 
      O => fax4_ins_FIFO1_multi_read_ins_latch2
17531 
    );
17532 
  fax4_ins_FIFO1_multi_read_ins_latch1_or00001 : LUT4
17533 
    generic map(
17534 
      INIT => X"AEAA"
17535 
    )
17536 
    port map (
17537 
      I0 => fax4_ins_fifo1_rd,
17538 
      I1 => fax4_ins_FIFO1_multi_read_ins_N7,
17539 
      I2 => fax4_ins_FIFO1_multi_read_ins_used(0),
17540 
      I3 => fax4_ins_fifo1_wr,
17541 
      O => fax4_ins_FIFO1_multi_read_ins_latch1
17542 
    );
17543 
  huffman_ins_v2_code_white_6_mux000014_SW0 : LUT3
17544 
    generic map(
17545 
      INIT => X"EA"
17546 
    )
17547 
    port map (
17548 
      I0 => huffman_ins_v2_code_white_6_mux00004_1778,
17549 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(1),
17550 
      I2 => huffman_ins_v2_code_white_8_cmp_eq0001,
17551 
      O => N355
17552 
    );
17553 
  huffman_ins_v2_code_white_6_mux000014 : LUT4
17554 
    generic map(
17555 
      INIT => X"AEAA"
17556 
    )
17557 
    port map (
17558 
      I0 => N355,
17559 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(0),
17560 
      I2 => huffman_ins_v2_codetab_ter_white_width(0),
17561 
      I3 => huffman_ins_v2_N239,
17562 
      O => huffman_ins_v2_code_white_6_mux000014_1776
17563 
    );
17564 
  huffman_ins_v2_hor_code_13_mux0003137 : LUT4
17565 
    generic map(
17566 
      INIT => X"A820"
17567 
    )
17568 
    port map (
17569 
      I0 => N359,
17570 
      I1 => huffman_ins_v2_a0_value_2_1510,
17571 
      I2 => huffman_ins_v2_code_black(13),
17572 
      I3 => huffman_ins_v2_code_white(13),
17573 
      O => huffman_ins_v2_hor_code_13_mux0003137_1852
17574 
    );
17575 
  huffman_ins_v2_code_white_14_mux0000141 : LUT4
17576 
    generic map(
17577 
      INIT => X"A820"
17578 
    )
17579 
    port map (
17580 
      I0 => huffman_ins_v2_N239,
17581 
      I1 => huffman_ins_v2_codetab_ter_white_width(0),
17582 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(8),
17583 
      I3 => huffman_ins_v2_code_table_ins_makeup_white(7),
17584 
      O => huffman_ins_v2_code_white_14_mux000014
17585 
    );
17586 
  huffman_ins_v2_hor_code_13_mux0003137_SW0 : LUT4
17587 
    generic map(
17588 
      INIT => X"42AA"
17589 
    )
17590 
    port map (
17591 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
17592 
      I1 => huffman_ins_v2_mux_code_white_width(1),
17593 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17594 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17595 
      O => N359
17596 
    );
17597 
  huffman_ins_v2_hor_code_16_mux000332_SW0 : LUT4
17598 
    generic map(
17599 
      INIT => X"A820"
17600 
    )
17601 
    port map (
17602 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17603 
      I1 => huffman_ins_v2_a0_value_2_1510,
17604 
      I2 => huffman_ins_v2_code_black_width(3),
17605 
      I3 => huffman_ins_v2_code_white_width(3),
17606 
      O => N361
17607 
    );
17608 
  huffman_ins_v2_hor_code_5_mux000311 : LUT4
17609 
    generic map(
17610 
      INIT => X"6E7F"
17611 
    )
17612 
    port map (
17613 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17614 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
17615 
      I2 => huffman_ins_v2_N59,
17616 
      I3 => huffman_ins_v2_hor_code_13_or0005,
17617 
      O => huffman_ins_v2_N39
17618 
    );
17619 
  fax4_ins_state_FSM_FFd6_In221 : LUT4
17620 
    generic map(
17621 
      INIT => X"FF01"
17622 
    )
17623 
    port map (
17624 
      I0 => fax4_ins_EOL,
17625 
      I1 => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(9),
17626 
      I2 => fax4_ins_state_FSM_FFd8_1338,
17627 
      I3 => fax4_ins_pix_changed_1319,
17628 
      O => fax4_ins_N53
17629 
    );
17630 
  huffman_ins_v2_hor_code_10_mux000363 : LUT3
17631 
    generic map(
17632 
      INIT => X"01"
17633 
    )
17634 
    port map (
17635 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
17636 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
17637 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17638 
      O => huffman_ins_v2_N100
17639 
    );
17640 
  huffman_ins_v2_hor_code_7_mux000325 : LUT4
17641 
    generic map(
17642 
      INIT => X"70A0"
17643 
    )
17644 
    port map (
17645 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17646 
      I1 => huffman_ins_v2_N59,
17647 
      I2 => huffman_ins_v2_hor_code_7_mux000324_2022,
17648 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
17649 
      O => huffman_ins_v2_hor_code_7_mux000325_2023
17650 
    );
17651 
  fax4_ins_b1_mux0004_9_41_SW1 : LUT4
17652 
    generic map(
17653 
      INIT => X"AB01"
17654 
    )
17655 
    port map (
17656 
      I0 => fax4_ins_mux_b1(1),
17657 
      I1 => fax4_ins_mux_b1(2),
17658 
      I2 => fax4_ins_mux_b1(3),
17659 
      I3 => fax4_ins_fifo_out_prev1_x(9),
17660 
      O => N363
17661 
    );
17662 
  fax4_ins_b1_mux0004_9_41 : LUT4
17663 
    generic map(
17664 
      INIT => X"FE54"
17665 
    )
17666 
    port map (
17667 
      I0 => fax4_ins_mux_b1(0),
17668 
      I1 => fax4_ins_b1_mux0004_9_18_1053,
17669 
      I2 => N363,
17670 
      I3 => fax4_ins_fifo_out_prev2_x(9),
17671 
      O => fax4_ins_b1_mux0004(9)
17672 
    );
17673 
  fax4_ins_b1_mux0004_7_41_SW1 : LUT4
17674 
    generic map(
17675 
      INIT => X"AB01"
17676 
    )
17677 
    port map (
17678 
      I0 => fax4_ins_mux_b1(1),
17679 
      I1 => fax4_ins_mux_b1(2),
17680 
      I2 => fax4_ins_mux_b1(3),
17681 
      I3 => fax4_ins_fifo_out_prev1_x(7),
17682 
      O => N365
17683 
    );
17684 
  fax4_ins_b1_mux0004_7_41 : LUT4
17685 
    generic map(
17686 
      INIT => X"FE54"
17687 
    )
17688 
    port map (
17689 
      I0 => fax4_ins_mux_b1(0),
17690 
      I1 => fax4_ins_b1_mux0004_7_18_1047,
17691 
      I2 => N365,
17692 
      I3 => fax4_ins_fifo_out_prev2_x(7),
17693 
      O => fax4_ins_b1_mux0004(7)
17694 
    );
17695 
  fax4_ins_b1_mux0004_6_41_SW1 : LUT4
17696 
    generic map(
17697 
      INIT => X"AB01"
17698 
    )
17699 
    port map (
17700 
      I0 => fax4_ins_mux_b1(1),
17701 
      I1 => fax4_ins_mux_b1(2),
17702 
      I2 => fax4_ins_mux_b1(3),
17703 
      I3 => fax4_ins_fifo_out_prev1_x(6),
17704 
      O => N367
17705 
    );
17706 
  fax4_ins_b1_mux0004_6_41 : LUT4
17707 
    generic map(
17708 
      INIT => X"FE54"
17709 
    )
17710 
    port map (
17711 
      I0 => fax4_ins_mux_b1(0),
17712 
      I1 => fax4_ins_b1_mux0004_6_18_1045,
17713 
      I2 => N367,
17714 
      I3 => fax4_ins_fifo_out_prev2_x(6),
17715 
      O => fax4_ins_b1_mux0004(6)
17716 
    );
17717 
  fax4_ins_b1_mux0004_5_41_SW1 : LUT4
17718 
    generic map(
17719 
      INIT => X"AB01"
17720 
    )
17721 
    port map (
17722 
      I0 => fax4_ins_mux_b1(1),
17723 
      I1 => fax4_ins_mux_b1(2),
17724 
      I2 => fax4_ins_mux_b1(3),
17725 
      I3 => fax4_ins_fifo_out_prev1_x(5),
17726 
      O => N369
17727 
    );
17728 
  fax4_ins_b1_mux0004_5_41 : LUT4
17729 
    generic map(
17730 
      INIT => X"FE54"
17731 
    )
17732 
    port map (
17733 
      I0 => fax4_ins_mux_b1(0),
17734 
      I1 => fax4_ins_b1_mux0004_5_18_1043,
17735 
      I2 => N369,
17736 
      I3 => fax4_ins_fifo_out_prev2_x(5),
17737 
      O => fax4_ins_b1_mux0004(5)
17738 
    );
17739 
  fax4_ins_b1_mux0004_4_41_SW1 : LUT4
17740 
    generic map(
17741 
      INIT => X"AB01"
17742 
    )
17743 
    port map (
17744 
      I0 => fax4_ins_mux_b1(1),
17745 
      I1 => fax4_ins_mux_b1(2),
17746 
      I2 => fax4_ins_mux_b1(3),
17747 
      I3 => fax4_ins_fifo_out_prev1_x(4),
17748 
      O => N371
17749 
    );
17750 
  fax4_ins_b1_mux0004_4_41 : LUT4
17751 
    generic map(
17752 
      INIT => X"FE54"
17753 
    )
17754 
    port map (
17755 
      I0 => fax4_ins_mux_b1(0),
17756 
      I1 => fax4_ins_b1_mux0004_4_18_1041,
17757 
      I2 => N371,
17758 
      I3 => fax4_ins_fifo_out_prev2_x(4),
17759 
      O => fax4_ins_b1_mux0004(4)
17760 
    );
17761 
  fax4_ins_b1_mux0004_0_41_SW1 : LUT4
17762 
    generic map(
17763 
      INIT => X"AB01"
17764 
    )
17765 
    port map (
17766 
      I0 => fax4_ins_mux_b1(1),
17767 
      I1 => fax4_ins_mux_b1(2),
17768 
      I2 => fax4_ins_mux_b1(3),
17769 
      I3 => fax4_ins_fifo_out_prev1_x(0),
17770 
      O => N373
17771 
    );
17772 
  fax4_ins_b1_mux0004_0_41 : LUT4
17773 
    generic map(
17774 
      INIT => X"FE54"
17775 
    )
17776 
    port map (
17777 
      I0 => fax4_ins_mux_b1(0),
17778 
      I1 => fax4_ins_b1_mux0004_0_18_1027,
17779 
      I2 => N373,
17780 
      I3 => fax4_ins_fifo_out_prev2_x(0),
17781 
      O => fax4_ins_b1_mux0004(0)
17782 
    );
17783 
  huffman_ins_v2_hor_code_20_mux00030 : LUT4
17784 
    generic map(
17785 
      INIT => X"217B"
17786 
    )
17787 
    port map (
17788 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
17789 
      I1 => huffman_ins_v2_code_black_width(4),
17790 
      I2 => huffman_ins_v2_a0_value_2_1510,
17791 
      I3 => huffman_ins_v2_code_white_width(4),
17792 
      O => huffman_ins_v2_hor_code_20_mux00030_1938
17793 
    );
17794 
  huffman_ins_v2_hor_code_20_mux0003111 : LUT4
17795 
    generic map(
17796 
      INIT => X"1018"
17797 
    )
17798 
    port map (
17799 
      I0 => huffman_ins_v2_mux_code_black_width(1),
17800 
      I1 => huffman_ins_v2_mux_code_black_width(2),
17801 
      I2 => huffman_ins_v2_mux_code_black_width(3),
17802 
      I3 => huffman_ins_v2_mux_code_black_width(0),
17803 
      O => huffman_ins_v2_N169
17804 
    );
17805 
  huffman_ins_v2_hor_code_21_mux000310 : LUT4
17806 
    generic map(
17807 
      INIT => X"0280"
17808 
    )
17809 
    port map (
17810 
      I0 => huffman_ins_v2_N95,
17811 
      I1 => huffman_ins_v2_mux_code_black_width(1),
17812 
      I2 => huffman_ins_v2_mux_code_black_width(2),
17813 
      I3 => huffman_ins_v2_mux_code_black_width(3),
17814 
      O => huffman_ins_v2_hor_code_21_mux000310_1949
17815 
    );
17816 
  huffman_ins_v2_hor_code_19_mux000380_SW0_SW0 : LUT4
17817 
    generic map(
17818 
      INIT => X"2028"
17819 
    )
17820 
    port map (
17821 
      I0 => huffman_ins_v2_N103,
17822 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17823 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17824 
      I3 => huffman_ins_v2_mux_code_white_width(1),
17825 
      O => N375
17826 
    );
17827 
  huffman_ins_v2_hor_code_19_mux000380_SW0 : LUT4
17828 
    generic map(
17829 
      INIT => X"FF4C"
17830 
    )
17831 
    port map (
17832 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
17833 
      I1 => N375,
17834 
      I2 => huffman_ins_v2_N246,
17835 
      I3 => huffman_ins_v2_hor_code_19_mux000323_1926,
17836 
      O => N337
17837 
    );
17838 
  fax4_ins_mode_indicator_o_mux0001_2_322_SW0_SW0 : LUT4
17839 
    generic map(
17840 
      INIT => X"F3F1"
17841 
    )
17842 
    port map (
17843 
      I0 => fax4_ins_EOL,
17844 
      I1 => fax4_ins_pix_changed_1319,
17845 
      I2 => fax4_ins_state_FSM_FFd8_1338,
17846 
      I3 => fax4_ins_EOL_prev_230,
17847 
      O => N174
17848 
    );
17849 
  fax4_ins_fifo1_wr1 : LUT4
17850 
    generic map(
17851 
      INIT => X"2000"
17852 
    )
17853 
    port map (
17854 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
17855 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
17856 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
17857 
      I3 => fax4_ins_pix_changed_1319,
17858 
      O => fax4_ins_fifo1_wr
17859 
    );
17860 
  fax4_ins_load_a1_and00001 : LUT4
17861 
    generic map(
17862 
      INIT => X"F020"
17863 
    )
17864 
    port map (
17865 
      I0 => fax4_ins_EOL,
17866 
      I1 => fax4_ins_EOL_prev_230,
17867 
      I2 => fax4_ins_load_a1_or0000,
17868 
      I3 => fax4_ins_pix_changed_1319,
17869 
      O => fax4_ins_load_a0
17870 
    );
17871 
  huffman_ins_v2_N1701 : LUT3
17872 
    generic map(
17873 
      INIT => X"1F"
17874 
    )
17875 
    port map (
17876 
      I0 => huffman_ins_v2_mux_code_white_width(1),
17877 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
17878 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17879 
      O => huffman_ins_v2_N170
17880 
    );
17881 
  huffman_ins_v2_hor_code_5_mux000381 : LUT3
17882 
    generic map(
17883 
      INIT => X"08"
17884 
    )
17885 
    port map (
17886 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17887 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
17888 
      I2 => huffman_ins_v2_mux_code_white_width(1),
17889 
      O => huffman_ins_v2_hor_code_13_cmp_eq0000
17890 
    );
17891 
  huffman_ins_v2_hor_code_11_mux000312 : LUT4
17892 
    generic map(
17893 
      INIT => X"4A6A"
17894 
    )
17895 
    port map (
17896 
      I0 => huffman_ins_v2_mux_code_black_width(4),
17897 
      I1 => huffman_ins_v2_mux_code_black_width(2),
17898 
      I2 => huffman_ins_v2_mux_code_black_width(3),
17899 
      I3 => huffman_ins_v2_mux_code_black_width(1),
17900 
      O => huffman_ins_v2_N62
17901 
    );
17902 
  huffman_ins_v2_hor_code_6_mux000321 : LUT3
17903 
    generic map(
17904 
      INIT => X"7F"
17905 
    )
17906 
    port map (
17907 
      I0 => huffman_ins_v2_mux_code_black_width(0),
17908 
      I1 => huffman_ins_v2_mux_code_black_width(1),
17909 
      I2 => huffman_ins_v2_mux_code_black_width(2),
17910 
      O => huffman_ins_v2_N67
17911 
    );
17912 
  huffman_ins_v2_hor_code_24_mux000361 : LUT4
17913 
    generic map(
17914 
      INIT => X"1000"
17915 
    )
17916 
    port map (
17917 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17918 
      I1 => huffman_ins_v2_mux_code_white_width(1),
17919 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17920 
      I3 => huffman_ins_v2_N102,
17921 
      O => huffman_ins_v2_N244
17922 
    );
17923 
  huffman_ins_v2_hor_code_10_mux000372 : LUT3
17924 
    generic map(
17925 
      INIT => X"10"
17926 
    )
17927 
    port map (
17928 
      I0 => huffman_ins_v2_mux_code_black_width(4),
17929 
      I1 => huffman_ins_v2_mux_code_black_width(3),
17930 
      I2 => huffman_ins_v2_horizontal_mode_part_2_2065,
17931 
      O => huffman_ins_v2_N105
17932 
    );
17933 
  huffman_ins_v2_hor_code_18_mux000381_SW0 : LUT4
17934 
    generic map(
17935 
      INIT => X"777F"
17936 
    )
17937 
    port map (
17938 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17939 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17940 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
17941 
      I3 => huffman_ins_v2_mux_code_white_width(1),
17942 
      O => N305
17943 
    );
17944 
  huffman_ins_v2_hor_code_16_mux000311 : LUT4
17945 
    generic map(
17946 
      INIT => X"5756"
17947 
    )
17948 
    port map (
17949 
      I0 => huffman_ins_v2_mux_code_black_width(3),
17950 
      I1 => huffman_ins_v2_mux_code_black_width(1),
17951 
      I2 => huffman_ins_v2_mux_code_black_width(2),
17952 
      I3 => huffman_ins_v2_mux_code_black_width(0),
17953 
      O => huffman_ins_v2_N34
17954 
    );
17955 
  huffman_ins_v2_hor_code_20_mux000350 : LUT4
17956 
    generic map(
17957 
      INIT => X"8891"
17958 
    )
17959 
    port map (
17960 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17961 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17962 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
17963 
      I3 => huffman_ins_v2_mux_code_white_width(1),
17964 
      O => huffman_ins_v2_hor_code_20_mux000350_1946
17965 
    );
17966 
  huffman_ins_v2_hor_code_17_mux0003811 : LUT3
17967 
    generic map(
17968 
      INIT => X"10"
17969 
    )
17970 
    port map (
17971 
      I0 => huffman_ins_v2_a0_value_2_1510,
17972 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
17973 
      I2 => huffman_ins_v2_code_black_width(4),
17974 
      O => huffman_ins_v2_N245
17975 
    );
17976 
  huffman_ins_v2_hor_code_18_mux0003164_SW0 : LUT4
17977 
    generic map(
17978 
      INIT => X"EAE2"
17979 
    )
17980 
    port map (
17981 
      I0 => huffman_ins_v2_mux_code_black_width(2),
17982 
      I1 => huffman_ins_v2_code_black_width(1),
17983 
      I2 => huffman_ins_v2_mux_code_black_width(0),
17984 
      I3 => huffman_ins_v2_mux_code_black_width(1),
17985 
      O => N345
17986 
    );
17987 
  huffman_ins_v2_hor_code_10_mux000312 : LUT4
17988 
    generic map(
17989 
      INIT => X"5A6A"
17990 
    )
17991 
    port map (
17992 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
17993 
      I1 => huffman_ins_v2_mux_code_white_width(1),
17994 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
17995 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
17996 
      O => huffman_ins_v2_N38
17997 
    );
17998 
  huffman_ins_v2_hor_code_2_mux000335_SW0 : LUT4
17999 
    generic map(
18000 
      INIT => X"FFE2"
18001 
    )
18002 
    port map (
18003 
      I0 => huffman_ins_v2_code_black_width(1),
18004 
      I1 => huffman_ins_v2_a0_value_2_1510,
18005 
      I2 => huffman_ins_v2_code_white_width(1),
18006 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
18007 
      O => N377
18008 
    );
18009 
  huffman_ins_v2_hor_code_2_mux000335 : LUT4
18010 
    generic map(
18011 
      INIT => X"70E0"
18012 
    )
18013 
    port map (
18014 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
18015 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
18016 
      I2 => huffman_ins_v2_hor_code_2_mux000330_1986,
18017 
      I3 => N377,
18018 
      O => huffman_ins_v2_hor_code_2_mux000335_1987
18019 
    );
18020 
  huffman_ins_v2_hor_code_6_mux000311 : LUT4
18021 
    generic map(
18022 
      INIT => X"6E7F"
18023 
    )
18024 
    port map (
18025 
      I0 => huffman_ins_v2_mux_code_black_width(3),
18026 
      I1 => huffman_ins_v2_mux_code_black_width(4),
18027 
      I2 => huffman_ins_v2_N99,
18028 
      I3 => huffman_ins_v2_N67,
18029 
      O => huffman_ins_v2_N55
18030 
    );
18031 
  huffman_ins_v2_hor_code_21_mux000335 : LUT4
18032 
    generic map(
18033 
      INIT => X"1000"
18034 
    )
18035 
    port map (
18036 
      I0 => huffman_ins_v2_a0_value_2_1510,
18037 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
18038 
      I2 => huffman_ins_v2_code_black_width(4),
18039 
      I3 => huffman_ins_v2_hor_code_21_mux000334_1953,
18040 
      O => huffman_ins_v2_hor_code_21_mux000335_1954
18041 
    );
18042 
  huffman_ins_v2_hor_code_5_mux000331 : LUT4
18043 
    generic map(
18044 
      INIT => X"1FBF"
18045 
    )
18046 
    port map (
18047 
      I0 => huffman_ins_v2_a0_value_2_1510,
18048 
      I1 => huffman_ins_v2_code_black_width(0),
18049 
      I2 => huffman_ins_v2_mux_code_white_width(1),
18050 
      I3 => huffman_ins_v2_code_white_width(0),
18051 
      O => huffman_ins_v2_N70
18052 
    );
18053 
  huffman_ins_v2_hor_code_4_mux00033 : LUT4
18054 
    generic map(
18055 
      INIT => X"0010"
18056 
    )
18057 
    port map (
18058 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
18059 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
18060 
      I2 => huffman_ins_v2_N109,
18061 
      I3 => huffman_ins_v2_mux_code_white_width(1),
18062 
      O => huffman_ins_v2_hor_code_4_mux00033_1999
18063 
    );
18064 
  huffman_ins_v2_hor_code_13_or00051 : LUT4
18065 
    generic map(
18066 
      INIT => X"1FBF"
18067 
    )
18068 
    port map (
18069 
      I0 => huffman_ins_v2_a0_value_2_1510,
18070 
      I1 => huffman_ins_v2_code_black_width(2),
18071 
      I2 => huffman_ins_v2_mux_code_white_width(1),
18072 
      I3 => huffman_ins_v2_code_white_width(2),
18073 
      O => huffman_ins_v2_hor_code_13_or0005
18074 
    );
18075 
  huffman_ins_v2_hor_code_20_mux0003121 : LUT4
18076 
    generic map(
18077 
      INIT => X"A820"
18078 
    )
18079 
    port map (
18080 
      I0 => huffman_ins_v2_mux_code_black_width(0),
18081 
      I1 => huffman_ins_v2_a0_value_2_1510,
18082 
      I2 => huffman_ins_v2_code_white_width(2),
18083 
      I3 => huffman_ins_v2_code_black_width(2),
18084 
      O => huffman_ins_v2_N250
18085 
    );
18086 
  huffman_ins_v2_hor_code_22_mux000320 : LUT4
18087 
    generic map(
18088 
      INIT => X"1000"
18089 
    )
18090 
    port map (
18091 
      I0 => huffman_ins_v2_N59,
18092 
      I1 => huffman_ins_v2_a0_value_2_1510,
18093 
      I2 => huffman_ins_v2_code_black_width(3),
18094 
      I3 => huffman_ins_v2_N102,
18095 
      O => huffman_ins_v2_hor_code_22_mux000320_1962
18096 
    );
18097 
  huffman_ins_v2_hor_code_23_and00001 : LUT4
18098 
    generic map(
18099 
      INIT => X"A820"
18100 
    )
18101 
    port map (
18102 
      I0 => huffman_ins_v2_mux_code_black_width(3),
18103 
      I1 => huffman_ins_v2_a0_value_2_1510,
18104 
      I2 => huffman_ins_v2_code_white_width(4),
18105 
      I3 => huffman_ins_v2_code_black_width(4),
18106 
      O => huffman_ins_v2_hor_code_23_and0000
18107 
    );
18108 
  fax4_ins_mux_b1_2_and000032_SW0 : LUT4
18109 
    generic map(
18110 
      INIT => X"8F0F"
18111 
    )
18112 
    port map (
18113 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
18114 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
18115 
      I2 => fax4_ins_mux_b1_2_and000019_1310,
18116 
      I3 => fax4_ins_Mcompar_mux_b1_2_cmp_gt0000_cy(9),
18117 
      O => N381
18118 
    );
18119 
  fax4_ins_state_FSM_FFd10_In21 : LUT3
18120 
    generic map(
18121 
      INIT => X"EA"
18122 
    )
18123 
    port map (
18124 
      I0 => fax4_ins_EOL_prev_230,
18125 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
18126 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
18127 
      O => fax4_ins_state_FSM_N7
18128 
    );
18129 
  fax4_ins_load_a1_or00011 : LUT4
18130 
    generic map(
18131 
      INIT => X"FF15"
18132 
    )
18133 
    port map (
18134 
      I0 => fax4_ins_EOL_prev_230,
18135 
      I1 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
18136 
      I2 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
18137 
      I3 => fax4_ins_pix_changed_1319,
18138 
      O => fax4_ins_load_a1_or0001
18139 
    );
18140 
  huffman_ins_v2_hor_code_7_mux000311 : LUT4
18141 
    generic map(
18142 
      INIT => X"57AA"
18143 
    )
18144 
    port map (
18145 
      I0 => huffman_ins_v2_mux_code_black_width(3),
18146 
      I1 => huffman_ins_v2_mux_code_black_width(1),
18147 
      I2 => huffman_ins_v2_mux_code_black_width(2),
18148 
      I3 => huffman_ins_v2_mux_code_black_width(4),
18149 
      O => huffman_ins_v2_N48
18150 
    );
18151 
  huffman_ins_v2_hor_code_10_mux0003114 : LUT4
18152 
    generic map(
18153 
      INIT => X"028A"
18154 
    )
18155 
    port map (
18156 
      I0 => huffman_ins_v2_horizontal_mode_part_2_2065,
18157 
      I1 => huffman_ins_v2_a0_value_2_1510,
18158 
      I2 => huffman_ins_v2_code_white_width(4),
18159 
      I3 => huffman_ins_v2_code_black_width(4),
18160 
      O => huffman_ins_v2_N110
18161 
    );
18162 
  huffman_ins_v2_hor_code_10_mux0003103 : LUT4
18163 
    generic map(
18164 
      INIT => X"0213"
18165 
    )
18166 
    port map (
18167 
      I0 => huffman_ins_v2_a0_value_2_1510,
18168 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
18169 
      I2 => huffman_ins_v2_code_white_width(4),
18170 
      I3 => huffman_ins_v2_code_black_width(4),
18171 
      O => huffman_ins_v2_N109
18172 
    );
18173 
  huffman_ins_v2_hor_code_12_mux000321 : LUT3
18174 
    generic map(
18175 
      INIT => X"1F"
18176 
    )
18177 
    port map (
18178 
      I0 => huffman_ins_v2_mux_code_white_width(1),
18179 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
18180 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
18181 
      O => huffman_ins_v2_N14
18182 
    );
18183 
  huffman_ins_v2_hor_code_3_mux000311 : LUT4
18184 
    generic map(
18185 
      INIT => X"57FA"
18186 
    )
18187 
    port map (
18188 
      I0 => huffman_ins_v2_mux_code_black_width(4),
18189 
      I1 => huffman_ins_v2_mux_code_black_width(1),
18190 
      I2 => huffman_ins_v2_mux_code_black_width(2),
18191 
      I3 => huffman_ins_v2_mux_code_black_width(3),
18192 
      O => huffman_ins_v2_N52
18193 
    );
18194 
  huffman_ins_v2_hor_code_8_mux000321 : LUT4
18195 
    generic map(
18196 
      INIT => X"57AA"
18197 
    )
18198 
    port map (
18199 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
18200 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
18201 
      I2 => huffman_ins_v2_mux_code_white_width(1),
18202 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
18203 
      O => huffman_ins_v2_N51
18204 
    );
18205 
  huffman_ins_v2_hor_code_4_mux000311 : LUT4
18206 
    generic map(
18207 
      INIT => X"57FA"
18208 
    )
18209 
    port map (
18210 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
18211 
      I1 => huffman_ins_v2_mux_code_white_width(1),
18212 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
18213 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
18214 
      O => huffman_ins_v2_N40
18215 
    );
18216 
  huffman_ins_v2_hor_code_12_mux000341 : LUT4
18217 
    generic map(
18218 
      INIT => X"4A6A"
18219 
    )
18220 
    port map (
18221 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
18222 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
18223 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
18224 
      I3 => huffman_ins_v2_mux_code_white_width(1),
18225 
      O => huffman_ins_v2_N44
18226 
    );
18227 
  huffman_ins_v2_Madd_hor_code_width_addsub0000_cy_1_11 : LUT4
18228 
    generic map(
18229 
      INIT => X"FFE2"
18230 
    )
18231 
    port map (
18232 
      I0 => huffman_ins_v2_code_black_width(1),
18233 
      I1 => huffman_ins_v2_a0_value_2_1510,
18234 
      I2 => huffman_ins_v2_code_white_width(1),
18235 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
18236 
      O => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(1)
18237 
    );
18238 
  huffman_ins_v2_hor_code_13_mux0003411 : LUT4
18239 
    generic map(
18240 
      INIT => X"1FBF"
18241 
    )
18242 
    port map (
18243 
      I0 => huffman_ins_v2_a0_value_2_1510,
18244 
      I1 => huffman_ins_v2_code_black_width(2),
18245 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
18246 
      I3 => huffman_ins_v2_code_white_width(2),
18247 
      O => huffman_ins_v2_N98
18248 
    );
18249 
  huffman_ins_v2_hor_code_5_mux000341 : LUT4
18250 
    generic map(
18251 
      INIT => X"1FBF"
18252 
    )
18253 
    port map (
18254 
      I0 => huffman_ins_v2_a0_value_2_1510,
18255 
      I1 => huffman_ins_v2_code_white_width(1),
18256 
      I2 => huffman_ins_v2_mux_code_black_width(2),
18257 
      I3 => huffman_ins_v2_code_black_width(1),
18258 
      O => huffman_ins_v2_N78
18259 
    );
18260 
  huffman_ins_v2_hor_code_8_mux000392_SW0 : LUT4
18261 
    generic map(
18262 
      INIT => X"A8A9"
18263 
    )
18264 
    port map (
18265 
      I0 => huffman_ins_v2_mux_code_black_width(4),
18266 
      I1 => huffman_ins_v2_mux_code_black_width(1),
18267 
      I2 => huffman_ins_v2_mux_code_black_width(2),
18268 
      I3 => huffman_ins_v2_mux_code_black_width(0),
18269 
      O => N383
18270 
    );
18271 
  huffman_ins_v2_hor_code_8_mux000392 : LUT4
18272 
    generic map(
18273 
      INIT => X"2A08"
18274 
    )
18275 
    port map (
18276 
      I0 => huffman_ins_v2_hor_code_8_mux000390_2037,
18277 
      I1 => huffman_ins_v2_mux_code_black_width(3),
18278 
      I2 => N383,
18279 
      I3 => huffman_ins_v2_mux_code_black_width(4),
18280 
      O => huffman_ins_v2_hor_code_8_mux000392_2038
18281 
    );
18282 
  fax4_ins_FIFO1_multi_read_ins_used_not0003_inv2 : LUT3
18283 
    generic map(
18284 
      INIT => X"80"
18285 
    )
18286 
    port map (
18287 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
18288 
      I1 => N208,
18289 
      I2 => fax4_ins_fifo_rd,
18290 
      O => fax4_ins_FIFO1_multi_read_ins_used_not0003_inv
18291 
    );
18292 
  huffman_ins_v2_hor_code_18_and00011 : LUT4
18293 
    generic map(
18294 
      INIT => X"A820"
18295 
    )
18296 
    port map (
18297 
      I0 => huffman_ins_v2_N246,
18298 
      I1 => huffman_ins_v2_a0_value_2_1510,
18299 
      I2 => huffman_ins_v2_code_black_width(4),
18300 
      I3 => huffman_ins_v2_code_white_width(4),
18301 
      O => huffman_ins_v2_hor_code_18_and0001
18302 
    );
18303 
  huffman_ins_v2_hor_code_17_mux00037111 : LUT4
18304 
    generic map(
18305 
      INIT => X"A820"
18306 
    )
18307 
    port map (
18308 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
18309 
      I1 => huffman_ins_v2_a0_value_2_1510,
18310 
      I2 => huffman_ins_v2_code_black_width(2),
18311 
      I3 => huffman_ins_v2_code_white_width(2),
18312 
      O => huffman_ins_v2_N248
18313 
    );
18314 
  huffman_ins_v2_hor_code_13_mux000389_SW0 : LUT3
18315 
    generic map(
18316 
      INIT => X"BD"
18317 
    )
18318 
    port map (
18319 
      I0 => huffman_ins_v2_mux_code_black_width(4),
18320 
      I1 => huffman_ins_v2_mux_code_black_width(1),
18321 
      I2 => huffman_ins_v2_mux_code_black_width(2),
18322 
      O => N385
18323 
    );
18324 
  huffman_ins_v2_hor_code_13_mux000389 : LUT4
18325 
    generic map(
18326 
      INIT => X"2A08"
18327 
    )
18328 
    port map (
18329 
      I0 => huffman_ins_v2_hor_code_13_mux000386_1859,
18330 
      I1 => huffman_ins_v2_mux_code_black_width(3),
18331 
      I2 => N385,
18332 
      I3 => huffman_ins_v2_mux_code_black_width(4),
18333 
      O => huffman_ins_v2_hor_code_13_mux000389_1860
18334 
    );
18335 
  huffman_ins_v2_hor_code_1_mux0003111 : LUT4
18336 
    generic map(
18337 
      INIT => X"FFE2"
18338 
    )
18339 
    port map (
18340 
      I0 => huffman_ins_v2_code_black_width(2),
18341 
      I1 => huffman_ins_v2_a0_value_2_1510,
18342 
      I2 => huffman_ins_v2_code_white_width(2),
18343 
      I3 => huffman_ins_v2_mux_code_white_width(1),
18344 
      O => huffman_ins_v2_N59
18345 
    );
18346 
  huffman_ins_v2_hor_code_8_mux0003311 : LUT4
18347 
    generic map(
18348 
      INIT => X"FFE2"
18349 
    )
18350 
    port map (
18351 
      I0 => huffman_ins_v2_code_white_width(1),
18352 
      I1 => huffman_ins_v2_a0_value_2_1510,
18353 
      I2 => huffman_ins_v2_code_black_width(1),
18354 
      I3 => huffman_ins_v2_mux_code_black_width(2),
18355 
      O => huffman_ins_v2_N99
18356 
    );
18357 
  fax4_ins_Madd_a1b1_addsub0001_cy_9_rt : LUT1
18358 
    generic map(
18359 
      INIT => X"2"
18360 
    )
18361 
    port map (
18362 
      I0 => fax4_ins_b1(9),
18363 
      O => fax4_ins_Madd_a1b1_addsub0001_cy_9_rt_730
18364 
    );
18365 
  fax4_ins_Madd_a1b1_addsub0001_cy_7_rt : LUT1
18366 
    generic map(
18367 
      INIT => X"2"
18368 
    )
18369 
    port map (
18370 
      I0 => fax4_ins_b1(7),
18371 
      O => fax4_ins_Madd_a1b1_addsub0001_cy_7_rt_727
18372 
    );
18373 
  fax4_ins_Madd_a1b1_addsub0001_cy_6_rt : LUT1
18374 
    generic map(
18375 
      INIT => X"2"
18376 
    )
18377 
    port map (
18378 
      I0 => fax4_ins_b1(6),
18379 
      O => fax4_ins_Madd_a1b1_addsub0001_cy_6_rt_725
18380 
    );
18381 
  fax4_ins_Madd_a1b1_addsub0001_cy_5_rt : LUT1
18382 
    generic map(
18383 
      INIT => X"2"
18384 
    )
18385 
    port map (
18386 
      I0 => fax4_ins_b1(5),
18387 
      O => fax4_ins_Madd_a1b1_addsub0001_cy_5_rt_723
18388 
    );
18389 
  fax4_ins_Madd_a1b1_addsub0001_cy_4_rt : LUT1
18390 
    generic map(
18391 
      INIT => X"2"
18392 
    )
18393 
    port map (
18394 
      I0 => fax4_ins_b1(4),
18395 
      O => fax4_ins_Madd_a1b1_addsub0001_cy_4_rt_721
18396 
    );
18397 
  fax4_ins_Madd_a1b1_addsub0001_cy_1_rt : LUT1
18398 
    generic map(
18399 
      INIT => X"2"
18400 
    )
18401 
    port map (
18402 
      I0 => fax4_ins_b1(1),
18403 
      O => fax4_ins_Madd_a1b1_addsub0001_cy_1_rt_717
18404 
    );
18405 
  huffman_ins_v2_code_black_8_mux0000172 : MUXF5
18406 
    port map (
18407 
      I0 => N387,
18408 
      I1 => N388,
18409 
      S => huffman_ins_v2_codetab_ter_black_width(2),
18410 
      O => huffman_ins_v2_code_black_8_mux0000172_1666
18411 
    );
18412 
  huffman_ins_v2_code_black_8_mux0000172_F : LUT4
18413 
    generic map(
18414 
      INIT => X"ABA8"
18415 
    )
18416 
    port map (
18417 
      I0 => huffman_ins_v2_ter_black_code(8),
18418 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
18419 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
18420 
      I3 => huffman_ins_v2_code_table_ins_makeup_black_0_Q,
18421 
      O => N387
18422 
    );
18423 
  huffman_ins_v2_code_black_8_mux0000172_G : LUT4
18424 
    generic map(
18425 
      INIT => X"ABA8"
18426 
    )
18427 
    port map (
18428 
      I0 => huffman_ins_v2_code_black(8),
18429 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
18430 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
18431 
      I3 => huffman_ins_v2_ter_black_code(8),
18432 
      O => N388
18433 
    );
18434 
  huffman_ins_v2_code_black_14_mux00001107 : MUXF5
18435 
    port map (
18436 
      I0 => N389,
18437 
      I1 => N390,
18438 
      S => huffman_ins_v2_code_black_10_mux0000_bdd4,
18439 
      O => huffman_ins_v2_code_black_14_mux00001107_1554
18440 
    );
18441 
  huffman_ins_v2_code_black_14_mux00001107_F : LUT4
18442 
    generic map(
18443 
      INIT => X"7160"
18444 
    )
18445 
    port map (
18446 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
18447 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
18448 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
18449 
      I3 => huffman_ins_v2_code_black(14),
18450 
      O => N389
18451 
    );
18452 
  huffman_ins_v2_code_black_14_mux00001107_G : LUT4
18453 
    generic map(
18454 
      INIT => X"EDE8"
18455 
    )
18456 
    port map (
18457 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
18458 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
18459 
      I2 => huffman_ins_v2_codetab_ter_black_width(2),
18460 
      I3 => huffman_ins_v2_code_black(14),
18461 
      O => N390
18462 
    );
18463 
  huffman_ins_v2_code_black_13_mux00001107 : MUXF5
18464 
    port map (
18465 
      I0 => N391,
18466 
      I1 => N392,
18467 
      S => huffman_ins_v2_code_black_11_mux0000_bdd5,
18468 
      O => huffman_ins_v2_code_black_13_mux00001107_1547
18469 
    );
18470 
  huffman_ins_v2_code_black_13_mux00001107_F : LUT4
18471 
    generic map(
18472 
      INIT => X"7160"
18473 
    )
18474 
    port map (
18475 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
18476 
      I1 => huffman_ins_v2_codetab_ter_black_width(2),
18477 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
18478 
      I3 => huffman_ins_v2_code_black(13),
18479 
      O => N391
18480 
    );
18481 
  huffman_ins_v2_code_black_13_mux00001107_G : LUT4
18482 
    generic map(
18483 
      INIT => X"EDE8"
18484 
    )
18485 
    port map (
18486 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
18487 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
18488 
      I2 => huffman_ins_v2_codetab_ter_black_width(2),
18489 
      I3 => huffman_ins_v2_code_black(13),
18490 
      O => N392
18491 
    );
18492 
  huffman_ins_v2_code_black_12_mux00001107 : MUXF5
18493 
    port map (
18494 
      I0 => N393,
18495 
      I1 => N394,
18496 
      S => huffman_ins_v2_codetab_ter_black_width(1),
18497 
      O => huffman_ins_v2_code_black_12_mux00001107_1540
18498 
    );
18499 
  huffman_ins_v2_code_black_12_mux00001107_F : LUT3
18500 
    generic map(
18501 
      INIT => X"E4"
18502 
    )
18503 
    port map (
18504 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
18505 
      I1 => huffman_ins_v2_code_black(12),
18506 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd4,
18507 
      O => N393
18508 
    );
18509 
  huffman_ins_v2_code_black_12_mux00001107_G : LUT3
18510 
    generic map(
18511 
      INIT => X"E4"
18512 
    )
18513 
    port map (
18514 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
18515 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
18516 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd5,
18517 
      O => N394
18518 
    );
18519 
  huffman_ins_v2_code_black_11_mux00001107 : MUXF5
18520 
    port map (
18521 
      I0 => N395,
18522 
      I1 => N396,
18523 
      S => huffman_ins_v2_codetab_ter_black_width(1),
18524 
      O => huffman_ins_v2_code_black_11_mux00001107_1529
18525 
    );
18526 
  huffman_ins_v2_code_black_11_mux00001107_F : LUT3
18527 
    generic map(
18528 
      INIT => X"E4"
18529 
    )
18530 
    port map (
18531 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
18532 
      I1 => huffman_ins_v2_code_black(11),
18533 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd5,
18534 
      O => N395
18535 
    );
18536 
  huffman_ins_v2_code_black_11_mux00001107_G : LUT3
18537 
    generic map(
18538 
      INIT => X"E4"
18539 
    )
18540 
    port map (
18541 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
18542 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
18543 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd3,
18544 
      O => N396
18545 
    );
18546 
  fax4_ins_state_FSM_FFd10_In : MUXF5
18547 
    port map (
18548 
      I0 => N397,
18549 
      I1 => N398,
18550 
      S => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
18551 
      O => fax4_ins_state_FSM_FFd10_In_1324
18552 
    );
18553 
  fax4_ins_state_FSM_FFd10_In_F : LUT3
18554 
    generic map(
18555 
      INIT => X"EA"
18556 
    )
18557 
    port map (
18558 
      I0 => fax4_ins_state_FSM_FFd11_1325,
18559 
      I1 => fax4_ins_EOF_prev_228,
18560 
      I2 => fax4_ins_state_FSM_N12,
18561 
      O => N397
18562 
    );
18563 
  fax4_ins_state_FSM_FFd10_In_G : LUT3
18564 
    generic map(
18565 
      INIT => X"FE"
18566 
    )
18567 
    port map (
18568 
      I0 => fax4_ins_state_FSM_FFd3_1329,
18569 
      I1 => fax4_ins_state_FSM_FFd9_1341,
18570 
      I2 => fax4_ins_state_FSM_N12,
18571 
      O => N398
18572 
    );
18573 
  huffman_ins_v2_hor_code_12_mux000364 : MUXF5
18574 
    port map (
18575 
      I0 => N399,
18576 
      I1 => N400,
18577 
      S => huffman_ins_v2_mux_code_black_width(4),
18578 
      O => huffman_ins_v2_hor_code_12_mux000364_1849
18579 
    );
18580 
  huffman_ins_v2_hor_code_12_mux000364_F : LUT3
18581 
    generic map(
18582 
      INIT => X"FE"
18583 
    )
18584 
    port map (
18585 
      I0 => huffman_ins_v2_hor_code_12_mux000311_1839,
18586 
      I1 => huffman_ins_v2_hor_code_12_mux000339_1848,
18587 
      I2 => huffman_ins_v2_hor_code_12_mux000324_1846,
18588 
      O => N399
18589 
    );
18590 
  huffman_ins_v2_hor_code_12_mux000364_G : LUT4
18591 
    generic map(
18592 
      INIT => X"FFEA"
18593 
    )
18594 
    port map (
18595 
      I0 => huffman_ins_v2_hor_code_12_mux000311_1839,
18596 
      I1 => huffman_ins_v2_N251,
18597 
      I2 => huffman_ins_v2_mux_code_black_width(3),
18598 
      I3 => huffman_ins_v2_hor_code_12_mux000324_1846,
18599 
      O => N400
18600 
    );
18601 
  huffman_ins_v2_code_black_10_mux00001154 : MUXF5
18602 
    port map (
18603 
      I0 => N401,
18604 
      I1 => N402,
18605 
      S => huffman_ins_v2_codetab_ter_black_width(3),
18606 
      O => huffman_ins_v2_code_black_10_mux0000
18607 
    );
18608 
  huffman_ins_v2_code_black_10_mux00001154_F : LUT3
18609 
    generic map(
18610 
      INIT => X"E4"
18611 
    )
18612 
    port map (
18613 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
18614 
      I1 => huffman_ins_v2_code_black_10_mux00001116_1518,
18615 
      I2 => huffman_ins_v2_code_black_10_mux00001103_1517,
18616 
      O => N401
18617 
    );
18618 
  huffman_ins_v2_code_black_10_mux00001154_G : LUT4
18619 
    generic map(
18620 
      INIT => X"FAD8"
18621 
    )
18622 
    port map (
18623 
      I0 => huffman_ins_v2_codetab_ter_black_width(1),
18624 
      I1 => huffman_ins_v2_code_black_10_mux000010_1516,
18625 
      I2 => huffman_ins_v2_code_black_10_mux0000152,
18626 
      I3 => huffman_ins_v2_code_black_10_mux0000115_1519,
18627 
      O => N402
18628 
    );
18629 
  huffman_ins_v2_code_black_6_mux00002126 : MUXF5
18630 
    port map (
18631 
      I0 => N403,
18632 
      I1 => N404,
18633 
      S => huffman_ins_v2_codetab_ter_black_width(1),
18634 
      O => huffman_ins_v2_code_black_6_mux00002126_1652
18635 
    );
18636 
  huffman_ins_v2_code_black_6_mux00002126_F : LUT3
18637 
    generic map(
18638 
      INIT => X"E4"
18639 
    )
18640 
    port map (
18641 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
18642 
      I1 => huffman_ins_v2_code_black(6),
18643 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd2,
18644 
      O => N403
18645 
    );
18646 
  huffman_ins_v2_code_black_6_mux00002126_G : LUT3
18647 
    generic map(
18648 
      INIT => X"E4"
18649 
    )
18650 
    port map (
18651 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
18652 
      I1 => huffman_ins_v2_code_black_10_mux0000_bdd3,
18653 
      I2 => huffman_ins_v2_code_black_6_mux0000282_1654,
18654 
      O => N404
18655 
    );
18656 
  huffman_ins_v2_code_black_9_mux00002107 : MUXF5
18657 
    port map (
18658 
      I0 => N405,
18659 
      I1 => N406,
18660 
      S => huffman_ins_v2_codetab_ter_black_width(1),
18661 
      O => huffman_ins_v2_code_black_9_mux00002107_1669
18662 
    );
18663 
  huffman_ins_v2_code_black_9_mux00002107_F : LUT3
18664 
    generic map(
18665 
      INIT => X"E4"
18666 
    )
18667 
    port map (
18668 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
18669 
      I1 => huffman_ins_v2_code_black(9),
18670 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd3,
18671 
      O => N405
18672 
    );
18673 
  huffman_ins_v2_code_black_9_mux00002107_G : LUT3
18674 
    generic map(
18675 
      INIT => X"E4"
18676 
    )
18677 
    port map (
18678 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
18679 
      I1 => huffman_ins_v2_code_black_11_mux0000_bdd5,
18680 
      I2 => huffman_ins_v2_code_black_11_mux0000_bdd2,
18681 
      O => N406
18682 
    );
18683 
  huffman_ins_v2_code_black_8_mux00001126 : MUXF5
18684 
    port map (
18685 
      I0 => N407,
18686 
      I1 => N408,
18687 
      S => huffman_ins_v2_codetab_ter_black_width(1),
18688 
      O => huffman_ins_v2_code_black_8_mux00001126_1665
18689 
    );
18690 
  huffman_ins_v2_code_black_8_mux00001126_F : LUT3
18691 
    generic map(
18692 
      INIT => X"E4"
18693 
    )
18694 
    port map (
18695 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
18696 
      I1 => huffman_ins_v2_code_black(8),
18697 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd3,
18698 
      O => N407
18699 
    );
18700 
  huffman_ins_v2_code_black_8_mux00001126_G : LUT3
18701 
    generic map(
18702 
      INIT => X"E4"
18703 
    )
18704 
    port map (
18705 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
18706 
      I1 => huffman_ins_v2_code_black_10_mux0000_bdd5,
18707 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd2,
18708 
      O => N408
18709 
    );
18710 
  huffman_ins_v2_hor_code_19_mux0003138 : MUXF5
18711 
    port map (
18712 
      I0 => N409,
18713 
      I1 => N410,
18714 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
18715 
      O => huffman_ins_v2_hor_code_19_mux0003138_1925
18716 
    );
18717 
  huffman_ins_v2_hor_code_19_mux0003138_F : LUT4
18718 
    generic map(
18719 
      INIT => X"2A08"
18720 
    )
18721 
    port map (
18722 
      I0 => huffman_ins_v2_hor_code(19),
18723 
      I1 => huffman_ins_v2_hor_code_18_and0001,
18724 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(1),
18725 
      I3 => huffman_ins_v2_N3,
18726 
      O => N409
18727 
    );
18728 
  huffman_ins_v2_hor_code_19_mux0003138_G : LUT4
18729 
    generic map(
18730 
      INIT => X"AA02"
18731 
    )
18732 
    port map (
18733 
      I0 => huffman_ins_v2_hor_code(19),
18734 
      I1 => huffman_ins_v2_mux_code_black_width(2),
18735 
      I2 => huffman_ins_v2_mux_code_black_width(3),
18736 
      I3 => huffman_ins_v2_N65,
18737 
      O => N410
18738 
    );
18739 
  huffman_ins_v2_hor_code_14_mux000343 : MUXF5
18740 
    port map (
18741 
      I0 => N411,
18742 
      I1 => N412,
18743 
      S => huffman_ins_v2_N11,
18744 
      O => huffman_ins_v2_hor_code_14_mux000343_1879
18745 
    );
18746 
  huffman_ins_v2_hor_code_14_mux000343_F : LUT3
18747 
    generic map(
18748 
      INIT => X"80"
18749 
    )
18750 
    port map (
18751 
      I0 => huffman_ins_v2_hor_code_14_mux000327_1876,
18752 
      I1 => huffman_ins_v2_code_white_width(4),
18753 
      I2 => huffman_ins_v2_code_white(14),
18754 
      O => N411
18755 
    );
18756 
  huffman_ins_v2_hor_code_14_mux000343_G : LUT3
18757 
    generic map(
18758 
      INIT => X"80"
18759 
    )
18760 
    port map (
18761 
      I0 => huffman_ins_v2_hor_code_14_mux00038_1882,
18762 
      I1 => huffman_ins_v2_code_black_width(4),
18763 
      I2 => huffman_ins_v2_code_black(14),
18764 
      O => N412
18765 
    );
18766 
  huffman_ins_v2_hor_code_21_mux0003168 : MUXF5
18767 
    port map (
18768 
      I0 => N413,
18769 
      I1 => N414,
18770 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
18771 
      O => huffman_ins_v2_hor_code_21_mux0003168_1951
18772 
    );
18773 
  huffman_ins_v2_hor_code_21_mux0003168_F : LUT3
18774 
    generic map(
18775 
      INIT => X"FD"
18776 
    )
18777 
    port map (
18778 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
18779 
      I1 => huffman_ins_v2_hor_code_21_mux0003123_1950,
18780 
      I2 => huffman_ins_v2_hor_code_20_mux000346_1945,
18781 
      O => N413
18782 
    );
18783 
  huffman_ins_v2_hor_code_21_mux0003168_G : LUT4
18784 
    generic map(
18785 
      INIT => X"FFAE"
18786 
    )
18787 
    port map (
18788 
      I0 => huffman_ins_v2_N186,
18789 
      I1 => huffman_ins_v2_N78,
18790 
      I2 => huffman_ins_v2_mux_code_black_width(3),
18791 
      I3 => huffman_ins_v2_hor_code_21_mux000395_1957,
18792 
      O => N414
18793 
    );
18794 
  huffman_ins_v2_hor_code_3_mux000397 : MUXF5
18795 
    port map (
18796 
      I0 => N415,
18797 
      I1 => N416,
18798 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
18799 
      O => huffman_ins_v2_hor_code_3_mux000397_1995
18800 
    );
18801 
  huffman_ins_v2_hor_code_3_mux000397_F : LUT4
18802 
    generic map(
18803 
      INIT => X"A820"
18804 
    )
18805 
    port map (
18806 
      I0 => huffman_ins_v2_N40,
18807 
      I1 => huffman_ins_v2_a0_value_2_1510,
18808 
      I2 => huffman_ins_v2_code_black(3),
18809 
      I3 => huffman_ins_v2_code_white(3),
18810 
      O => N415
18811 
    );
18812 
  huffman_ins_v2_hor_code_3_mux000397_G : LUT4
18813 
    generic map(
18814 
      INIT => X"A820"
18815 
    )
18816 
    port map (
18817 
      I0 => huffman_ins_v2_N52,
18818 
      I1 => huffman_ins_v2_a0_value_2_1510,
18819 
      I2 => huffman_ins_v2_code_white(3),
18820 
      I3 => huffman_ins_v2_code_black(3),
18821 
      O => N416
18822 
    );
18823 
  huffman_ins_v2_hor_code_18_mux000328 : MUXF5
18824 
    port map (
18825 
      I0 => N417,
18826 
      I1 => N418,
18827 
      S => huffman_ins_v2_a0_value_2_1510,
18828 
      O => huffman_ins_v2_hor_code_18_mux000328_1921
18829 
    );
18830 
  huffman_ins_v2_hor_code_18_mux000328_F : LUT4
18831 
    generic map(
18832 
      INIT => X"0103"
18833 
    )
18834 
    port map (
18835 
      I0 => huffman_ins_v2_code_white_width(0),
18836 
      I1 => huffman_ins_v2_code_white_width(3),
18837 
      I2 => huffman_ins_v2_code_white_width(2),
18838 
      I3 => huffman_ins_v2_code_white_width(1),
18839 
      O => N417
18840 
    );
18841 
  huffman_ins_v2_hor_code_18_mux000328_G : LUT4
18842 
    generic map(
18843 
      INIT => X"0103"
18844 
    )
18845 
    port map (
18846 
      I0 => huffman_ins_v2_code_black_width(0),
18847 
      I1 => huffman_ins_v2_code_black_width(3),
18848 
      I2 => huffman_ins_v2_code_black_width(2),
18849 
      I3 => huffman_ins_v2_code_black_width(1),
18850 
      O => N418
18851 
    );
18852 
  fax4_ins_b2_mux0004_9_36 : MUXF5
18853 
    port map (
18854 
      I0 => N419,
18855 
      I1 => N420,
18856 
      S => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
18857 
      O => fax4_ins_b2_mux0004_9_36_1093
18858 
    );
18859 
  fax4_ins_b2_mux0004_9_36_F : LUT4
18860 
    generic map(
18861 
      INIT => X"AA2A"
18862 
    )
18863 
    port map (
18864 
      I0 => fax4_ins_N19,
18865 
      I1 => fax4_ins_mux_b1(3),
18866 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
18867 
      I3 => fax4_ins_FIFO2_multi_read_ins_data3_o(9),
18868 
      O => N419
18869 
    );
18870 
  fax4_ins_b2_mux0004_9_36_G : LUT4
18871 
    generic map(
18872 
      INIT => X"AA2A"
18873 
    )
18874 
    port map (
18875 
      I0 => fax4_ins_N19,
18876 
      I1 => fax4_ins_mux_b1(3),
18877 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
18878 
      I3 => fax4_ins_FIFO1_multi_read_ins_data3_o(9),
18879 
      O => N420
18880 
    );
18881 
  fax4_ins_b2_mux0004_8_33 : MUXF5
18882 
    port map (
18883 
      I0 => N421,
18884 
      I1 => N422,
18885 
      S => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
18886 
      O => fax4_ins_b2_mux0004_8_33_1090
18887 
    );
18888 
  fax4_ins_b2_mux0004_8_33_F : LUT4
18889 
    generic map(
18890 
      INIT => X"8000"
18891 
    )
18892 
    port map (
18893 
      I0 => fax4_ins_N19,
18894 
      I1 => fax4_ins_mux_b1(3),
18895 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
18896 
      I3 => fax4_ins_FIFO2_multi_read_ins_data3_o(8),
18897 
      O => N421
18898 
    );
18899 
  fax4_ins_b2_mux0004_8_33_G : LUT4
18900 
    generic map(
18901 
      INIT => X"8000"
18902 
    )
18903 
    port map (
18904 
      I0 => fax4_ins_N19,
18905 
      I1 => fax4_ins_mux_b1(3),
18906 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
18907 
      I3 => fax4_ins_FIFO1_multi_read_ins_data3_o(8),
18908 
      O => N422
18909 
    );
18910 
  fax4_ins_b2_mux0004_7_36 : MUXF5
18911 
    port map (
18912 
      I0 => N423,
18913 
      I1 => N424,
18914 
      S => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
18915 
      O => fax4_ins_b2_mux0004_7_36_1087
18916 
    );
18917 
  fax4_ins_b2_mux0004_7_36_F : LUT4
18918 
    generic map(
18919 
      INIT => X"AA2A"
18920 
    )
18921 
    port map (
18922 
      I0 => fax4_ins_N19,
18923 
      I1 => fax4_ins_mux_b1(3),
18924 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
18925 
      I3 => fax4_ins_FIFO2_multi_read_ins_data3_o(7),
18926 
      O => N423
18927 
    );
18928 
  fax4_ins_b2_mux0004_7_36_G : LUT4
18929 
    generic map(
18930 
      INIT => X"AA2A"
18931 
    )
18932 
    port map (
18933 
      I0 => fax4_ins_N19,
18934 
      I1 => fax4_ins_mux_b1(3),
18935 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
18936 
      I3 => fax4_ins_FIFO1_multi_read_ins_data3_o(7),
18937 
      O => N424
18938 
    );
18939 
  fax4_ins_b2_mux0004_6_36 : MUXF5
18940 
    port map (
18941 
      I0 => N425,
18942 
      I1 => N426,
18943 
      S => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
18944 
      O => fax4_ins_b2_mux0004_6_36_1084
18945 
    );
18946 
  fax4_ins_b2_mux0004_6_36_F : LUT4
18947 
    generic map(
18948 
      INIT => X"AA2A"
18949 
    )
18950 
    port map (
18951 
      I0 => fax4_ins_N19,
18952 
      I1 => fax4_ins_mux_b1(3),
18953 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
18954 
      I3 => fax4_ins_FIFO2_multi_read_ins_data3_o(6),
18955 
      O => N425
18956 
    );
18957 
  fax4_ins_b2_mux0004_6_36_G : LUT4
18958 
    generic map(
18959 
      INIT => X"AA2A"
18960 
    )
18961 
    port map (
18962 
      I0 => fax4_ins_N19,
18963 
      I1 => fax4_ins_mux_b1(3),
18964 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
18965 
      I3 => fax4_ins_FIFO1_multi_read_ins_data3_o(6),
18966 
      O => N426
18967 
    );
18968 
  fax4_ins_b2_mux0004_5_36 : MUXF5
18969 
    port map (
18970 
      I0 => N427,
18971 
      I1 => N428,
18972 
      S => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
18973 
      O => fax4_ins_b2_mux0004_5_36_1081
18974 
    );
18975 
  fax4_ins_b2_mux0004_5_36_F : LUT4
18976 
    generic map(
18977 
      INIT => X"AA2A"
18978 
    )
18979 
    port map (
18980 
      I0 => fax4_ins_N19,
18981 
      I1 => fax4_ins_mux_b1(3),
18982 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
18983 
      I3 => fax4_ins_FIFO2_multi_read_ins_data3_o(5),
18984 
      O => N427
18985 
    );
18986 
  fax4_ins_b2_mux0004_5_36_G : LUT4
18987 
    generic map(
18988 
      INIT => X"AA2A"
18989 
    )
18990 
    port map (
18991 
      I0 => fax4_ins_N19,
18992 
      I1 => fax4_ins_mux_b1(3),
18993 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
18994 
      I3 => fax4_ins_FIFO1_multi_read_ins_data3_o(5),
18995 
      O => N428
18996 
    );
18997 
  fax4_ins_b2_mux0004_4_36 : MUXF5
18998 
    port map (
18999 
      I0 => N429,
19000 
      I1 => N430,
19001 
      S => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
19002 
      O => fax4_ins_b2_mux0004_4_36_1078
19003 
    );
19004 
  fax4_ins_b2_mux0004_4_36_F : LUT4
19005 
    generic map(
19006 
      INIT => X"AA2A"
19007 
    )
19008 
    port map (
19009 
      I0 => fax4_ins_N19,
19010 
      I1 => fax4_ins_mux_b1(3),
19011 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
19012 
      I3 => fax4_ins_FIFO2_multi_read_ins_data3_o(4),
19013 
      O => N429
19014 
    );
19015 
  fax4_ins_b2_mux0004_4_36_G : LUT4
19016 
    generic map(
19017 
      INIT => X"AA2A"
19018 
    )
19019 
    port map (
19020 
      I0 => fax4_ins_N19,
19021 
      I1 => fax4_ins_mux_b1(3),
19022 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
19023 
      I3 => fax4_ins_FIFO1_multi_read_ins_data3_o(4),
19024 
      O => N430
19025 
    );
19026 
  fax4_ins_b2_mux0004_3_33 : MUXF5
19027 
    port map (
19028 
      I0 => N431,
19029 
      I1 => N432,
19030 
      S => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
19031 
      O => fax4_ins_b2_mux0004_3_33_1075
19032 
    );
19033 
  fax4_ins_b2_mux0004_3_33_F : LUT4
19034 
    generic map(
19035 
      INIT => X"8000"
19036 
    )
19037 
    port map (
19038 
      I0 => fax4_ins_N19,
19039 
      I1 => fax4_ins_mux_b1(3),
19040 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
19041 
      I3 => fax4_ins_FIFO2_multi_read_ins_data3_o(3),
19042 
      O => N431
19043 
    );
19044 
  fax4_ins_b2_mux0004_3_33_G : LUT4
19045 
    generic map(
19046 
      INIT => X"8000"
19047 
    )
19048 
    port map (
19049 
      I0 => fax4_ins_N19,
19050 
      I1 => fax4_ins_mux_b1(3),
19051 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
19052 
      I3 => fax4_ins_FIFO1_multi_read_ins_data3_o(3),
19053 
      O => N432
19054 
    );
19055 
  fax4_ins_b2_mux0004_2_33 : MUXF5
19056 
    port map (
19057 
      I0 => N433,
19058 
      I1 => N434,
19059 
      S => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
19060 
      O => fax4_ins_b2_mux0004_2_33_1072
19061 
    );
19062 
  fax4_ins_b2_mux0004_2_33_F : LUT4
19063 
    generic map(
19064 
      INIT => X"8000"
19065 
    )
19066 
    port map (
19067 
      I0 => fax4_ins_N19,
19068 
      I1 => fax4_ins_mux_b1(3),
19069 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
19070 
      I3 => fax4_ins_FIFO2_multi_read_ins_data3_o(2),
19071 
      O => N433
19072 
    );
19073 
  fax4_ins_b2_mux0004_2_33_G : LUT4
19074 
    generic map(
19075 
      INIT => X"8000"
19076 
    )
19077 
    port map (
19078 
      I0 => fax4_ins_N19,
19079 
      I1 => fax4_ins_mux_b1(3),
19080 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
19081 
      I3 => fax4_ins_FIFO1_multi_read_ins_data3_o(2),
19082 
      O => N434
19083 
    );
19084 
  fax4_ins_b2_mux0004_1_33 : MUXF5
19085 
    port map (
19086 
      I0 => N435,
19087 
      I1 => N436,
19088 
      S => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
19089 
      O => fax4_ins_b2_mux0004_1_33_1069
19090 
    );
19091 
  fax4_ins_b2_mux0004_1_33_F : LUT4
19092 
    generic map(
19093 
      INIT => X"8000"
19094 
    )
19095 
    port map (
19096 
      I0 => fax4_ins_N19,
19097 
      I1 => fax4_ins_mux_b1(3),
19098 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
19099 
      I3 => fax4_ins_FIFO2_multi_read_ins_data3_o(1),
19100 
      O => N435
19101 
    );
19102 
  fax4_ins_b2_mux0004_1_33_G : LUT4
19103 
    generic map(
19104 
      INIT => X"8000"
19105 
    )
19106 
    port map (
19107 
      I0 => fax4_ins_N19,
19108 
      I1 => fax4_ins_mux_b1(3),
19109 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
19110 
      I3 => fax4_ins_FIFO1_multi_read_ins_data3_o(1),
19111 
      O => N436
19112 
    );
19113 
  fax4_ins_b2_mux0004_0_36 : MUXF5
19114 
    port map (
19115 
      I0 => N437,
19116 
      I1 => N438,
19117 
      S => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
19118 
      O => fax4_ins_b2_mux0004_0_36_1066
19119 
    );
19120 
  fax4_ins_b2_mux0004_0_36_F : LUT4
19121 
    generic map(
19122 
      INIT => X"AA2A"
19123 
    )
19124 
    port map (
19125 
      I0 => fax4_ins_N19,
19126 
      I1 => fax4_ins_mux_b1(3),
19127 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
19128 
      I3 => fax4_ins_FIFO2_multi_read_ins_data3_o(0),
19129 
      O => N437
19130 
    );
19131 
  fax4_ins_b2_mux0004_0_36_G : LUT4
19132 
    generic map(
19133 
      INIT => X"AA2A"
19134 
    )
19135 
    port map (
19136 
      I0 => fax4_ins_N19,
19137 
      I1 => fax4_ins_mux_b1(3),
19138 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
19139 
      I3 => fax4_ins_FIFO1_multi_read_ins_data3_o(0),
19140 
      O => N438
19141 
    );
19142 
  fax4_ins_b2_to_white_mux000452 : MUXF5
19143 
    port map (
19144 
      I0 => N439,
19145 
      I1 => N440,
19146 
      S => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
19147 
      O => fax4_ins_b2_to_white_mux000452_1099
19148 
    );
19149 
  fax4_ins_b2_to_white_mux000452_F : LUT4
19150 
    generic map(
19151 
      INIT => X"AA2A"
19152 
    )
19153 
    port map (
19154 
      I0 => fax4_ins_N19,
19155 
      I1 => fax4_ins_mux_b1(3),
19156 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid3_o_700,
19157 
      I3 => fax4_ins_FIFO2_multi_read_ins_to_white3_o_685,
19158 
      O => N439
19159 
    );
19160 
  fax4_ins_b2_to_white_mux000452_G : LUT4
19161 
    generic map(
19162 
      INIT => X"AA2A"
19163 
    )
19164 
    port map (
19165 
      I0 => fax4_ins_N19,
19166 
      I1 => fax4_ins_mux_b1(3),
19167 
      I2 => fax4_ins_FIFO1_multi_read_ins_valid3_o_458,
19168 
      I3 => fax4_ins_FIFO1_multi_read_ins_to_white3_o_443,
19169 
      O => N440
19170 
    );
19171 
  huffman_ins_v2_hor_code_12_mux0003249 : MUXF5
19172 
    port map (
19173 
      I0 => N441,
19174 
      I1 => N442,
19175 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
19176 
      O => huffman_ins_v2_hor_code_12_mux0003249_1847
19177 
    );
19178 
  huffman_ins_v2_hor_code_12_mux0003249_F : LUT4
19179 
    generic map(
19180 
      INIT => X"A820"
19181 
    )
19182 
    port map (
19183 
      I0 => huffman_ins_v2_N44,
19184 
      I1 => huffman_ins_v2_a0_value_2_1510,
19185 
      I2 => huffman_ins_v2_code_black(12),
19186 
      I3 => huffman_ins_v2_code_white(12),
19187 
      O => N441
19188 
    );
19189 
  huffman_ins_v2_hor_code_12_mux0003249_G : LUT4
19190 
    generic map(
19191 
      INIT => X"A820"
19192 
    )
19193 
    port map (
19194 
      I0 => huffman_ins_v2_N60,
19195 
      I1 => huffman_ins_v2_a0_value_2_1510,
19196 
      I2 => huffman_ins_v2_code_white(12),
19197 
      I3 => huffman_ins_v2_code_black(12),
19198 
      O => N442
19199 
    );
19200 
  huffman_ins_v2_hor_code_0_mux000352 : MUXF5
19201 
    port map (
19202 
      I0 => N443,
19203 
      I1 => N444,
19204 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
19205 
      O => huffman_ins_v2_hor_code_0_mux000352_1819
19206 
    );
19207 
  huffman_ins_v2_hor_code_0_mux000352_F : LUT4
19208 
    generic map(
19209 
      INIT => X"A820"
19210 
    )
19211 
    port map (
19212 
      I0 => huffman_ins_v2_N45,
19213 
      I1 => huffman_ins_v2_a0_value_2_1510,
19214 
      I2 => huffman_ins_v2_code_black(0),
19215 
      I3 => huffman_ins_v2_code_white(0),
19216 
      O => N443
19217 
    );
19218 
  huffman_ins_v2_hor_code_0_mux000352_G : LUT4
19219 
    generic map(
19220 
      INIT => X"A820"
19221 
    )
19222 
    port map (
19223 
      I0 => huffman_ins_v2_N16,
19224 
      I1 => huffman_ins_v2_a0_value_2_1510,
19225 
      I2 => huffman_ins_v2_code_white(0),
19226 
      I3 => huffman_ins_v2_code_black(0),
19227 
      O => N444
19228 
    );
19229 
  huffman_ins_v2_hor_code_25_mux000380 : MUXF5
19230 
    port map (
19231 
      I0 => N445,
19232 
      I1 => N446,
19233 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
19234 
      O => huffman_ins_v2_hor_code_25_mux000380_1982
19235 
    );
19236 
  huffman_ins_v2_hor_code_25_mux000380_F : LUT4
19237 
    generic map(
19238 
      INIT => X"EAAA"
19239 
    )
19240 
    port map (
19241 
      I0 => huffman_ins_v2_hor_code_25_mux000342_1981,
19242 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
19243 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
19244 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(1),
19245 
      O => N445
19246 
    );
19247 
  huffman_ins_v2_hor_code_25_mux000380_G : LUT4
19248 
    generic map(
19249 
      INIT => X"F7D7"
19250 
    )
19251 
    port map (
19252 
      I0 => huffman_ins_v2_hor_code_23_and0000,
19253 
      I1 => huffman_ins_v2_mux_code_black_width(1),
19254 
      I2 => huffman_ins_v2_mux_code_black_width(2),
19255 
      I3 => huffman_ins_v2_mux_code_black_width(0),
19256 
      O => N446
19257 
    );
19258 
  huffman_ins_v2_hor_code_23_mux000356 : MUXF5
19259 
    port map (
19260 
      I0 => N447,
19261 
      I1 => N448,
19262 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
19263 
      O => huffman_ins_v2_hor_code_23_mux000356_1969
19264 
    );
19265 
  huffman_ins_v2_hor_code_23_mux000356_F : LUT4
19266 
    generic map(
19267 
      INIT => X"FF01"
19268 
    )
19269 
    port map (
19270 
      I0 => huffman_ins_v2_mux_code_white_width(1),
19271 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
19272 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
19273 
      I3 => huffman_ins_v2_N3,
19274 
      O => N447
19275 
    );
19276 
  huffman_ins_v2_hor_code_23_mux000356_G : LUT3
19277 
    generic map(
19278 
      INIT => X"F7"
19279 
    )
19280 
    port map (
19281 
      I0 => huffman_ins_v2_mux_code_black_width(4),
19282 
      I1 => huffman_ins_v2_mux_code_black_width(3),
19283 
      I2 => huffman_ins_v2_N251,
19284 
      O => N448
19285 
    );
19286 
  huffman_ins_v2_hor_code_11_mux000321 : MUXF5
19287 
    port map (
19288 
      I0 => N449,
19289 
      I1 => N450,
19290 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
19291 
      O => huffman_ins_v2_hor_code_11_mux000321_1833
19292 
    );
19293 
  huffman_ins_v2_hor_code_11_mux000321_F : LUT4
19294 
    generic map(
19295 
      INIT => X"0001"
19296 
    )
19297 
    port map (
19298 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
19299 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
19300 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
19301 
      I3 => huffman_ins_v2_mux_code_white_width(1),
19302 
      O => N449
19303 
    );
19304 
  huffman_ins_v2_hor_code_11_mux000321_G : LUT4
19305 
    generic map(
19306 
      INIT => X"0213"
19307 
    )
19308 
    port map (
19309 
      I0 => huffman_ins_v2_a0_value_2_1510,
19310 
      I1 => huffman_ins_v2_mux_code_black_width(4),
19311 
      I2 => huffman_ins_v2_code_black_width(2),
19312 
      I3 => huffman_ins_v2_code_white_width(2),
19313 
      O => N450
19314 
    );
19315 
  huffman_ins_v2_hor_code_11_mux0003129 : MUXF5
19316 
    port map (
19317 
      I0 => N451,
19318 
      I1 => N452,
19319 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
19320 
      O => huffman_ins_v2_hor_code_11_mux0003129_1831
19321 
    );
19322 
  huffman_ins_v2_hor_code_11_mux0003129_F : LUT4
19323 
    generic map(
19324 
      INIT => X"028A"
19325 
    )
19326 
    port map (
19327 
      I0 => huffman_ins_v2_hor_code_11_mux0003121,
19328 
      I1 => huffman_ins_v2_a0_value_2_1510,
19329 
      I2 => huffman_ins_v2_code_black_width(4),
19330 
      I3 => huffman_ins_v2_code_white_width(4),
19331 
      O => N451
19332 
    );
19333 
  huffman_ins_v2_hor_code_11_mux0003129_G : LUT4
19334 
    generic map(
19335 
      INIT => X"A820"
19336 
    )
19337 
    port map (
19338 
      I0 => huffman_ins_v2_N62,
19339 
      I1 => huffman_ins_v2_a0_value_2_1510,
19340 
      I2 => huffman_ins_v2_code_white(11),
19341 
      I3 => huffman_ins_v2_code_black(11),
19342 
      O => N452
19343 
    );
19344 
  fax4_ins_state_FSM_FFd2_In : MUXF5
19345 
    port map (
19346 
      I0 => N453,
19347 
      I1 => N454,
19348 
      S => fax4_ins_pix_changed_1319,
19349 
      O => fax4_ins_state_FSM_FFd2_In_1328
19350 
    );
19351 
  fax4_ins_state_FSM_FFd2_In_F : LUT4
19352 
    generic map(
19353 
      INIT => X"0C04"
19354 
    )
19355 
    port map (
19356 
      I0 => fax4_ins_EOL,
19357 
      I1 => fax4_ins_state_FSM_FFd2_1327,
19358 
      I2 => fax4_ins_pass_mode,
19359 
      I3 => fax4_ins_EOL_prev_230,
19360 
      O => N453
19361 
    );
19362 
  fax4_ins_state_FSM_FFd2_In_G : LUT3
19363 
    generic map(
19364 
      INIT => X"80"
19365 
    )
19366 
    port map (
19367 
      I0 => fax4_ins_state_FSM_FFd8_1338,
19368 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
19369 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
19370 
      O => N454
19371 
    );
19372 
  huffman_ins_v2_hor_code_16_mux000359 : MUXF5
19373 
    port map (
19374 
      I0 => N455,
19375 
      I1 => N456,
19376 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
19377 
      O => huffman_ins_v2_hor_code_16_mux000359_1900
19378 
    );
19379 
  huffman_ins_v2_hor_code_16_mux000359_F : LUT4
19380 
    generic map(
19381 
      INIT => X"C877"
19382 
    )
19383 
    port map (
19384 
      I0 => huffman_ins_v2_mux_code_white_width(1),
19385 
      I1 => N361,
19386 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_cy(0),
19387 
      I3 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
19388 
      O => N455
19389 
    );
19390 
  huffman_ins_v2_hor_code_16_mux000359_G : LUT4
19391 
    generic map(
19392 
      INIT => X"FFD5"
19393 
    )
19394 
    port map (
19395 
      I0 => huffman_ins_v2_N89,
19396 
      I1 => huffman_ins_v2_N251,
19397 
      I2 => huffman_ins_v2_mux_code_black_width(3),
19398 
      I3 => N12,
19399 
      O => N456
19400 
    );
19401 
  fax4_ins_mode_indicator_o_2_rstpot_SW0 : MUXF5
19402 
    port map (
19403 
      I0 => N457,
19404 
      I1 => N458,
19405 
      S => N167,
19406 
      O => N176
19407 
    );
19408 
  fax4_ins_mode_indicator_o_2_rstpot_SW0_F : LUT3
19409 
    generic map(
19410 
      INIT => X"5D"
19411 
    )
19412 
    port map (
19413 
      I0 => fax4_ins_mode_indicator_o(2),
19414 
      I1 => fax4_ins_EOL_prev_230,
19415 
      I2 => fax4_ins_EOL_prev_prev_231,
19416 
      O => N457
19417 
    );
19418 
  fax4_ins_mode_indicator_o_2_rstpot_SW0_G : LUT4
19419 
    generic map(
19420 
      INIT => X"FF72"
19421 
    )
19422 
    port map (
19423 
      I0 => fax4_ins_EOL_prev_230,
19424 
      I1 => fax4_ins_EOL_prev_prev_231,
19425 
      I2 => fax4_ins_EOL,
19426 
      I3 => fax4_ins_pix_changed_1319,
19427 
      O => N458
19428 
    );
19429 
  fax4_ins_mode_indicator_o_1_rstpot_SW0 : MUXF5
19430 
    port map (
19431 
      I0 => N459,
19432 
      I1 => N460,
19433 
      S => N167,
19434 
      O => N220
19435 
    );
19436 
  fax4_ins_mode_indicator_o_1_rstpot_SW0_F : LUT3
19437 
    generic map(
19438 
      INIT => X"5D"
19439 
    )
19440 
    port map (
19441 
      I0 => fax4_ins_mode_indicator_o(1),
19442 
      I1 => fax4_ins_EOL_prev_230,
19443 
      I2 => fax4_ins_EOL_prev_prev_231,
19444 
      O => N459
19445 
    );
19446 
  fax4_ins_mode_indicator_o_1_rstpot_SW0_G : LUT4
19447 
    generic map(
19448 
      INIT => X"FF72"
19449 
    )
19450 
    port map (
19451 
      I0 => fax4_ins_EOL_prev_230,
19452 
      I1 => fax4_ins_EOL_prev_prev_231,
19453 
      I2 => fax4_ins_EOL,
19454 
      I3 => fax4_ins_pix_changed_1319,
19455 
      O => N460
19456 
    );
19457 
  huffman_ins_v2_hor_code_3_mux000318 : MUXF5
19458 
    port map (
19459 
      I0 => N461,
19460 
      I1 => N462,
19461 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
19462 
      O => huffman_ins_v2_hor_code_3_mux000318_1991
19463 
    );
19464 
  huffman_ins_v2_hor_code_3_mux000318_F : LUT4
19465 
    generic map(
19466 
      INIT => X"FF04"
19467 
    )
19468 
    port map (
19469 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
19470 
      I1 => huffman_ins_v2_hor_code_3_mux00033_1992,
19471 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
19472 
      I3 => huffman_ins_v2_N166,
19473 
      O => N461
19474 
    );
19475 
  huffman_ins_v2_hor_code_3_mux000318_G : LUT4
19476 
    generic map(
19477 
      INIT => X"FF01"
19478 
    )
19479 
    port map (
19480 
      I0 => huffman_ins_v2_mux_code_black_width(3),
19481 
      I1 => huffman_ins_v2_mux_code_black_width(2),
19482 
      I2 => huffman_ins_v2_mux_code_black_width(4),
19483 
      I3 => huffman_ins_v2_N166,
19484 
      O => N462
19485 
    );
19486 
  huffman_ins_v2_hor_code_6_mux000310 : MUXF5
19487 
    port map (
19488 
      I0 => N463,
19489 
      I1 => N464,
19490 
      S => huffman_ins_v2_horizontal_mode_part_2_2065,
19491 
      O => huffman_ins_v2_hor_code_6_mux000310_2014
19492 
    );
19493 
  huffman_ins_v2_hor_code_6_mux000310_F : LUT4
19494 
    generic map(
19495 
      INIT => X"FF01"
19496 
    )
19497 
    port map (
19498 
      I0 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(3),
19499 
      I1 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(2),
19500 
      I2 => huffman_ins_v2_Madd_hor_code_width_addsub0000_lut(4),
19501 
      I3 => huffman_ins_v2_N166,
19502 
      O => N463
19503 
    );
19504 
  huffman_ins_v2_hor_code_6_mux000310_G : LUT4
19505 
    generic map(
19506 
      INIT => X"FF04"
19507 
    )
19508 
    port map (
19509 
      I0 => huffman_ins_v2_mux_code_black_width(4),
19510 
      I1 => huffman_ins_v2_N67,
19511 
      I2 => huffman_ins_v2_mux_code_black_width(3),
19512 
      I3 => huffman_ins_v2_N166,
19513 
      O => N464
19514 
    );
19515 
  huffman_ins_v2_Msub_run_length_white_addsub0000_lut_9_INV_0 : INV
19516 
    port map (
19517 
      I => fax4_ins_a1_o(9),
19518 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(9)
19519 
    );
19520 
  huffman_ins_v2_Msub_run_length_white_addsub0000_lut_8_INV_0 : INV
19521 
    port map (
19522 
      I => fax4_ins_a1_o(8),
19523 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(8)
19524 
    );
19525 
  huffman_ins_v2_Msub_run_length_white_addsub0000_lut_7_INV_0 : INV
19526 
    port map (
19527 
      I => fax4_ins_a1_o(7),
19528 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(7)
19529 
    );
19530 
  huffman_ins_v2_Msub_run_length_white_addsub0000_lut_6_INV_0 : INV
19531 
    port map (
19532 
      I => fax4_ins_a1_o(6),
19533 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(6)
19534 
    );
19535 
  huffman_ins_v2_Msub_run_length_white_addsub0000_lut_5_INV_0 : INV
19536 
    port map (
19537 
      I => fax4_ins_a1_o(5),
19538 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(5)
19539 
    );
19540 
  huffman_ins_v2_Msub_run_length_white_addsub0000_lut_4_INV_0 : INV
19541 
    port map (
19542 
      I => fax4_ins_a1_o(4),
19543 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(4)
19544 
    );
19545 
  huffman_ins_v2_Msub_run_length_white_addsub0000_lut_3_INV_0 : INV
19546 
    port map (
19547 
      I => fax4_ins_a1_o(3),
19548 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(3)
19549 
    );
19550 
  huffman_ins_v2_Msub_run_length_white_addsub0000_lut_2_INV_0 : INV
19551 
    port map (
19552 
      I => fax4_ins_a1_o(2),
19553 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(2)
19554 
    );
19555 
  huffman_ins_v2_Msub_run_length_white_addsub0000_lut_1_INV_0 : INV
19556 
    port map (
19557 
      I => fax4_ins_a1_o(1),
19558 
      O => huffman_ins_v2_Msub_run_length_white_addsub0000_lut(1)
19559 
    );
19560 
  fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_lut_0_INV_0 : INV
19561 
    port map (
19562 
      I => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
19563 
      O => fax4_ins_counter_xy_v2_ins_counter_x_ins_Madd_cnt_addsub0000_lut(0)
19564 
    );
19565 
  fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_lut_0_INV_0 : INV
19566 
    port map (
19567 
      I => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
19568 
      O => fax4_ins_counter_xy_v2_ins_counter_y_ins_Madd_cnt_addsub0000_lut(0)
19569 
    );
19570 
  fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_lut_0_INV_0 : INV
19571 
    port map (
19572 
      I => fax4_ins_FIFO1_multi_read_ins_read_pos(0),
19573 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_read_pos_lut(0)
19574 
    );
19575 
  fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_lut_0_INV_0 : INV
19576 
    port map (
19577 
      I => fax4_ins_FIFO1_multi_read_ins_write_pos(0),
19578 
      O => fax4_ins_FIFO1_multi_read_ins_Mcount_write_pos_lut(0)
19579 
    );
19580 
  fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_lut_0_INV_0 : INV
19581 
    port map (
19582 
      I => fax4_ins_FIFO2_multi_read_ins_read_pos(0),
19583 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_read_pos_lut(0)
19584 
    );
19585 
  fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_lut_0_INV_0 : INV
19586 
    port map (
19587 
      I => fax4_ins_FIFO2_multi_read_ins_write_pos(0),
19588 
      O => fax4_ins_FIFO2_multi_read_ins_Mcount_write_pos_lut(0)
19589 
    );
19590 
  fax4_ins_Madd_fifo_rd_addsub0000_lut_0_INV_0 : INV
19591 
    port map (
19592 
      I => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
19593 
      O => fax4_ins_Madd_fifo_rd_addsub0000_lut(0)
19594 
    );
19595 
  fax4_ins_pclk_not1_INV_0 : INV
19596 
    port map (
19597 
      I => pclk_i,
19598 
      O => fax4_ins_pclk_not
19599 
    );
19600 
  fax4_ins_a1b1_not0000_8_1_INV_0 : INV
19601 
    port map (
19602 
      I => fax4_ins_b1(8),
19603 
      O => fax4_ins_a1b1_not0000_8_Q
19604 
    );
19605 
  fax4_ins_a1b1_not0000_3_1_INV_0 : INV
19606 
    port map (
19607 
      I => fax4_ins_b1(3),
19608 
      O => fax4_ins_a1b1_not0000_3_Q
19609 
    );
19610 
  fax4_ins_a1b1_not0000_2_1_INV_0 : INV
19611 
    port map (
19612 
      I => fax4_ins_b1(2),
19613 
      O => fax4_ins_a1b1_not0000_2_Q
19614 
    );
19615 
  huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001 : RAMB16_S18
19616 
    generic map(
19617 
      WRITE_MODE => "WRITE_FIRST",
19618 
      INIT_02 => X"080A08050804082D082C082B082A08290828081708160815081408130812081B",
19619 
      INIT => X"00000",
19620 
      INIT_00 => X"06350634060306080508050705140513040F040E040C040B0408040706070835",
19621 
      INIT_01 => X"081A08030802071807240713072B07280704070307170708070C0727062B062A",
19622 
      INIT_03 => X"083408330832084B084A085B085A08590858082508240855085408530852080B"
19623 
    )
19624 
    port map (
19625 
      CLK => pclk_i,
19626 
      EN => N1,
19627 
      SSR => NlwRenamedSig_OI_run_len_code_o(26),
19628 
      WE => NlwRenamedSig_OI_run_len_code_o(26),
19629 
      ADDR(9) => NlwRenamedSig_OI_run_len_code_o(26),
19630 
      ADDR(8) => NlwRenamedSig_OI_run_len_code_o(26),
19631 
      ADDR(7) => NlwRenamedSig_OI_run_len_code_o(26),
19632 
      ADDR(6) => NlwRenamedSig_OI_run_len_code_o(26),
19633 
      ADDR(5) => huffman_ins_v2_run_length_white(5),
19634 
      ADDR(4) => huffman_ins_v2_run_length_white(4),
19635 
      ADDR(3) => huffman_ins_v2_run_length_white(3),
19636 
      ADDR(2) => huffman_ins_v2_run_length_white(2),
19637 
      ADDR(1) => huffman_ins_v2_run_length_white(1),
19638 
      ADDR(0) => huffman_ins_v2_run_length_white(0),
19639 
      DI(15) => NlwRenamedSig_OI_run_len_code_o(26),
19640 
      DI(14) => NlwRenamedSig_OI_run_len_code_o(26),
19641 
      DI(13) => NlwRenamedSig_OI_run_len_code_o(26),
19642 
      DI(12) => NlwRenamedSig_OI_run_len_code_o(26),
19643 
      DI(11) => NlwRenamedSig_OI_run_len_code_o(26),
19644 
      DI(10) => NlwRenamedSig_OI_run_len_code_o(26),
19645 
      DI(9) => NlwRenamedSig_OI_run_len_code_o(26),
19646 
      DI(8) => NlwRenamedSig_OI_run_len_code_o(26),
19647 
      DI(7) => NlwRenamedSig_OI_run_len_code_o(26),
19648 
      DI(6) => NlwRenamedSig_OI_run_len_code_o(26),
19649 
      DI(5) => NlwRenamedSig_OI_run_len_code_o(26),
19650 
      DI(4) => NlwRenamedSig_OI_run_len_code_o(26),
19651 
      DI(3) => NlwRenamedSig_OI_run_len_code_o(26),
19652 
      DI(2) => NlwRenamedSig_OI_run_len_code_o(26),
19653 
      DI(1) => NlwRenamedSig_OI_run_len_code_o(26),
19654 
      DI(0) => NlwRenamedSig_OI_run_len_code_o(26),
19655 
      DIP(1) => NlwRenamedSig_OI_run_len_code_o(26),
19656 
      DIP(0) => NlwRenamedSig_OI_run_len_code_o(26),
19657 
      DO(15) => NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DO_15_UNCONNECTED,
19658 
      DO(14) => NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DO_14_UNCONNECTED,
19659 
      DO(13) => NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DO_13_UNCONNECTED,
19660 
      DO(12) => NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DO_12_UNCONNECTED,
19661 
      DO(11) => huffman_ins_v2_codetab_ter_white_width(3),
19662 
      DO(10) => huffman_ins_v2_codetab_ter_white_width(2),
19663 
      DO(9) => huffman_ins_v2_codetab_ter_white_width(1),
19664 
      DO(8) => huffman_ins_v2_codetab_ter_white_width(0),
19665 
      DO(7) => huffman_ins_v2_ter_white_code(7),
19666 
      DO(6) => huffman_ins_v2_ter_white_code(6),
19667 
      DO(5) => huffman_ins_v2_ter_white_code(5),
19668 
      DO(4) => huffman_ins_v2_ter_white_code(4),
19669 
      DO(3) => huffman_ins_v2_ter_white_code(3),
19670 
      DO(2) => huffman_ins_v2_ter_white_code(2),
19671 
      DO(1) => huffman_ins_v2_ter_white_code(1),
19672 
      DO(0) => huffman_ins_v2_ter_white_code(0),
19673 
      DOP(1) => NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DOP_1_UNCONNECTED,
19674 
      DOP(0) => NLW_huffman_ins_v2_code_table_ins_Mrom_white_code_mux0001_DOP_0_UNCONNECTED
19675 
    );
19676 
  huffman_ins_v2_code_table_ins_Mrom_black_code_mux0001 : RAMB16_S18
19677 
    generic map(
19678 
      WRITE_MODE => "WRITE_FIRST",
19679 
      INIT_02 => X"C057C056C055C054C0DBC0DAC06DC06CC0D7C0D6C0D5C0D4C0D3C0D2C06BC06A",
19680 
      INIT => X"00000",
19681 
      INIT_00 => X"901880078004700770057004600460055003400240033003200220033002A037",
19682 
      INIT_01 => X"C069C068C0CDC0CCC0CBC0CAB018B017B028B037B06CB068B067A008A018A017",
19683 
      INIT_03 => X"C067C066C05AC02CC02BC059C058C028C027C038C037C024C053C052C065C064"
19684 
    )
19685 
    port map (
19686 
      CLK => pclk_i,
19687 
      EN => N1,
19688 
      SSR => NlwRenamedSig_OI_run_len_code_o(26),
19689 
      WE => NlwRenamedSig_OI_run_len_code_o(26),
19690 
      ADDR(9) => NlwRenamedSig_OI_run_len_code_o(26),
19691 
      ADDR(8) => NlwRenamedSig_OI_run_len_code_o(26),
19692 
      ADDR(7) => NlwRenamedSig_OI_run_len_code_o(26),
19693 
      ADDR(6) => NlwRenamedSig_OI_run_len_code_o(26),
19694 
      ADDR(5) => huffman_ins_v2_run_length_black(5),
19695 
      ADDR(4) => huffman_ins_v2_run_length_black(4),
19696 
      ADDR(3) => huffman_ins_v2_run_length_black(3),
19697 
      ADDR(2) => huffman_ins_v2_run_length_black(2),
19698 
      ADDR(1) => huffman_ins_v2_run_length_black(1),
19699 
      ADDR(0) => huffman_ins_v2_run_length_black(0),
19700 
      DI(15) => NlwRenamedSig_OI_run_len_code_o(26),
19701 
      DI(14) => NlwRenamedSig_OI_run_len_code_o(26),
19702 
      DI(13) => NlwRenamedSig_OI_run_len_code_o(26),
19703 
      DI(12) => NlwRenamedSig_OI_run_len_code_o(26),
19704 
      DI(11) => NlwRenamedSig_OI_run_len_code_o(26),
19705 
      DI(10) => NlwRenamedSig_OI_run_len_code_o(26),
19706 
      DI(9) => NlwRenamedSig_OI_run_len_code_o(26),
19707 
      DI(8) => NlwRenamedSig_OI_run_len_code_o(26),
19708 
      DI(7) => NlwRenamedSig_OI_run_len_code_o(26),
19709 
      DI(6) => NlwRenamedSig_OI_run_len_code_o(26),
19710 
      DI(5) => NlwRenamedSig_OI_run_len_code_o(26),
19711 
      DI(4) => NlwRenamedSig_OI_run_len_code_o(26),
19712 
      DI(3) => NlwRenamedSig_OI_run_len_code_o(26),
19713 
      DI(2) => NlwRenamedSig_OI_run_len_code_o(26),
19714 
      DI(1) => NlwRenamedSig_OI_run_len_code_o(26),
19715 
      DI(0) => NlwRenamedSig_OI_run_len_code_o(26),
19716 
      DIP(1) => NlwRenamedSig_OI_run_len_code_o(26),
19717 
      DIP(0) => NlwRenamedSig_OI_run_len_code_o(26),
19718 
      DO(15) => huffman_ins_v2_codetab_ter_black_width(3),
19719 
      DO(14) => huffman_ins_v2_codetab_ter_black_width(2),
19720 
      DO(13) => huffman_ins_v2_codetab_ter_black_width(1),
19721 
      DO(12) => huffman_ins_v2_codetab_ter_black_width(0),
19722 
      DO(11) => huffman_ins_v2_ter_black_code(11),
19723 
      DO(10) => huffman_ins_v2_ter_black_code(10),
19724 
      DO(9) => huffman_ins_v2_ter_black_code(9),
19725 
      DO(8) => huffman_ins_v2_ter_black_code(8),
19726 
      DO(7) => huffman_ins_v2_ter_black_code(7),
19727 
      DO(6) => huffman_ins_v2_ter_black_code(6),
19728 
      DO(5) => huffman_ins_v2_ter_black_code(5),
19729 
      DO(4) => huffman_ins_v2_ter_black_code(4),
19730 
      DO(3) => huffman_ins_v2_ter_black_code(3),
19731 
      DO(2) => huffman_ins_v2_ter_black_code(2),
19732 
      DO(1) => huffman_ins_v2_ter_black_code(1),
19733 
      DO(0) => huffman_ins_v2_ter_black_code(0),
19734 
      DOP(1) => NLW_huffman_ins_v2_code_table_ins_Mrom_black_code_mux0001_DOP_1_UNCONNECTED,
19735 
      DOP(0) => NLW_huffman_ins_v2_code_table_ins_Mrom_black_code_mux0001_DOP_0_UNCONNECTED
19736 
    );
19737 
  fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem : RAMB16_S18_S18
19738 
    generic map(
19739 
      WRITE_MODE_A => "READ_FIRST",
19740 
      WRITE_MODE_B => "WRITE_FIRST",
19741 
      INIT_B => X"00000"
19742 
    )
19743 
    port map (
19744 
      CLKA => fax4_ins_pclk_not,
19745 
      CLKB => fax4_ins_pclk_not,
19746 
      ENA => N1,
19747 
      ENB => fax4_ins_FIFO1_multi_read_ins_mem_rd_387,
19748 
      SSRA => NlwRenamedSig_OI_run_len_code_o(26),
19749 
      SSRB => NlwRenamedSig_OI_run_len_code_o(26),
19750 
      WEA => fax4_ins_FIFO1_multi_read_ins_wr_459,
19751 
      WEB => NlwRenamedSig_OI_run_len_code_o(26),
19752 
      ADDRA(9) => fax4_ins_FIFO1_multi_read_ins_write_pos(9),
19753 
      ADDRA(8) => fax4_ins_FIFO1_multi_read_ins_write_pos(8),
19754 
      ADDRA(7) => fax4_ins_FIFO1_multi_read_ins_write_pos(7),
19755 
      ADDRA(6) => fax4_ins_FIFO1_multi_read_ins_write_pos(6),
19756 
      ADDRA(5) => fax4_ins_FIFO1_multi_read_ins_write_pos(5),
19757 
      ADDRA(4) => fax4_ins_FIFO1_multi_read_ins_write_pos(4),
19758 
      ADDRA(3) => fax4_ins_FIFO1_multi_read_ins_write_pos(3),
19759 
      ADDRA(2) => fax4_ins_FIFO1_multi_read_ins_write_pos(2),
19760 
      ADDRA(1) => fax4_ins_FIFO1_multi_read_ins_write_pos(1),
19761 
      ADDRA(0) => fax4_ins_FIFO1_multi_read_ins_write_pos(0),
19762 
      ADDRB(9) => fax4_ins_FIFO1_multi_read_ins_read_pos(9),
19763 
      ADDRB(8) => fax4_ins_FIFO1_multi_read_ins_read_pos(8),
19764 
      ADDRB(7) => fax4_ins_FIFO1_multi_read_ins_read_pos(7),
19765 
      ADDRB(6) => fax4_ins_FIFO1_multi_read_ins_read_pos(6),
19766 
      ADDRB(5) => fax4_ins_FIFO1_multi_read_ins_read_pos(5),
19767 
      ADDRB(4) => fax4_ins_FIFO1_multi_read_ins_read_pos(4),
19768 
      ADDRB(3) => fax4_ins_FIFO1_multi_read_ins_read_pos(3),
19769 
      ADDRB(2) => fax4_ins_FIFO1_multi_read_ins_read_pos(2),
19770 
      ADDRB(1) => fax4_ins_FIFO1_multi_read_ins_read_pos(1),
19771 
      ADDRB(0) => fax4_ins_FIFO1_multi_read_ins_read_pos(0),
19772 
      DIA(15) => NlwRenamedSig_OI_run_len_code_o(26),
19773 
      DIA(14) => NlwRenamedSig_OI_run_len_code_o(26),
19774 
      DIA(13) => NlwRenamedSig_OI_run_len_code_o(26),
19775 
      DIA(12) => NlwRenamedSig_OI_run_len_code_o(26),
19776 
      DIA(11) => NlwRenamedSig_OI_run_len_code_o(26),
19777 
      DIA(10) => fax4_ins_to_white_1349,
19778 
      DIA(9) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
19779 
      DIA(8) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
19780 
      DIA(7) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
19781 
      DIA(6) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
19782 
      DIA(5) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
19783 
      DIA(4) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
19784 
      DIA(3) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
19785 
      DIA(2) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
19786 
      DIA(1) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
19787 
      DIA(0) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
19788 
      DIB(15) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_15_UNCONNECTED,
19789 
      DIB(14) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_14_UNCONNECTED,
19790 
      DIB(13) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_13_UNCONNECTED,
19791 
      DIB(12) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_12_UNCONNECTED,
19792 
      DIB(11) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_11_UNCONNECTED,
19793 
      DIB(10) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_10_UNCONNECTED,
19794 
      DIB(9) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_9_UNCONNECTED,
19795 
      DIB(8) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_8_UNCONNECTED,
19796 
      DIB(7) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_7_UNCONNECTED,
19797 
      DIB(6) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_6_UNCONNECTED,
19798 
      DIB(5) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_5_UNCONNECTED,
19799 
      DIB(4) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_4_UNCONNECTED,
19800 
      DIB(3) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_3_UNCONNECTED,
19801 
      DIB(2) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_2_UNCONNECTED,
19802 
      DIB(1) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_1_UNCONNECTED,
19803 
      DIB(0) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIB_0_UNCONNECTED,
19804 
      DIPA(1) => NlwRenamedSig_OI_run_len_code_o(26),
19805 
      DIPA(0) => NlwRenamedSig_OI_run_len_code_o(26),
19806 
      DIPB(1) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIPB_1_UNCONNECTED,
19807 
      DIPB(0) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DIPB_0_UNCONNECTED,
19808 
      DOA(15) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_15_UNCONNECTED,
19809 
      DOA(14) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_14_UNCONNECTED,
19810 
      DOA(13) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_13_UNCONNECTED,
19811 
      DOA(12) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_12_UNCONNECTED,
19812 
      DOA(11) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_11_UNCONNECTED,
19813 
      DOA(10) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_10_UNCONNECTED,
19814 
      DOA(9) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_9_UNCONNECTED,
19815 
      DOA(8) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_8_UNCONNECTED,
19816 
      DOA(7) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_7_UNCONNECTED,
19817 
      DOA(6) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_6_UNCONNECTED,
19818 
      DOA(5) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_5_UNCONNECTED,
19819 
      DOA(4) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_4_UNCONNECTED,
19820 
      DOA(3) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_3_UNCONNECTED,
19821 
      DOA(2) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_2_UNCONNECTED,
19822 
      DOA(1) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_1_UNCONNECTED,
19823 
      DOA(0) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOA_0_UNCONNECTED,
19824 
      DOPA(1) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOPA_1_UNCONNECTED,
19825 
      DOPA(0) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOPA_0_UNCONNECTED,
19826 
      DOB(15) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOB_15_UNCONNECTED,
19827 
      DOB(14) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOB_14_UNCONNECTED,
19828 
      DOB(13) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOB_13_UNCONNECTED,
19829 
      DOB(12) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOB_12_UNCONNECTED,
19830 
      DOB(11) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOB_11_UNCONNECTED,
19831 
      DOB(10) => fax4_ins_FIFO1_multi_read_ins_mem_data_out(10),
19832 
      DOB(9) => fax4_ins_FIFO1_multi_read_ins_mem_data_out(9),
19833 
      DOB(8) => fax4_ins_FIFO1_multi_read_ins_mem_data_out(8),
19834 
      DOB(7) => fax4_ins_FIFO1_multi_read_ins_mem_data_out(7),
19835 
      DOB(6) => fax4_ins_FIFO1_multi_read_ins_mem_data_out(6),
19836 
      DOB(5) => fax4_ins_FIFO1_multi_read_ins_mem_data_out(5),
19837 
      DOB(4) => fax4_ins_FIFO1_multi_read_ins_mem_data_out(4),
19838 
      DOB(3) => fax4_ins_FIFO1_multi_read_ins_mem_data_out(3),
19839 
      DOB(2) => fax4_ins_FIFO1_multi_read_ins_mem_data_out(2),
19840 
      DOB(1) => fax4_ins_FIFO1_multi_read_ins_mem_data_out(1),
19841 
      DOB(0) => fax4_ins_FIFO1_multi_read_ins_mem_data_out(0),
19842 
      DOPB(1) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOPB_1_UNCONNECTED,
19843 
      DOPB(0) => NLW_fax4_ins_FIFO1_multi_read_ins_RAM_ins_Mram_mem_DOPB_0_UNCONNECTED
19844 
    );
19845 
  fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem : RAMB16_S18_S18
19846 
    generic map(
19847 
      WRITE_MODE_A => "READ_FIRST",
19848 
      WRITE_MODE_B => "WRITE_FIRST",
19849 
      INIT_B => X"00000"
19850 
    )
19851 
    port map (
19852 
      CLKA => fax4_ins_pclk_not,
19853 
      CLKB => fax4_ins_pclk_not,
19854 
      ENA => N1,
19855 
      ENB => fax4_ins_FIFO2_multi_read_ins_mem_rd_628,
19856 
      SSRA => NlwRenamedSig_OI_run_len_code_o(26),
19857 
      SSRB => NlwRenamedSig_OI_run_len_code_o(26),
19858 
      WEA => fax4_ins_FIFO2_multi_read_ins_wr,
19859 
      WEB => NlwRenamedSig_OI_run_len_code_o(26),
19860 
      ADDRA(9) => fax4_ins_FIFO2_multi_read_ins_write_pos(9),
19861 
      ADDRA(8) => fax4_ins_FIFO2_multi_read_ins_write_pos(8),
19862 
      ADDRA(7) => fax4_ins_FIFO2_multi_read_ins_write_pos(7),
19863 
      ADDRA(6) => fax4_ins_FIFO2_multi_read_ins_write_pos(6),
19864 
      ADDRA(5) => fax4_ins_FIFO2_multi_read_ins_write_pos(5),
19865 
      ADDRA(4) => fax4_ins_FIFO2_multi_read_ins_write_pos(4),
19866 
      ADDRA(3) => fax4_ins_FIFO2_multi_read_ins_write_pos(3),
19867 
      ADDRA(2) => fax4_ins_FIFO2_multi_read_ins_write_pos(2),
19868 
      ADDRA(1) => fax4_ins_FIFO2_multi_read_ins_write_pos(1),
19869 
      ADDRA(0) => fax4_ins_FIFO2_multi_read_ins_write_pos(0),
19870 
      ADDRB(9) => fax4_ins_FIFO2_multi_read_ins_read_pos(9),
19871 
      ADDRB(8) => fax4_ins_FIFO2_multi_read_ins_read_pos(8),
19872 
      ADDRB(7) => fax4_ins_FIFO2_multi_read_ins_read_pos(7),
19873 
      ADDRB(6) => fax4_ins_FIFO2_multi_read_ins_read_pos(6),
19874 
      ADDRB(5) => fax4_ins_FIFO2_multi_read_ins_read_pos(5),
19875 
      ADDRB(4) => fax4_ins_FIFO2_multi_read_ins_read_pos(4),
19876 
      ADDRB(3) => fax4_ins_FIFO2_multi_read_ins_read_pos(3),
19877 
      ADDRB(2) => fax4_ins_FIFO2_multi_read_ins_read_pos(2),
19878 
      ADDRB(1) => fax4_ins_FIFO2_multi_read_ins_read_pos(1),
19879 
      ADDRB(0) => fax4_ins_FIFO2_multi_read_ins_read_pos(0),
19880 
      DIA(15) => NlwRenamedSig_OI_run_len_code_o(26),
19881 
      DIA(14) => NlwRenamedSig_OI_run_len_code_o(26),
19882 
      DIA(13) => NlwRenamedSig_OI_run_len_code_o(26),
19883 
      DIA(12) => NlwRenamedSig_OI_run_len_code_o(26),
19884 
      DIA(11) => NlwRenamedSig_OI_run_len_code_o(26),
19885 
      DIA(10) => fax4_ins_to_white_1349,
19886 
      DIA(9) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(9),
19887 
      DIA(8) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(8),
19888 
      DIA(7) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(7),
19889 
      DIA(6) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(6),
19890 
      DIA(5) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(5),
19891 
      DIA(4) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(4),
19892 
      DIA(3) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(3),
19893 
      DIA(2) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(2),
19894 
      DIA(1) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(1),
19895 
      DIA(0) => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_x_ins_cnt(0),
19896 
      DIB(15) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_15_UNCONNECTED,
19897 
      DIB(14) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_14_UNCONNECTED,
19898 
      DIB(13) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_13_UNCONNECTED,
19899 
      DIB(12) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_12_UNCONNECTED,
19900 
      DIB(11) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_11_UNCONNECTED,
19901 
      DIB(10) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_10_UNCONNECTED,
19902 
      DIB(9) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_9_UNCONNECTED,
19903 
      DIB(8) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_8_UNCONNECTED,
19904 
      DIB(7) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_7_UNCONNECTED,
19905 
      DIB(6) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_6_UNCONNECTED,
19906 
      DIB(5) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_5_UNCONNECTED,
19907 
      DIB(4) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_4_UNCONNECTED,
19908 
      DIB(3) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_3_UNCONNECTED,
19909 
      DIB(2) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_2_UNCONNECTED,
19910 
      DIB(1) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_1_UNCONNECTED,
19911 
      DIB(0) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIB_0_UNCONNECTED,
19912 
      DIPA(1) => NlwRenamedSig_OI_run_len_code_o(26),
19913 
      DIPA(0) => NlwRenamedSig_OI_run_len_code_o(26),
19914 
      DIPB(1) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIPB_1_UNCONNECTED,
19915 
      DIPB(0) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DIPB_0_UNCONNECTED,
19916 
      DOA(15) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_15_UNCONNECTED,
19917 
      DOA(14) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_14_UNCONNECTED,
19918 
      DOA(13) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_13_UNCONNECTED,
19919 
      DOA(12) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_12_UNCONNECTED,
19920 
      DOA(11) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_11_UNCONNECTED,
19921 
      DOA(10) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_10_UNCONNECTED,
19922 
      DOA(9) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_9_UNCONNECTED,
19923 
      DOA(8) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_8_UNCONNECTED,
19924 
      DOA(7) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_7_UNCONNECTED,
19925 
      DOA(6) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_6_UNCONNECTED,
19926 
      DOA(5) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_5_UNCONNECTED,
19927 
      DOA(4) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_4_UNCONNECTED,
19928 
      DOA(3) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_3_UNCONNECTED,
19929 
      DOA(2) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_2_UNCONNECTED,
19930 
      DOA(1) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_1_UNCONNECTED,
19931 
      DOA(0) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOA_0_UNCONNECTED,
19932 
      DOPA(1) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOPA_1_UNCONNECTED,
19933 
      DOPA(0) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOPA_0_UNCONNECTED,
19934 
      DOB(15) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOB_15_UNCONNECTED,
19935 
      DOB(14) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOB_14_UNCONNECTED,
19936 
      DOB(13) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOB_13_UNCONNECTED,
19937 
      DOB(12) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOB_12_UNCONNECTED,
19938 
      DOB(11) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOB_11_UNCONNECTED,
19939 
      DOB(10) => fax4_ins_FIFO2_multi_read_ins_mem_data_out(10),
19940 
      DOB(9) => fax4_ins_FIFO2_multi_read_ins_mem_data_out(9),
19941 
      DOB(8) => fax4_ins_FIFO2_multi_read_ins_mem_data_out(8),
19942 
      DOB(7) => fax4_ins_FIFO2_multi_read_ins_mem_data_out(7),
19943 
      DOB(6) => fax4_ins_FIFO2_multi_read_ins_mem_data_out(6),
19944 
      DOB(5) => fax4_ins_FIFO2_multi_read_ins_mem_data_out(5),
19945 
      DOB(4) => fax4_ins_FIFO2_multi_read_ins_mem_data_out(4),
19946 
      DOB(3) => fax4_ins_FIFO2_multi_read_ins_mem_data_out(3),
19947 
      DOB(2) => fax4_ins_FIFO2_multi_read_ins_mem_data_out(2),
19948 
      DOB(1) => fax4_ins_FIFO2_multi_read_ins_mem_data_out(1),
19949 
      DOB(0) => fax4_ins_FIFO2_multi_read_ins_mem_data_out(0),
19950 
      DOPB(1) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOPB_1_UNCONNECTED,
19951 
      DOPB(0) => NLW_fax4_ins_FIFO2_multi_read_ins_RAM_ins_Mram_mem_DOPB_0_UNCONNECTED
19952 
    );
19953 
  huffman_ins_v2_code_white_4_mux0000281 : LUT4
19954 
    generic map(
19955 
      INIT => X"F888"
19956 
    )
19957 
    port map (
19958 
      I0 => huffman_ins_v2_code_white(4),
19959 
      I1 => huffman_ins_v2_code_white_8_or0000,
19960 
      I2 => huffman_ins_v2_ter_white_code(4),
19961 
      I3 => huffman_ins_v2_code_white_4_mux000016_1765,
19962 
      O => huffman_ins_v2_code_white_4_mux0000281_1767
19963 
    );
19964 
  huffman_ins_v2_code_white_4_mux0000282 : LUT4
19965 
    generic map(
19966 
      INIT => X"F888"
19967 
    )
19968 
    port map (
19969 
      I0 => huffman_ins_v2_code_white(4),
19970 
      I1 => huffman_ins_v2_code_white_8_or0000,
19971 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(0),
19972 
      I3 => huffman_ins_v2_code_white_4_mux000016_1765,
19973 
      O => huffman_ins_v2_code_white_4_mux0000282_1768
19974 
    );
19975 
  huffman_ins_v2_code_white_4_mux000028_f5 : MUXF5
19976 
    port map (
19977 
      I0 => huffman_ins_v2_code_white_4_mux0000282_1768,
19978 
      I1 => huffman_ins_v2_code_white_4_mux0000281_1767,
19979 
      S => huffman_ins_v2_codetab_ter_white_width(0),
19980 
      O => huffman_ins_v2_code_white_4_mux000028
19981 
    );
19982 
  huffman_ins_v2_code_white_5_mux0000281 : LUT4
19983 
    generic map(
19984 
      INIT => X"F888"
19985 
    )
19986 
    port map (
19987 
      I0 => huffman_ins_v2_code_white(5),
19988 
      I1 => huffman_ins_v2_code_white_8_or0000,
19989 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(0),
19990 
      I3 => huffman_ins_v2_code_white_4_mux000016_1765,
19991 
      O => huffman_ins_v2_code_white_5_mux0000281_1772
19992 
    );
19993 
  huffman_ins_v2_code_white_5_mux0000282 : LUT4
19994 
    generic map(
19995 
      INIT => X"F888"
19996 
    )
19997 
    port map (
19998 
      I0 => huffman_ins_v2_code_white(5),
19999 
      I1 => huffman_ins_v2_code_white_8_or0000,
20000 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(1),
20001 
      I3 => huffman_ins_v2_code_white_4_mux000016_1765,
20002 
      O => huffman_ins_v2_code_white_5_mux0000282_1773
20003 
    );
20004 
  huffman_ins_v2_code_white_5_mux000028_f5 : MUXF5
20005 
    port map (
20006 
      I0 => huffman_ins_v2_code_white_5_mux0000282_1773,
20007 
      I1 => huffman_ins_v2_code_white_5_mux0000281_1772,
20008 
      S => huffman_ins_v2_codetab_ter_white_width(0),
20009 
      O => huffman_ins_v2_code_white_5_mux000028
20010 
    );
20011 
  huffman_ins_v2_hor_code_9_mux0003661 : LUT4
20012 
    generic map(
20013 
      INIT => X"C080"
20014 
    )
20015 
    port map (
20016 
      I0 => huffman_ins_v2_N62,
20017 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
20018 
      I2 => huffman_ins_v2_code_black(9),
20019 
      I3 => huffman_ins_v2_N87,
20020 
      O => huffman_ins_v2_hor_code_9_mux0003661_2047
20021 
    );
20022 
  huffman_ins_v2_hor_code_9_mux0003662 : LUT4
20023 
    generic map(
20024 
      INIT => X"C080"
20025 
    )
20026 
    port map (
20027 
      I0 => huffman_ins_v2_N62,
20028 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
20029 
      I2 => huffman_ins_v2_code_white(9),
20030 
      I3 => huffman_ins_v2_N87,
20031 
      O => huffman_ins_v2_hor_code_9_mux0003662_2048
20032 
    );
20033 
  huffman_ins_v2_hor_code_9_mux000366_f5 : MUXF5
20034 
    port map (
20035 
      I0 => huffman_ins_v2_hor_code_9_mux0003662_2048,
20036 
      I1 => huffman_ins_v2_hor_code_9_mux0003661_2047,
20037 
      S => huffman_ins_v2_a0_value_2_1510,
20038 
      O => huffman_ins_v2_hor_code_9_mux000366
20039 
    );
20040 
  huffman_ins_v2_code_black_6_mux000021551 : LUT4
20041 
    generic map(
20042 
      INIT => X"EC4C"
20043 
    )
20044 
    port map (
20045 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
20046 
      I1 => huffman_ins_v2_ter_black_code(6),
20047 
      I2 => N319,
20048 
      I3 => huffman_ins_v2_code_black(6),
20049 
      O => huffman_ins_v2_code_black_6_mux00002155
20050 
    );
20051 
  huffman_ins_v2_code_black_6_mux00002155_f5 : MUXF5
20052 
    port map (
20053 
      I0 => huffman_ins_v2_code_black_6_mux00002126_1652,
20054 
      I1 => huffman_ins_v2_code_black_6_mux00002155,
20055 
      S => huffman_ins_v2_codetab_ter_black_width(3),
20056 
      O => huffman_ins_v2_code_black_6_mux0000
20057 
    );
20058 
  huffman_ins_v2_code_black_9_mux00002431 : LUT4
20059 
    generic map(
20060 
      INIT => X"0E04"
20061 
    )
20062 
    port map (
20063 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
20064 
      I1 => huffman_ins_v2_ter_black_code(9),
20065 
      I2 => huffman_ins_v2_codetab_ter_black_width(1),
20066 
      I3 => huffman_ins_v2_code_black(9),
20067 
      O => huffman_ins_v2_code_black_9_mux00002431_1672
20068 
    );
20069 
  huffman_ins_v2_code_black_9_mux00002432 : LUT2
20070 
    generic map(
20071 
      INIT => X"2"
20072 
    )
20073 
    port map (
20074 
      I0 => huffman_ins_v2_code_black_11_mux0000_bdd0,
20075 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
20076 
      O => huffman_ins_v2_code_black_9_mux00002432_1673
20077 
    );
20078 
  huffman_ins_v2_code_black_9_mux0000243_f5 : MUXF5
20079 
    port map (
20080 
      I0 => huffman_ins_v2_code_black_9_mux00002432_1673,
20081 
      I1 => huffman_ins_v2_code_black_9_mux00002431_1672,
20082 
      S => huffman_ins_v2_codetab_ter_black_width(2),
20083 
      O => huffman_ins_v2_code_black_9_mux0000243
20084 
    );
20085 
  huffman_ins_v2_code_black_15_mux00001431 : LUT4
20086 
    generic map(
20087 
      INIT => X"0E04"
20088 
    )
20089 
    port map (
20090 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
20091 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_3_Q,
20092 
      I2 => huffman_ins_v2_codetab_ter_black_width(1),
20093 
      I3 => huffman_ins_v2_code_black(15),
20094 
      O => huffman_ins_v2_code_black_15_mux00001431_1566
20095 
    );
20096 
  huffman_ins_v2_code_black_15_mux00001432 : LUT2
20097 
    generic map(
20098 
      INIT => X"2"
20099 
    )
20100 
    port map (
20101 
      I0 => huffman_ins_v2_code_black_11_mux0000_bdd5,
20102 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
20103 
      O => huffman_ins_v2_code_black_15_mux00001432_1567
20104 
    );
20105 
  huffman_ins_v2_code_black_15_mux0000143_f5 : MUXF5
20106 
    port map (
20107 
      I0 => huffman_ins_v2_code_black_15_mux00001432_1567,
20108 
      I1 => huffman_ins_v2_code_black_15_mux00001431_1566,
20109 
      S => huffman_ins_v2_codetab_ter_black_width(2),
20110 
      O => huffman_ins_v2_code_black_15_mux0000143
20111 
    );
20112 
  huffman_ins_v2_code_black_14_mux00001431 : LUT4
20113 
    generic map(
20114 
      INIT => X"0E04"
20115 
    )
20116 
    port map (
20117 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
20118 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_2_Q,
20119 
      I2 => huffman_ins_v2_codetab_ter_black_width(1),
20120 
      I3 => huffman_ins_v2_code_black(14),
20121 
      O => huffman_ins_v2_code_black_14_mux00001431_1557
20122 
    );
20123 
  huffman_ins_v2_code_black_14_mux00001432 : LUT2
20124 
    generic map(
20125 
      INIT => X"2"
20126 
    )
20127 
    port map (
20128 
      I0 => huffman_ins_v2_code_black_10_mux0000_bdd5,
20129 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
20130 
      O => huffman_ins_v2_code_black_14_mux00001432_1558
20131 
    );
20132 
  huffman_ins_v2_code_black_14_mux0000143_f5 : MUXF5
20133 
    port map (
20134 
      I0 => huffman_ins_v2_code_black_14_mux00001432_1558,
20135 
      I1 => huffman_ins_v2_code_black_14_mux00001431_1557,
20136 
      S => huffman_ins_v2_codetab_ter_black_width(2),
20137 
      O => huffman_ins_v2_code_black_14_mux0000143
20138 
    );
20139 
  huffman_ins_v2_code_black_13_mux00001431 : LUT4
20140 
    generic map(
20141 
      INIT => X"0E04"
20142 
    )
20143 
    port map (
20144 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
20145 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_1_Q,
20146 
      I2 => huffman_ins_v2_codetab_ter_black_width(1),
20147 
      I3 => huffman_ins_v2_code_black(13),
20148 
      O => huffman_ins_v2_code_black_13_mux00001431_1550
20149 
    );
20150 
  huffman_ins_v2_code_black_13_mux00001432 : LUT2
20151 
    generic map(
20152 
      INIT => X"2"
20153 
    )
20154 
    port map (
20155 
      I0 => huffman_ins_v2_code_black_11_mux0000_bdd3,
20156 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
20157 
      O => huffman_ins_v2_code_black_13_mux00001432_1551
20158 
    );
20159 
  huffman_ins_v2_code_black_13_mux0000143_f5 : MUXF5
20160 
    port map (
20161 
      I0 => huffman_ins_v2_code_black_13_mux00001432_1551,
20162 
      I1 => huffman_ins_v2_code_black_13_mux00001431_1550,
20163 
      S => huffman_ins_v2_codetab_ter_black_width(2),
20164 
      O => huffman_ins_v2_code_black_13_mux0000143
20165 
    );
20166 
  huffman_ins_v2_code_black_12_mux00001431 : LUT4
20167 
    generic map(
20168 
      INIT => X"0E04"
20169 
    )
20170 
    port map (
20171 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
20172 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_0_Q,
20173 
      I2 => huffman_ins_v2_codetab_ter_black_width(1),
20174 
      I3 => huffman_ins_v2_code_black(12),
20175 
      O => huffman_ins_v2_code_black_12_mux00001431_1543
20176 
    );
20177 
  huffman_ins_v2_code_black_12_mux00001432 : LUT2
20178 
    generic map(
20179 
      INIT => X"2"
20180 
    )
20181 
    port map (
20182 
      I0 => huffman_ins_v2_code_black_10_mux0000_bdd3,
20183 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
20184 
      O => huffman_ins_v2_code_black_12_mux00001432_1544
20185 
    );
20186 
  huffman_ins_v2_code_black_12_mux0000143_f5 : MUXF5
20187 
    port map (
20188 
      I0 => huffman_ins_v2_code_black_12_mux00001432_1544,
20189 
      I1 => huffman_ins_v2_code_black_12_mux00001431_1543,
20190 
      S => huffman_ins_v2_codetab_ter_black_width(2),
20191 
      O => huffman_ins_v2_code_black_12_mux0000143
20192 
    );
20193 
  huffman_ins_v2_code_black_11_mux00001431 : LUT4
20194 
    generic map(
20195 
      INIT => X"0E04"
20196 
    )
20197 
    port map (
20198 
      I0 => huffman_ins_v2_codetab_ter_black_width(0),
20199 
      I1 => huffman_ins_v2_ter_black_code(11),
20200 
      I2 => huffman_ins_v2_codetab_ter_black_width(1),
20201 
      I3 => huffman_ins_v2_code_black(11),
20202 
      O => huffman_ins_v2_code_black_11_mux00001431_1532
20203 
    );
20204 
  huffman_ins_v2_code_black_11_mux00001432 : LUT2
20205 
    generic map(
20206 
      INIT => X"2"
20207 
    )
20208 
    port map (
20209 
      I0 => huffman_ins_v2_code_black_11_mux0000_bdd2,
20210 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
20211 
      O => huffman_ins_v2_code_black_11_mux00001432_1533
20212 
    );
20213 
  huffman_ins_v2_code_black_11_mux0000143_f5 : MUXF5
20214 
    port map (
20215 
      I0 => huffman_ins_v2_code_black_11_mux00001432_1533,
20216 
      I1 => huffman_ins_v2_code_black_11_mux00001431_1532,
20217 
      S => huffman_ins_v2_codetab_ter_black_width(2),
20218 
      O => huffman_ins_v2_code_black_11_mux0000143
20219 
    );
20220 
  huffman_ins_v2_code_black_10_mux00001521 : LUT4
20221 
    generic map(
20222 
      INIT => X"FA72"
20223 
    )
20224 
    port map (
20225 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
20226 
      I1 => huffman_ins_v2_codetab_ter_black_width(0),
20227 
      I2 => huffman_ins_v2_code_black_10_mux0000_bdd2,
20228 
      I3 => huffman_ins_v2_code_black(10),
20229 
      O => huffman_ins_v2_code_black_10_mux00001521_1521
20230 
    );
20231 
  huffman_ins_v2_code_black_10_mux00001522 : LUT4
20232 
    generic map(
20233 
      INIT => X"E444"
20234 
    )
20235 
    port map (
20236 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
20237 
      I1 => huffman_ins_v2_code_black_10_mux0000_bdd2,
20238 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
20239 
      I3 => huffman_ins_v2_code_black(10),
20240 
      O => huffman_ins_v2_code_black_10_mux00001522_1522
20241 
    );
20242 
  huffman_ins_v2_code_black_10_mux0000152_f5 : MUXF5
20243 
    port map (
20244 
      I0 => huffman_ins_v2_code_black_10_mux00001522_1522,
20245 
      I1 => huffman_ins_v2_code_black_10_mux00001521_1521,
20246 
      S => huffman_ins_v2_ter_black_code(10),
20247 
      O => huffman_ins_v2_code_black_10_mux0000152
20248 
    );
20249 
  fax4_ins_FIFO2_multi_read_ins_wr1 : LUT4
20250 
    generic map(
20251 
      INIT => X"FFEA"
20252 
    )
20253 
    port map (
20254 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(2),
20255 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(1),
20256 
      I2 => fax4_ins_FIFO2_multi_read_ins_used(0),
20257 
      I3 => fax4_ins_FIFO2_multi_read_ins_N4,
20258 
      O => fax4_ins_FIFO2_multi_read_ins_wr1_702
20259 
    );
20260 
  fax4_ins_FIFO2_multi_read_ins_wr_f5 : MUXF5
20261 
    port map (
20262 
      I0 => NlwRenamedSig_OI_run_len_code_o(26),
20263 
      I1 => fax4_ins_FIFO2_multi_read_ins_wr1_702,
20264 
      S => fax4_ins_fifo2_wr,
20265 
      O => fax4_ins_FIFO2_multi_read_ins_wr
20266 
    );
20267 
  huffman_ins_v2_run_length_white_0_1 : LUT4
20268 
    generic map(
20269 
      INIT => X"F5B1"
20270 
    )
20271 
    port map (
20272 
      I0 => huffman_ins_v2_run_length_white_and0000,
20273 
      I1 => fax4_ins_a0_value_o_950,
20274 
      I2 => huffman_ins_v2_run_length_white_addsub0000(0),
20275 
      I3 => huffman_ins_v2_run_length_white_sub0000(0),
20276 
      O => huffman_ins_v2_run_length_white_0_1_2094
20277 
    );
20278 
  huffman_ins_v2_run_length_white_0_2 : LUT4
20279 
    generic map(
20280 
      INIT => X"EC20"
20281 
    )
20282 
    port map (
20283 
      I0 => huffman_ins_v2_run_length_white_sub0000(0),
20284 
      I1 => huffman_ins_v2_run_length_white_and0000,
20285 
      I2 => fax4_ins_a0_value_o_950,
20286 
      I3 => huffman_ins_v2_run_length_white_addsub0000(0),
20287 
      O => huffman_ins_v2_run_length_white_0_2_2095
20288 
    );
20289 
  huffman_ins_v2_run_length_white_0_f5 : MUXF5
20290 
    port map (
20291 
      I0 => huffman_ins_v2_run_length_white_0_2_2095,
20292 
      I1 => huffman_ins_v2_run_length_white_0_1_2094,
20293 
      S => huffman_ins_v2_run_length_white_sub0001(0),
20294 
      O => huffman_ins_v2_run_length_white(0)
20295 
    );
20296 
  fax4_ins_FIFO2_multi_read_ins_mux3_and00001 : LUT4
20297 
    generic map(
20298 
      INIT => X"0010"
20299 
    )
20300 
    port map (
20301 
      I0 => fax4_ins_FIFO2_multi_read_ins_used(2),
20302 
      I1 => fax4_ins_FIFO2_multi_read_ins_used(0),
20303 
      I2 => fax4_ins_FIFO2_multi_read_ins_used(1),
20304 
      I3 => fax4_ins_FIFO2_multi_read_ins_N4,
20305 
      O => fax4_ins_FIFO2_multi_read_ins_mux3_and0000
20306 
    );
20307 
  fax4_ins_FIFO2_multi_read_ins_mux3_and0000_f5 : MUXF5
20308 
    port map (
20309 
      I0 => NlwRenamedSig_OI_run_len_code_o(26),
20310 
      I1 => fax4_ins_FIFO2_multi_read_ins_mux3_and0000,
20311 
      S => fax4_ins_fifo2_wr,
20312 
      O => fax4_ins_FIFO2_multi_read_ins_mux3
20313 
    );
20314 
  huffman_ins_v2_hor_code_17_mux000315311 : LUT4
20315 
    generic map(
20316 
      INIT => X"A820"
20317 
    )
20318 
    port map (
20319 
      I0 => huffman_ins_v2_hor_code(17),
20320 
      I1 => huffman_ins_v2_horizontal_mode_part_2_2065,
20321 
      I2 => huffman_ins_v2_hor_code_17_mux0003110_1904,
20322 
      I3 => huffman_ins_v2_hor_code_17_mux000371_1911,
20323 
      O => huffman_ins_v2_hor_code_17_mux00031531
20324 
    );
20325 
  huffman_ins_v2_hor_code_17_mux00031531_f5 : MUXF5
20326 
    port map (
20327 
      I0 => huffman_ins_v2_hor_code_17_mux00031531,
20328 
      I1 => huffman_ins_v2_hor_code(17),
20329 
      S => huffman_ins_v2_hor_code_17_mux000378_1912,
20330 
      O => huffman_ins_v2_hor_code_17_mux0003153
20331 
    );
20332 
  fax4_ins_b1_mux0004_8_421 : LUT3
20333 
    generic map(
20334 
      INIT => X"E4"
20335 
    )
20336 
    port map (
20337 
      I0 => fax4_ins_mux_b1(0),
20338 
      I1 => fax4_ins_fifo_out_prev1_x(8),
20339 
      I2 => fax4_ins_fifo_out_prev2_x(8),
20340 
      O => fax4_ins_b1_mux0004_8_42
20341 
    );
20342 
  fax4_ins_b1_mux0004_8_422 : LUT3
20343 
    generic map(
20344 
      INIT => X"E4"
20345 
    )
20346 
    port map (
20347 
      I0 => fax4_ins_mux_b1(0),
20348 
      I1 => fax4_ins_b1_mux0004_8_12_1049,
20349 
      I2 => fax4_ins_fifo_out_prev2_x(8),
20350 
      O => fax4_ins_b1_mux0004_8_421_1051
20351 
    );
20352 
  fax4_ins_b1_mux0004_8_42_f5 : MUXF5
20353 
    port map (
20354 
      I0 => fax4_ins_b1_mux0004_8_421_1051,
20355 
      I1 => fax4_ins_b1_mux0004_8_42,
20356 
      S => fax4_ins_mux_b1(1),
20357 
      O => fax4_ins_b1_mux0004(8)
20358 
    );
20359 
  fax4_ins_b1_mux0004_3_421 : LUT3
20360 
    generic map(
20361 
      INIT => X"E4"
20362 
    )
20363 
    port map (
20364 
      I0 => fax4_ins_mux_b1(0),
20365 
      I1 => fax4_ins_fifo_out_prev1_x(3),
20366 
      I2 => fax4_ins_fifo_out_prev2_x(3),
20367 
      O => fax4_ins_b1_mux0004_3_42
20368 
    );
20369 
  fax4_ins_b1_mux0004_3_422 : LUT3
20370 
    generic map(
20371 
      INIT => X"E4"
20372 
    )
20373 
    port map (
20374 
      I0 => fax4_ins_mux_b1(0),
20375 
      I1 => fax4_ins_b1_mux0004_3_12_1037,
20376 
      I2 => fax4_ins_fifo_out_prev2_x(3),
20377 
      O => fax4_ins_b1_mux0004_3_421_1039
20378 
    );
20379 
  fax4_ins_b1_mux0004_3_42_f5 : MUXF5
20380 
    port map (
20381 
      I0 => fax4_ins_b1_mux0004_3_421_1039,
20382 
      I1 => fax4_ins_b1_mux0004_3_42,
20383 
      S => fax4_ins_mux_b1(1),
20384 
      O => fax4_ins_b1_mux0004(3)
20385 
    );
20386 
  fax4_ins_b1_mux0004_2_421 : LUT3
20387 
    generic map(
20388 
      INIT => X"E4"
20389 
    )
20390 
    port map (
20391 
      I0 => fax4_ins_mux_b1(0),
20392 
      I1 => fax4_ins_fifo_out_prev1_x(2),
20393 
      I2 => fax4_ins_fifo_out_prev2_x(2),
20394 
      O => fax4_ins_b1_mux0004_2_42
20395 
    );
20396 
  fax4_ins_b1_mux0004_2_422 : LUT3
20397 
    generic map(
20398 
      INIT => X"E4"
20399 
    )
20400 
    port map (
20401 
      I0 => fax4_ins_mux_b1(0),
20402 
      I1 => fax4_ins_b1_mux0004_2_12_1033,
20403 
      I2 => fax4_ins_fifo_out_prev2_x(2),
20404 
      O => fax4_ins_b1_mux0004_2_421_1035
20405 
    );
20406 
  fax4_ins_b1_mux0004_2_42_f5 : MUXF5
20407 
    port map (
20408 
      I0 => fax4_ins_b1_mux0004_2_421_1035,
20409 
      I1 => fax4_ins_b1_mux0004_2_42,
20410 
      S => fax4_ins_mux_b1(1),
20411 
      O => fax4_ins_b1_mux0004(2)
20412 
    );
20413 
  fax4_ins_b1_mux0004_1_421 : LUT3
20414 
    generic map(
20415 
      INIT => X"E4"
20416 
    )
20417 
    port map (
20418 
      I0 => fax4_ins_mux_b1(0),
20419 
      I1 => fax4_ins_fifo_out_prev1_x(1),
20420 
      I2 => fax4_ins_fifo_out_prev2_x(1),
20421 
      O => fax4_ins_b1_mux0004_1_42
20422 
    );
20423 
  fax4_ins_b1_mux0004_1_422 : LUT3
20424 
    generic map(
20425 
      INIT => X"E4"
20426 
    )
20427 
    port map (
20428 
      I0 => fax4_ins_mux_b1(0),
20429 
      I1 => fax4_ins_b1_mux0004_1_12_1029,
20430 
      I2 => fax4_ins_fifo_out_prev2_x(1),
20431 
      O => fax4_ins_b1_mux0004_1_421_1031
20432 
    );
20433 
  fax4_ins_b1_mux0004_1_42_f5 : MUXF5
20434 
    port map (
20435 
      I0 => fax4_ins_b1_mux0004_1_421_1031,
20436 
      I1 => fax4_ins_b1_mux0004_1_42,
20437 
      S => fax4_ins_mux_b1(1),
20438 
      O => fax4_ins_b1_mux0004(1)
20439 
    );
20440 
  huffman_ins_v2_hor_code_15_mux0003551 : LUT4
20441 
    generic map(
20442 
      INIT => X"EC20"
20443 
    )
20444 
    port map (
20445 
      I0 => huffman_ins_v2_code_black(15),
20446 
      I1 => huffman_ins_v2_a0_value_2_1510,
20447 
      I2 => huffman_ins_v2_code_black_width(4),
20448 
      I3 => huffman_ins_v2_code_white(15),
20449 
      O => huffman_ins_v2_hor_code_15_mux0003551_1890
20450 
    );
20451 
  huffman_ins_v2_hor_code_15_mux0003552 : LUT3
20452 
    generic map(
20453 
      INIT => X"08"
20454 
    )
20455 
    port map (
20456 
      I0 => huffman_ins_v2_code_black_width(4),
20457 
      I1 => huffman_ins_v2_code_black(15),
20458 
      I2 => huffman_ins_v2_a0_value_2_1510,
20459 
      O => huffman_ins_v2_hor_code_15_mux0003552_1891
20460 
    );
20461 
  huffman_ins_v2_hor_code_15_mux000355_f5 : MUXF5
20462 
    port map (
20463 
      I0 => huffman_ins_v2_hor_code_15_mux0003552_1891,
20464 
      I1 => huffman_ins_v2_hor_code_15_mux0003551_1890,
20465 
      S => huffman_ins_v2_code_white_width(4),
20466 
      O => huffman_ins_v2_hor_code_15_mux000355
20467 
    );
20468 
  huffman_ins_v2_run_length_white_9_1 : LUT4
20469 
    generic map(
20470 
      INIT => X"F5B1"
20471 
    )
20472 
    port map (
20473 
      I0 => huffman_ins_v2_run_length_white_and0000,
20474 
      I1 => fax4_ins_a0_value_o_950,
20475 
      I2 => huffman_ins_v2_run_length_white_addsub0000(9),
20476 
      I3 => huffman_ins_v2_run_length_white_sub0000(9),
20477 
      O => huffman_ins_v2_run_length_white_9_1_2121
20478 
    );
20479 
  huffman_ins_v2_run_length_white_9_2 : LUT4
20480 
    generic map(
20481 
      INIT => X"EC20"
20482 
    )
20483 
    port map (
20484 
      I0 => huffman_ins_v2_run_length_white_sub0000(9),
20485 
      I1 => huffman_ins_v2_run_length_white_and0000,
20486 
      I2 => fax4_ins_a0_value_o_950,
20487 
      I3 => huffman_ins_v2_run_length_white_addsub0000(9),
20488 
      O => huffman_ins_v2_run_length_white_9_2_2122
20489 
    );
20490 
  huffman_ins_v2_run_length_white_9_f5 : MUXF5
20491 
    port map (
20492 
      I0 => huffman_ins_v2_run_length_white_9_2_2122,
20493 
      I1 => huffman_ins_v2_run_length_white_9_1_2121,
20494 
      S => huffman_ins_v2_run_length_white_sub0001(9),
20495 
      O => huffman_ins_v2_run_length_white(9)
20496 
    );
20497 
  huffman_ins_v2_run_length_white_8_1 : LUT4
20498 
    generic map(
20499 
      INIT => X"F5B1"
20500 
    )
20501 
    port map (
20502 
      I0 => huffman_ins_v2_run_length_white_and0000,
20503 
      I1 => fax4_ins_a0_value_o_950,
20504 
      I2 => huffman_ins_v2_run_length_white_addsub0000(8),
20505 
      I3 => huffman_ins_v2_run_length_white_sub0000(8),
20506 
      O => huffman_ins_v2_run_length_white_8_1_2118
20507 
    );
20508 
  huffman_ins_v2_run_length_white_8_2 : LUT4
20509 
    generic map(
20510 
      INIT => X"EC20"
20511 
    )
20512 
    port map (
20513 
      I0 => huffman_ins_v2_run_length_white_sub0000(8),
20514 
      I1 => huffman_ins_v2_run_length_white_and0000,
20515 
      I2 => fax4_ins_a0_value_o_950,
20516 
      I3 => huffman_ins_v2_run_length_white_addsub0000(8),
20517 
      O => huffman_ins_v2_run_length_white_8_2_2119
20518 
    );
20519 
  huffman_ins_v2_run_length_white_8_f5 : MUXF5
20520 
    port map (
20521 
      I0 => huffman_ins_v2_run_length_white_8_2_2119,
20522 
      I1 => huffman_ins_v2_run_length_white_8_1_2118,
20523 
      S => huffman_ins_v2_run_length_white_sub0001(8),
20524 
      O => huffman_ins_v2_run_length_white(8)
20525 
    );
20526 
  huffman_ins_v2_run_length_white_7_1 : LUT4
20527 
    generic map(
20528 
      INIT => X"F5B1"
20529 
    )
20530 
    port map (
20531 
      I0 => huffman_ins_v2_run_length_white_and0000,
20532 
      I1 => fax4_ins_a0_value_o_950,
20533 
      I2 => huffman_ins_v2_run_length_white_addsub0000(7),
20534 
      I3 => huffman_ins_v2_run_length_white_sub0000(7),
20535 
      O => huffman_ins_v2_run_length_white_7_1_2115
20536 
    );
20537 
  huffman_ins_v2_run_length_white_7_2 : LUT4
20538 
    generic map(
20539 
      INIT => X"EC20"
20540 
    )
20541 
    port map (
20542 
      I0 => huffman_ins_v2_run_length_white_sub0000(7),
20543 
      I1 => huffman_ins_v2_run_length_white_and0000,
20544 
      I2 => fax4_ins_a0_value_o_950,
20545 
      I3 => huffman_ins_v2_run_length_white_addsub0000(7),
20546 
      O => huffman_ins_v2_run_length_white_7_2_2116
20547 
    );
20548 
  huffman_ins_v2_run_length_white_7_f5 : MUXF5
20549 
    port map (
20550 
      I0 => huffman_ins_v2_run_length_white_7_2_2116,
20551 
      I1 => huffman_ins_v2_run_length_white_7_1_2115,
20552 
      S => huffman_ins_v2_run_length_white_sub0001(7),
20553 
      O => huffman_ins_v2_run_length_white(7)
20554 
    );
20555 
  huffman_ins_v2_run_length_white_6_1 : LUT4
20556 
    generic map(
20557 
      INIT => X"F5B1"
20558 
    )
20559 
    port map (
20560 
      I0 => huffman_ins_v2_run_length_white_and0000,
20561 
      I1 => fax4_ins_a0_value_o_950,
20562 
      I2 => huffman_ins_v2_run_length_white_addsub0000(6),
20563 
      I3 => huffman_ins_v2_run_length_white_sub0000(6),
20564 
      O => huffman_ins_v2_run_length_white_6_1_2112
20565 
    );
20566 
  huffman_ins_v2_run_length_white_6_2 : LUT4
20567 
    generic map(
20568 
      INIT => X"EC20"
20569 
    )
20570 
    port map (
20571 
      I0 => huffman_ins_v2_run_length_white_sub0000(6),
20572 
      I1 => huffman_ins_v2_run_length_white_and0000,
20573 
      I2 => fax4_ins_a0_value_o_950,
20574 
      I3 => huffman_ins_v2_run_length_white_addsub0000(6),
20575 
      O => huffman_ins_v2_run_length_white_6_2_2113
20576 
    );
20577 
  huffman_ins_v2_run_length_white_6_f5 : MUXF5
20578 
    port map (
20579 
      I0 => huffman_ins_v2_run_length_white_6_2_2113,
20580 
      I1 => huffman_ins_v2_run_length_white_6_1_2112,
20581 
      S => huffman_ins_v2_run_length_white_sub0001(6),
20582 
      O => huffman_ins_v2_run_length_white(6)
20583 
    );
20584 
  huffman_ins_v2_run_length_white_5_1 : LUT4
20585 
    generic map(
20586 
      INIT => X"F5B1"
20587 
    )
20588 
    port map (
20589 
      I0 => huffman_ins_v2_run_length_white_and0000,
20590 
      I1 => fax4_ins_a0_value_o_950,
20591 
      I2 => huffman_ins_v2_run_length_white_addsub0000(5),
20592 
      I3 => huffman_ins_v2_run_length_white_sub0000(5),
20593 
      O => huffman_ins_v2_run_length_white_5_1_2109
20594 
    );
20595 
  huffman_ins_v2_run_length_white_5_2 : LUT4
20596 
    generic map(
20597 
      INIT => X"EC20"
20598 
    )
20599 
    port map (
20600 
      I0 => huffman_ins_v2_run_length_white_sub0000(5),
20601 
      I1 => huffman_ins_v2_run_length_white_and0000,
20602 
      I2 => fax4_ins_a0_value_o_950,
20603 
      I3 => huffman_ins_v2_run_length_white_addsub0000(5),
20604 
      O => huffman_ins_v2_run_length_white_5_2_2110
20605 
    );
20606 
  huffman_ins_v2_run_length_white_5_f5 : MUXF5
20607 
    port map (
20608 
      I0 => huffman_ins_v2_run_length_white_5_2_2110,
20609 
      I1 => huffman_ins_v2_run_length_white_5_1_2109,
20610 
      S => huffman_ins_v2_run_length_white_sub0001(5),
20611 
      O => huffman_ins_v2_run_length_white(5)
20612 
    );
20613 
  huffman_ins_v2_run_length_white_4_1 : LUT4
20614 
    generic map(
20615 
      INIT => X"F5B1"
20616 
    )
20617 
    port map (
20618 
      I0 => huffman_ins_v2_run_length_white_and0000,
20619 
      I1 => fax4_ins_a0_value_o_950,
20620 
      I2 => huffman_ins_v2_run_length_white_addsub0000(4),
20621 
      I3 => huffman_ins_v2_run_length_white_sub0000(4),
20622 
      O => huffman_ins_v2_run_length_white_4_1_2106
20623 
    );
20624 
  huffman_ins_v2_run_length_white_4_2 : LUT4
20625 
    generic map(
20626 
      INIT => X"EC20"
20627 
    )
20628 
    port map (
20629 
      I0 => huffman_ins_v2_run_length_white_sub0000(4),
20630 
      I1 => huffman_ins_v2_run_length_white_and0000,
20631 
      I2 => fax4_ins_a0_value_o_950,
20632 
      I3 => huffman_ins_v2_run_length_white_addsub0000(4),
20633 
      O => huffman_ins_v2_run_length_white_4_2_2107
20634 
    );
20635 
  huffman_ins_v2_run_length_white_4_f5 : MUXF5
20636 
    port map (
20637 
      I0 => huffman_ins_v2_run_length_white_4_2_2107,
20638 
      I1 => huffman_ins_v2_run_length_white_4_1_2106,
20639 
      S => huffman_ins_v2_run_length_white_sub0001(4),
20640 
      O => huffman_ins_v2_run_length_white(4)
20641 
    );
20642 
  huffman_ins_v2_run_length_white_3_1 : LUT4
20643 
    generic map(
20644 
      INIT => X"F5B1"
20645 
    )
20646 
    port map (
20647 
      I0 => huffman_ins_v2_run_length_white_and0000,
20648 
      I1 => fax4_ins_a0_value_o_950,
20649 
      I2 => huffman_ins_v2_run_length_white_addsub0000(3),
20650 
      I3 => huffman_ins_v2_run_length_white_sub0000(3),
20651 
      O => huffman_ins_v2_run_length_white_3_1_2103
20652 
    );
20653 
  huffman_ins_v2_run_length_white_3_2 : LUT4
20654 
    generic map(
20655 
      INIT => X"EC20"
20656 
    )
20657 
    port map (
20658 
      I0 => huffman_ins_v2_run_length_white_sub0000(3),
20659 
      I1 => huffman_ins_v2_run_length_white_and0000,
20660 
      I2 => fax4_ins_a0_value_o_950,
20661 
      I3 => huffman_ins_v2_run_length_white_addsub0000(3),
20662 
      O => huffman_ins_v2_run_length_white_3_2_2104
20663 
    );
20664 
  huffman_ins_v2_run_length_white_3_f5 : MUXF5
20665 
    port map (
20666 
      I0 => huffman_ins_v2_run_length_white_3_2_2104,
20667 
      I1 => huffman_ins_v2_run_length_white_3_1_2103,
20668 
      S => huffman_ins_v2_run_length_white_sub0001(3),
20669 
      O => huffman_ins_v2_run_length_white(3)
20670 
    );
20671 
  huffman_ins_v2_run_length_white_2_1 : LUT4
20672 
    generic map(
20673 
      INIT => X"F5B1"
20674 
    )
20675 
    port map (
20676 
      I0 => huffman_ins_v2_run_length_white_and0000,
20677 
      I1 => fax4_ins_a0_value_o_950,
20678 
      I2 => huffman_ins_v2_run_length_white_addsub0000(2),
20679 
      I3 => huffman_ins_v2_run_length_white_sub0000(2),
20680 
      O => huffman_ins_v2_run_length_white_2_1_2100
20681 
    );
20682 
  huffman_ins_v2_run_length_white_2_2 : LUT4
20683 
    generic map(
20684 
      INIT => X"EC20"
20685 
    )
20686 
    port map (
20687 
      I0 => huffman_ins_v2_run_length_white_sub0000(2),
20688 
      I1 => huffman_ins_v2_run_length_white_and0000,
20689 
      I2 => fax4_ins_a0_value_o_950,
20690 
      I3 => huffman_ins_v2_run_length_white_addsub0000(2),
20691 
      O => huffman_ins_v2_run_length_white_2_2_2101
20692 
    );
20693 
  huffman_ins_v2_run_length_white_2_f5 : MUXF5
20694 
    port map (
20695 
      I0 => huffman_ins_v2_run_length_white_2_2_2101,
20696 
      I1 => huffman_ins_v2_run_length_white_2_1_2100,
20697 
      S => huffman_ins_v2_run_length_white_sub0001(2),
20698 
      O => huffman_ins_v2_run_length_white(2)
20699 
    );
20700 
  huffman_ins_v2_run_length_white_1_1 : LUT4
20701 
    generic map(
20702 
      INIT => X"F5B1"
20703 
    )
20704 
    port map (
20705 
      I0 => huffman_ins_v2_run_length_white_and0000,
20706 
      I1 => fax4_ins_a0_value_o_950,
20707 
      I2 => huffman_ins_v2_run_length_white_addsub0000(1),
20708 
      I3 => huffman_ins_v2_run_length_white_sub0000(1),
20709 
      O => huffman_ins_v2_run_length_white_1_1_2097
20710 
    );
20711 
  huffman_ins_v2_run_length_white_1_2 : LUT4
20712 
    generic map(
20713 
      INIT => X"EC20"
20714 
    )
20715 
    port map (
20716 
      I0 => huffman_ins_v2_run_length_white_sub0000(1),
20717 
      I1 => huffman_ins_v2_run_length_white_and0000,
20718 
      I2 => fax4_ins_a0_value_o_950,
20719 
      I3 => huffman_ins_v2_run_length_white_addsub0000(1),
20720 
      O => huffman_ins_v2_run_length_white_1_2_2098
20721 
    );
20722 
  huffman_ins_v2_run_length_white_1_f5 : MUXF5
20723 
    port map (
20724 
      I0 => huffman_ins_v2_run_length_white_1_2_2098,
20725 
      I1 => huffman_ins_v2_run_length_white_1_1_2097,
20726 
      S => huffman_ins_v2_run_length_white_sub0001(1),
20727 
      O => huffman_ins_v2_run_length_white(1)
20728 
    );
20729 
  huffman_ins_v2_code_black_15_mux000011071 : LUT4
20730 
    generic map(
20731 
      INIT => X"FFE2"
20732 
    )
20733 
    port map (
20734 
      I0 => huffman_ins_v2_code_black(15),
20735 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
20736 
      I2 => huffman_ins_v2_codetab_ter_black_width(0),
20737 
      I3 => huffman_ins_v2_codetab_ter_black_width(2),
20738 
      O => huffman_ins_v2_code_black_15_mux000011071_1562
20739 
    );
20740 
  huffman_ins_v2_code_black_15_mux000011072 : LUT3
20741 
    generic map(
20742 
      INIT => X"10"
20743 
    )
20744 
    port map (
20745 
      I0 => huffman_ins_v2_codetab_ter_black_width(2),
20746 
      I1 => huffman_ins_v2_codetab_ter_black_width(1),
20747 
      I2 => huffman_ins_v2_code_black(15),
20748 
      O => huffman_ins_v2_code_black_15_mux000011072_1563
20749 
    );
20750 
  huffman_ins_v2_code_black_15_mux00001107_f5 : MUXF5
20751 
    port map (
20752 
      I0 => huffman_ins_v2_code_black_15_mux000011072_1563,
20753 
      I1 => huffman_ins_v2_code_black_15_mux000011071_1562,
20754 
      S => huffman_ins_v2_code_table_ins_makeup_black_8_Q,
20755 
      O => huffman_ins_v2_code_black_15_mux00001107
20756 
    );
20757 
  huffman_ins_v2_Madd_code_white_width_add0000_xor_3_111 : LUT4
20758 
    generic map(
20759 
      INIT => X"9996"
20760 
    )
20761 
    port map (
20762 
      I0 => huffman_ins_v2_code_table_ins_makeup_white(12),
20763 
      I1 => huffman_ins_v2_codetab_ter_white_width(3),
20764 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(11),
20765 
      I3 => huffman_ins_v2_codetab_ter_white_width(2),
20766 
      O => huffman_ins_v2_Madd_code_white_width_add0000_xor_3_11
20767 
    );
20768 
  huffman_ins_v2_Madd_code_white_width_add0000_xor_3_112 : LUT4
20769 
    generic map(
20770 
      INIT => X"9666"
20771 
    )
20772 
    port map (
20773 
      I0 => huffman_ins_v2_code_table_ins_makeup_white(12),
20774 
      I1 => huffman_ins_v2_codetab_ter_white_width(3),
20775 
      I2 => huffman_ins_v2_code_table_ins_makeup_white(11),
20776 
      I3 => huffman_ins_v2_codetab_ter_white_width(2),
20777 
      O => huffman_ins_v2_Madd_code_white_width_add0000_xor_3_111_1383
20778 
    );
20779 
  huffman_ins_v2_Madd_code_white_width_add0000_xor_3_11_f5 : MUXF5
20780 
    port map (
20781 
      I0 => huffman_ins_v2_Madd_code_white_width_add0000_xor_3_111_1383,
20782 
      I1 => huffman_ins_v2_Madd_code_white_width_add0000_xor_3_11,
20783 
      S => huffman_ins_v2_Madd_code_white_width_add0000_cy_1_Q,
20784 
      O => huffman_ins_v2_code_white_width_add0000(3)
20785 
    );
20786 
  huffman_ins_v2_Madd_code_black_width_add0000_xor_3_111 : LUT4
20787 
    generic map(
20788 
      INIT => X"9996"
20789 
    )
20790 
    port map (
20791 
      I0 => huffman_ins_v2_code_table_ins_makeup_black_16_Q,
20792 
      I1 => huffman_ins_v2_codetab_ter_black_width(3),
20793 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_15_Q,
20794 
      I3 => huffman_ins_v2_codetab_ter_black_width(2),
20795 
      O => huffman_ins_v2_Madd_code_black_width_add0000_xor_3_11
20796 
    );
20797 
  huffman_ins_v2_Madd_code_black_width_add0000_xor_3_112 : LUT4
20798 
    generic map(
20799 
      INIT => X"9666"
20800 
    )
20801 
    port map (
20802 
      I0 => huffman_ins_v2_code_table_ins_makeup_black_16_Q,
20803 
      I1 => huffman_ins_v2_codetab_ter_black_width(3),
20804 
      I2 => huffman_ins_v2_code_table_ins_makeup_black_15_Q,
20805 
      I3 => huffman_ins_v2_codetab_ter_black_width(2),
20806 
      O => huffman_ins_v2_Madd_code_black_width_add0000_xor_3_111_1376
20807 
    );
20808 
  huffman_ins_v2_Madd_code_black_width_add0000_xor_3_11_f5 : MUXF5
20809 
    port map (
20810 
      I0 => huffman_ins_v2_Madd_code_black_width_add0000_xor_3_111_1376,
20811 
      I1 => huffman_ins_v2_Madd_code_black_width_add0000_xor_3_11,
20812 
      S => huffman_ins_v2_Madd_code_black_width_add0000_cy_1_Q,
20813 
      O => huffman_ins_v2_code_black_width_add0000(3)
20814 
    );
20815 
  huffman_ins_v2_Madd_code_white_width_add0000_cy_3_11 : LUT4
20816 
    generic map(
20817 
      INIT => X"FEA8"
20818 
    )
20819 
    port map (
20820 
      I0 => huffman_ins_v2_code_table_ins_makeup_white(12),
20821 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(11),
20822 
      I2 => huffman_ins_v2_codetab_ter_white_width(2),
20823 
      I3 => huffman_ins_v2_codetab_ter_white_width(3),
20824 
      O => huffman_ins_v2_Madd_code_white_width_add0000_cy_3_1
20825 
    );
20826 
  huffman_ins_v2_Madd_code_white_width_add0000_cy_3_12 : LUT4
20827 
    generic map(
20828 
      INIT => X"EA80"
20829 
    )
20830 
    port map (
20831 
      I0 => huffman_ins_v2_code_table_ins_makeup_white(12),
20832 
      I1 => huffman_ins_v2_code_table_ins_makeup_white(11),
20833 
      I2 => huffman_ins_v2_codetab_ter_white_width(2),
20834 
      I3 => huffman_ins_v2_codetab_ter_white_width(3),
20835 
      O => huffman_ins_v2_Madd_code_white_width_add0000_cy_3_11_1380
20836 
    );
20837 
  huffman_ins_v2_Madd_code_white_width_add0000_cy_3_1_f5 : MUXF5
20838 
    port map (
20839 
      I0 => huffman_ins_v2_Madd_code_white_width_add0000_cy_3_11_1380,
20840 
      I1 => huffman_ins_v2_Madd_code_white_width_add0000_cy_3_1,
20841 
      S => huffman_ins_v2_Madd_code_white_width_add0000_cy_1_Q,
20842 
      O => huffman_ins_v2_Madd_code_white_width_add0000_cy_3_Q
20843 
    );
20844 
  huffman_ins_v2_Madd_code_black_width_add0000_cy_3_11 : LUT4
20845 
    generic map(
20846 
      INIT => X"FEA8"
20847 
    )
20848 
    port map (
20849 
      I0 => huffman_ins_v2_code_table_ins_makeup_black_16_Q,
20850 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_15_Q,
20851 
      I2 => huffman_ins_v2_codetab_ter_black_width(2),
20852 
      I3 => huffman_ins_v2_codetab_ter_black_width(3),
20853 
      O => huffman_ins_v2_Madd_code_black_width_add0000_cy_3_1
20854 
    );
20855 
  huffman_ins_v2_Madd_code_black_width_add0000_cy_3_12 : LUT4
20856 
    generic map(
20857 
      INIT => X"EA80"
20858 
    )
20859 
    port map (
20860 
      I0 => huffman_ins_v2_code_table_ins_makeup_black_16_Q,
20861 
      I1 => huffman_ins_v2_code_table_ins_makeup_black_15_Q,
20862 
      I2 => huffman_ins_v2_codetab_ter_black_width(2),
20863 
      I3 => huffman_ins_v2_codetab_ter_black_width(3),
20864 
      O => huffman_ins_v2_Madd_code_black_width_add0000_cy_3_11_1373
20865 
    );
20866 
  huffman_ins_v2_Madd_code_black_width_add0000_cy_3_1_f5 : MUXF5
20867 
    port map (
20868 
      I0 => huffman_ins_v2_Madd_code_black_width_add0000_cy_3_11_1373,
20869 
      I1 => huffman_ins_v2_Madd_code_black_width_add0000_cy_3_1,
20870 
      S => huffman_ins_v2_Madd_code_black_width_add0000_cy_1_Q,
20871 
      O => huffman_ins_v2_Madd_code_black_width_add0000_cy_3_Q
20872 
    );
20873 
  fax4_ins_output_valid_o_mux0003151 : LUT4
20874 
    generic map(
20875 
      INIT => X"FF72"
20876 
    )
20877 
    port map (
20878 
      I0 => fax4_ins_EOL_prev_230,
20879 
      I1 => fax4_ins_EOL_prev_prev_231,
20880 
      I2 => fax4_ins_EOL,
20881 
      I3 => fax4_ins_pix_changed_1319,
20882 
      O => fax4_ins_output_valid_o_mux0003151_1313
20883 
    );
20884 
  fax4_ins_output_valid_o_mux000315_f5 : MUXF5
20885 
    port map (
20886 
      I0 => NlwRenamedSig_OI_run_len_code_o(26),
20887 
      I1 => fax4_ins_output_valid_o_mux0003151_1313,
20888 
      S => fax4_ins_state_FSM_FFd8_1338,
20889 
      O => fax4_ins_output_valid_o_mux000315
20890 
    );
20891 
  fax4_ins_mode_indicator_o_2_rstpot_SW11 : LUT3
20892 
    generic map(
20893 
      INIT => X"1F"
20894 
    )
20895 
    port map (
20896 
      I0 => fax4_ins_a1b1(1),
20897 
      I1 => fax4_ins_a1b1(0),
20898 
      I2 => fax4_ins_N15,
20899 
      O => fax4_ins_mode_indicator_o_2_rstpot_SW1
20900 
    );
20901 
  fax4_ins_mode_indicator_o_2_rstpot_SW12 : LUT2
20902 
    generic map(
20903 
      INIT => X"1"
20904 
    )
20905 
    port map (
20906 
      I0 => fax4_ins_mode_indicator_o(2),
20907 
      I1 => fax4_ins_pass_mode,
20908 
      O => fax4_ins_mode_indicator_o_2_rstpot_SW11_1293
20909 
    );
20910 
  fax4_ins_mode_indicator_o_2_rstpot_SW1_f5 : MUXF5
20911 
    port map (
20912 
      I0 => fax4_ins_mode_indicator_o_2_rstpot_SW11_1293,
20913 
      I1 => fax4_ins_mode_indicator_o_2_rstpot_SW1,
20914 
      S => fax4_ins_load_a1_or0001,
20915 
      O => N177
20916 
    );
20917 
  huffman_ins_v2_run_length_white_and00007 : LUT3_L
20918 
    generic map(
20919 
      INIT => X"10"
20920 
    )
20921 
    port map (
20922 
      I0 => fax4_ins_a0_o(9),
20923 
      I1 => fax4_ins_a0_o(5),
20924 
      I2 => fax4_ins_a0_value_o_950,
20925 
      LO => huffman_ins_v2_run_length_white_and00007_2136
20926 
    );
20927 
  huffman_ins_v2_run_length_black_7_1 : LUT3_D
20928 
    generic map(
20929 
      INIT => X"E4"
20930 
    )
20931 
    port map (
20932 
      I0 => fax4_ins_a0_value_o_950,
20933 
      I1 => huffman_ins_v2_run_length_white_sub0000(7),
20934 
      I2 => huffman_ins_v2_run_length_white_sub0001(7),
20935 
      LO => N465,
20936 
      O => huffman_ins_v2_run_length_black(7)
20937 
    );
20938 
  fax4_ins_b2_mux0004_1_11 : LUT4_D
20939 
    generic map(
20940 
      INIT => X"1000"
20941 
    )
20942 
    port map (
20943 
      I0 => fax4_ins_b2_to_white_and0000,
20944 
      I1 => fax4_ins_b2_to_white_and0001,
20945 
      I2 => fax4_ins_fifo_out2_valid,
20946 
      I3 => fax4_ins_mux_b1(2),
20947 
      LO => N466,
20948 
      O => fax4_ins_N13
20949 
    );
20950 
  fax4_ins_b1_mux0004_7_18 : LUT4_L
20951 
    generic map(
20952 
      INIT => X"0E04"
20953 
    )
20954 
    port map (
20955 
      I0 => fax4_ins_mux_b1(2),
20956 
      I1 => fax4_ins_fifo_out2_x(7),
20957 
      I2 => fax4_ins_mux_b1(1),
20958 
      I3 => fax4_ins_fifo_out1_x(7),
20959 
      LO => fax4_ins_b1_mux0004_7_18_1047
20960 
    );
20961 
  fax4_ins_b1_mux0004_6_18 : LUT4_L
20962 
    generic map(
20963 
      INIT => X"0E04"
20964 
    )
20965 
    port map (
20966 
      I0 => fax4_ins_mux_b1(2),
20967 
      I1 => fax4_ins_fifo_out2_x(6),
20968 
      I2 => fax4_ins_mux_b1(1),
20969 
      I3 => fax4_ins_fifo_out1_x(6),
20970 
      LO => fax4_ins_b1_mux0004_6_18_1045
20971 
    );
20972 
  fax4_ins_b1_mux0004_5_18 : LUT4_L
20973 
    generic map(
20974 
      INIT => X"0E04"
20975 
    )
20976 
    port map (
20977 
      I0 => fax4_ins_mux_b1(2),
20978 
      I1 => fax4_ins_fifo_out2_x(5),
20979 
      I2 => fax4_ins_mux_b1(1),
20980 
      I3 => fax4_ins_fifo_out1_x(5),
20981 
      LO => fax4_ins_b1_mux0004_5_18_1043
20982 
    );
20983 
  fax4_ins_b1_mux0004_4_18 : LUT4_L
20984 
    generic map(
20985 
      INIT => X"0E04"
20986 
    )
20987 
    port map (
20988 
      I0 => fax4_ins_mux_b1(2),
20989 
      I1 => fax4_ins_fifo_out2_x(4),
20990 
      I2 => fax4_ins_mux_b1(1),
20991 
      I3 => fax4_ins_fifo_out1_x(4),
20992 
      LO => fax4_ins_b1_mux0004_4_18_1041
20993 
    );
20994 
  fax4_ins_b1_mux0004_0_18 : LUT4_L
20995 
    generic map(
20996 
      INIT => X"0E04"
20997 
    )
20998 
    port map (
20999 
      I0 => fax4_ins_mux_b1(2),
21000 
      I1 => fax4_ins_fifo_out2_x(0),
21001 
      I2 => fax4_ins_mux_b1(1),
21002 
      I3 => fax4_ins_fifo_out1_x(0),
21003 
      LO => fax4_ins_b1_mux0004_0_18_1027
21004 
    );
21005 
  fax4_ins_b2_mux0004_9_10 : LUT4_L
21006 
    generic map(
21007 
      INIT => X"EC20"
21008 
    )
21009 
    port map (
21010 
      I0 => fax4_ins_fifo_out1_x(9),
21011 
      I1 => fax4_ins_b2_to_white_and0000,
21012 
      I2 => fax4_ins_b2_to_white_and0001,
21013 
      I3 => fax4_ins_fifo_out_prev1_x(9),
21014 
      LO => fax4_ins_b2_mux0004_9_10_1092
21015 
    );
21016 
  fax4_ins_b2_mux0004_8_10 : LUT4_L
21017 
    generic map(
21018 
      INIT => X"EC20"
21019 
    )
21020 
    port map (
21021 
      I0 => fax4_ins_fifo_out1_x(8),
21022 
      I1 => fax4_ins_b2_to_white_and0000,
21023 
      I2 => fax4_ins_b2_to_white_and0001,
21024 
      I3 => fax4_ins_fifo_out_prev1_x(8),
21025 
      LO => fax4_ins_b2_mux0004_8_10_1089
21026 
    );
21027 
  fax4_ins_b2_mux0004_7_10 : LUT4_L
21028 
    generic map(
21029 
      INIT => X"EC20"
21030 
    )
21031 
    port map (
21032 
      I0 => fax4_ins_fifo_out1_x(7),
21033 
      I1 => fax4_ins_b2_to_white_and0000,
21034 
      I2 => fax4_ins_b2_to_white_and0001,
21035 
      I3 => fax4_ins_fifo_out_prev1_x(7),
21036 
      LO => fax4_ins_b2_mux0004_7_10_1086
21037 
    );
21038 
  fax4_ins_b2_mux0004_6_10 : LUT4_L
21039 
    generic map(
21040 
      INIT => X"EC20"
21041 
    )
21042 
    port map (
21043 
      I0 => fax4_ins_fifo_out1_x(6),
21044 
      I1 => fax4_ins_b2_to_white_and0000,
21045 
      I2 => fax4_ins_b2_to_white_and0001,
21046 
      I3 => fax4_ins_fifo_out_prev1_x(6),
21047 
      LO => fax4_ins_b2_mux0004_6_10_1083
21048 
    );
21049 
  fax4_ins_b2_mux0004_5_10 : LUT4_L
21050 
    generic map(
21051 
      INIT => X"EC20"
21052 
    )
21053 
    port map (
21054 
      I0 => fax4_ins_fifo_out1_x(5),
21055 
      I1 => fax4_ins_b2_to_white_and0000,
21056 
      I2 => fax4_ins_b2_to_white_and0001,
21057 
      I3 => fax4_ins_fifo_out_prev1_x(5),
21058 
      LO => fax4_ins_b2_mux0004_5_10_1080
21059 
    );
21060 
  fax4_ins_b2_mux0004_4_10 : LUT4_L
21061 
    generic map(
21062 
      INIT => X"EC20"
21063 
    )
21064 
    port map (
21065 
      I0 => fax4_ins_fifo_out1_x(4),
21066 
      I1 => fax4_ins_b2_to_white_and0000,
21067 
      I2 => fax4_ins_b2_to_white_and0001,
21068 
      I3 => fax4_ins_fifo_out_prev1_x(4),
21069 
      LO => fax4_ins_b2_mux0004_4_10_1077
21070 
    );
21071 
  fax4_ins_b2_mux0004_3_10 : LUT4_L
21072 
    generic map(
21073 
      INIT => X"EC20"
21074 
    )
21075 
    port map (
21076 
      I0 => fax4_ins_fifo_out1_x(3),
21077 
      I1 => fax4_ins_b2_to_white_and0000,
21078 
      I2 => fax4_ins_b2_to_white_and0001,
21079 
      I3 => fax4_ins_fifo_out_prev1_x(3),
21080 
      LO => fax4_ins_b2_mux0004_3_10_1074
21081 
    );
21082 
  fax4_ins_b2_mux0004_2_10 : LUT4_L
21083 
    generic map(
21084 
      INIT => X"EC20"
21085 
    )
21086 
    port map (
21087 
      I0 => fax4_ins_fifo_out1_x(2),
21088 
      I1 => fax4_ins_b2_to_white_and0000,
21089 
      I2 => fax4_ins_b2_to_white_and0001,
21090 
      I3 => fax4_ins_fifo_out_prev1_x(2),
21091 
      LO => fax4_ins_b2_mux0004_2_10_1071
21092 
    );
21093 
  fax4_ins_b2_mux0004_1_10 : LUT4_L
21094 
    generic map(
21095 
      INIT => X"EC20"
21096 
    )
21097 
    port map (
21098 
      I0 => fax4_ins_fifo_out1_x(1),
21099 
      I1 => fax4_ins_b2_to_white_and0000,
21100 
      I2 => fax4_ins_b2_to_white_and0001,
21101 
      I3 => fax4_ins_fifo_out_prev1_x(1),
21102 
      LO => fax4_ins_b2_mux0004_1_10_1068
21103 
    );
21104 
  fax4_ins_fifo_rd0 : LUT2_D
21105 
    generic map(
21106 
      INIT => X"E"
21107 
    )
21108 
    port map (
21109 
      I0 => fax4_ins_state_FSM_FFd10_1323,
21110 
      I1 => fax4_ins_state_FSM_FFd2_1327,
21111 
      LO => N467,
21112 
      O => fax4_ins_fifo_rd0_1266
21113 
    );
21114 
  fax4_ins_fifo_rd3 : LUT3_D
21115 
    generic map(
21116 
      INIT => X"FE"
21117 
    )
21118 
    port map (
21119 
      I0 => fax4_ins_state_FSM_FFd8_1338,
21120 
      I1 => fax4_ins_state_FSM_FFd5_1333,
21121 
      I2 => fax4_ins_state_FSM_FFd6_1336,
21122 
      LO => N468,
21123 
      O => fax4_ins_fifo_rd3_1268
21124 
    );
21125 
  fax4_ins_mode_indicator_o_mux0001_2_341 : LUT4_D
21126 
    generic map(
21127 
      INIT => X"8000"
21128 
    )
21129 
    port map (
21130 
      I0 => fax4_ins_a1b1(7),
21131 
      I1 => fax4_ins_a1b1(6),
21132 
      I2 => fax4_ins_a1b1(5),
21133 
      I3 => fax4_ins_a1b1(4),
21134 
      LO => N469,
21135 
      O => fax4_ins_mode_indicator_o_mux0001_2_341_1299
21136 
    );
21137 
  fax4_ins_mode_indicator_o_mux0001_2_3111 : LUT4_D
21138 
    generic map(
21139 
      INIT => X"8000"
21140 
    )
21141 
    port map (
21142 
      I0 => fax4_ins_a1b1(9),
21143 
      I1 => fax4_ins_a1b1(8),
21144 
      I2 => fax4_ins_a1b1(10),
21145 
      I3 => fax4_ins_mode_indicator_o_mux0001_2_36_1300,
21146 
      LO => N470,
21147 
      O => fax4_ins_mode_indicator_o_mux0001_2_3111_1298
21148 
    );
21149 
  fax4_ins_vertical_mode_cmp_le00002199 : LUT4_D
21150 
    generic map(
21151 
      INIT => X"EAAA"
21152 
    )
21153 
    port map (
21154 
      I0 => fax4_ins_vertical_mode_cmp_le000020_1361,
21155 
      I1 => fax4_ins_vertical_mode_cmp_le0000213_1363,
21156 
      I2 => fax4_ins_vertical_mode_cmp_le0000226_1365,
21157 
      I3 => fax4_ins_vertical_mode_cmp_le00002169_1364,
21158 
      LO => N471,
21159 
      O => fax4_ins_vertical_mode_cmp_le0000
21160 
    );
21161 
  fax4_ins_vertical_mode_cmp_le0000281 : LUT4_L
21162 
    generic map(
21163 
      INIT => X"F0F1"
21164 
    )
21165 
    port map (
21166 
      I0 => fax4_ins_a1b1(8),
21167 
      I1 => fax4_ins_a1b1(9),
21168 
      I2 => fax4_ins_a1b1(10),
21169 
      I3 => N113,
21170 
      LO => fax4_ins_vertical_mode_cmp_le0000281_1367
21171 
    );
21172 
  fax4_ins_a0_mux0000_9_SW0_SW0 : LUT4_D
21173 
    generic map(
21174 
      INIT => X"1DDD"
21175 
    )
21176 
    port map (
21177 
      I0 => fax4_ins_a1_o_mux0000(9),
21178 
      I1 => fax4_ins_N20,
21179 
      I2 => fax4_ins_pass_mode,
21180 
      I3 => fax4_ins_b2(0),
21181 
      LO => N472,
21182 
      O => N117
21183 
    );
21184 
  fax4_ins_a0_mux0000_5_SW0_SW0 : LUT4_D
21185 
    generic map(
21186 
      INIT => X"1DDD"
21187 
    )
21188 
    port map (
21189 
      I0 => fax4_ins_a1_o_mux0000(5),
21190 
      I1 => fax4_ins_N20,
21191 
      I2 => fax4_ins_pass_mode,
21192 
      I3 => fax4_ins_b2(4),
21193 
      LO => N473,
21194 
      O => N119
21195 
    );
21196 
  fax4_ins_a0_mux0000_4_SW0_SW0 : LUT4_D
21197 
    generic map(
21198 
      INIT => X"1DDD"
21199 
    )
21200 
    port map (
21201 
      I0 => fax4_ins_a1_o_mux0000(4),
21202 
      I1 => fax4_ins_N20,
21203 
      I2 => fax4_ins_pass_mode,
21204 
      I3 => fax4_ins_b2(5),
21205 
      LO => N474,
21206 
      O => N121
21207 
    );
21208 
  fax4_ins_a0_mux0000_3_SW0_SW0 : LUT4_D
21209 
    generic map(
21210 
      INIT => X"1DDD"
21211 
    )
21212 
    port map (
21213 
      I0 => fax4_ins_a1_o_mux0000(3),
21214 
      I1 => fax4_ins_N20,
21215 
      I2 => fax4_ins_pass_mode,
21216 
      I3 => fax4_ins_b2(6),
21217 
      LO => N475,
21218 
      O => N123
21219 
    );
21220 
  fax4_ins_a0_mux0000_2_SW0_SW0 : LUT4_D
21221 
    generic map(
21222 
      INIT => X"1DDD"
21223 
    )
21224 
    port map (
21225 
      I0 => fax4_ins_a1_o_mux0000(2),
21226 
      I1 => fax4_ins_N20,
21227 
      I2 => fax4_ins_pass_mode,
21228 
      I3 => fax4_ins_b2(7),
21229 
      LO => N476,
21230 
      O => N125
21231 
    );
21232 
  fax4_ins_a0_mux0000_0_SW0_SW0 : LUT4_D
21233 
    generic map(
21234 
      INIT => X"1DDD"
21235 
    )
21236 
    port map (
21237 
      I0 => fax4_ins_a1_o_mux0000(0),
21238 
      I1 => fax4_ins_N20,
21239 
      I2 => fax4_ins_pass_mode,
21240 
      I3 => fax4_ins_b2(9),
21241 
      LO => N477,
21242 
      O => N127
21243 
    );
21244 
  fax4_ins_a1b1_6_1 : LUT4_D
21245 
    generic map(
21246 
      INIT => X"EC4C"
21247 
    )
21248 
    port map (
21249 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
21250 
      I1 => fax4_ins_a1b1_addsub0001(6),
21251 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
21252 
      I3 => fax4_ins_a1b1_addsub0000(6),
21253 
      LO => N478,
21254 
      O => fax4_ins_a1b1(6)
21255 
    );
21256 
  fax4_ins_a0_to_white_mux000047_SW1 : LUT4_D
21257 
    generic map(
21258 
      INIT => X"E444"
21259 
    )
21260 
    port map (
21261 
      I0 => fax4_ins_N20,
21262 
      I1 => fax4_ins_a0_to_white_mux000026_948,
21263 
      I2 => fax4_ins_pass_mode,
21264 
      I3 => fax4_ins_b2_to_white_1094,
21265 
      LO => N479,
21266 
      O => N133
21267 
    );
21268 
  fax4_ins_vertical_mode_cmp_le00002114_SW0 : LUT4_L
21269 
    generic map(
21270 
      INIT => X"FFE2"
21271 
    )
21272 
    port map (
21273 
      I0 => fax4_ins_a1b1_addsub0000(3),
21274 
      I1 => fax4_ins_EOL,
21275 
      I2 => fax4_ins_a1b1_addsub0001(3),
21276 
      I3 => fax4_ins_a1b1(2),
21277 
      LO => N111
21278 
    );
21279 
  fax4_ins_a1b1_2_1 : LUT4_D
21280 
    generic map(
21281 
      INIT => X"EC4C"
21282 
    )
21283 
    port map (
21284 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
21285 
      I1 => fax4_ins_a1b1_addsub0001(2),
21286 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
21287 
      I3 => fax4_ins_a1b1_addsub0000(2),
21288 
      LO => N480,
21289 
      O => fax4_ins_a1b1(2)
21290 
    );
21291 
  fax4_ins_a1b1_10_1 : LUT4_D
21292 
    generic map(
21293 
      INIT => X"EC4C"
21294 
    )
21295 
    port map (
21296 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
21297 
      I1 => fax4_ins_a1b1_addsub0001(10),
21298 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
21299 
      I3 => fax4_ins_a1b1_addsub0000(10),
21300 
      LO => N481,
21301 
      O => fax4_ins_a1b1(10)
21302 
    );
21303 
  fax4_ins_a1b1_8_1 : LUT4_D
21304 
    generic map(
21305 
      INIT => X"EC4C"
21306 
    )
21307 
    port map (
21308 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
21309 
      I1 => fax4_ins_a1b1_addsub0001(8),
21310 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
21311 
      I3 => fax4_ins_a1b1_addsub0000(8),
21312 
      LO => N482,
21313 
      O => fax4_ins_a1b1(8)
21314 
    );
21315 
  fax4_ins_mode_indicator_o_mux0001_3_41 : LUT4_L
21316 
    generic map(
21317 
      INIT => X"FCAA"
21318 
    )
21319 
    port map (
21320 
      I0 => N160,
21321 
      I1 => N161,
21322 
      I2 => fax4_ins_mode_indicator_o_mux0001_3_9_1302,
21323 
      I3 => fax4_ins_vertical_mode_cmp_le0000,
21324 
      LO => fax4_ins_mode_indicator_o_mux0001(3)
21325 
    );
21326 
  fax4_ins_a1b1_7_1 : LUT4_D
21327 
    generic map(
21328 
      INIT => X"EC4C"
21329 
    )
21330 
    port map (
21331 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
21332 
      I1 => fax4_ins_a1b1_addsub0001(7),
21333 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
21334 
      I3 => fax4_ins_a1b1_addsub0000(7),
21335 
      LO => N483,
21336 
      O => fax4_ins_a1b1(7)
21337 
    );
21338 
  fax4_ins_mode_indicator_o_mux0001_2_234 : LUT4_D
21339 
    generic map(
21340 
      INIT => X"0010"
21341 
    )
21342 
    port map (
21343 
      I0 => fax4_ins_a1b1(10),
21344 
      I1 => fax4_ins_a1b1(9),
21345 
      I2 => fax4_ins_mode_indicator_o_mux0001_2_232_1296,
21346 
      I3 => N218,
21347 
      LO => N484,
21348 
      O => fax4_ins_N15
21349 
    );
21350 
  fax4_ins_fifo2_rd1 : LUT4_D
21351 
    generic map(
21352 
      INIT => X"0010"
21353 
    )
21354 
    port map (
21355 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
21356 
      I1 => N227,
21357 
      I2 => fax4_ins_fifo_rd22_1267,
21358 
      I3 => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(9),
21359 
      LO => N485,
21360 
      O => fax4_ins_fifo2_rd
21361 
    );
21362 
  fax4_ins_fifo1_rd1 : LUT4_D
21363 
    generic map(
21364 
      INIT => X"0080"
21365 
    )
21366 
    port map (
21367 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
21368 
      I1 => N229,
21369 
      I2 => fax4_ins_fifo_rd22_1267,
21370 
      I3 => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(9),
21371 
      LO => N486,
21372 
      O => fax4_ins_fifo1_rd
21373 
    );
21374 
  fax4_ins_FIFO1_multi_read_ins_read_as_last_operation_and0000111 : LUT4_D
21375 
    generic map(
21376 
      INIT => X"2000"
21377 
    )
21378 
    port map (
21379 
      I0 => fax4_ins_fifo_rd22_1267,
21380 
      I1 => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(9),
21381 
      I2 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
21382 
      I3 => N231,
21383 
      LO => N487,
21384 
      O => fax4_ins_FIFO1_multi_read_ins_N8
21385 
    );
21386 
  fax4_ins_FIFO2_multi_read_ins_read_as_last_operation_and0000111 : LUT4_D
21387 
    generic map(
21388 
      INIT => X"0010"
21389 
    )
21390 
    port map (
21391 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
21392 
      I1 => N233,
21393 
      I2 => fax4_ins_fifo_rd22_1267,
21394 
      I3 => fax4_ins_Mcompar_fifo_rd_cmp_lt0000_cy(9),
21395 
      LO => N488,
21396 
      O => fax4_ins_FIFO2_multi_read_ins_N8
21397 
    );
21398 
  fax4_ins_mode_indicator_o_1_rstpot_SW1 : LUT4_L
21399 
    generic map(
21400 
      INIT => X"111D"
21401 
    )
21402 
    port map (
21403 
      I0 => fax4_ins_mode_indicator_o(1),
21404 
      I1 => N167,
21405 
      I2 => N172,
21406 
      I3 => N235,
21407 
      LO => N221
21408 
    );
21409 
  fax4_ins_vertical_mode_cmp_le00002199_SW1 : LUT4_L
21410 
    generic map(
21411 
      INIT => X"888C"
21412 
    )
21413 
    port map (
21414 
      I0 => fax4_ins_state_FSM_FFd8_1338,
21415 
      I1 => N142,
21416 
      I2 => fax4_ins_vertical_mode_cmp_le0000226_1365,
21417 
      I3 => fax4_ins_vertical_mode_cmp_le000020_1361,
21418 
      LO => N240
21419 
    );
21420 
  fax4_ins_mux_a0_3_1 : LUT4_D
21421 
    generic map(
21422 
      INIT => X"207F"
21423 
    )
21424 
    port map (
21425 
      I0 => fax4_ins_vertical_mode_cmp_le0000213_1363,
21426 
      I1 => N246,
21427 
      I2 => fax4_ins_vertical_mode_cmp_le00002169_1364,
21428 
      I3 => N245,
21429 
      LO => N489,
21430 
      O => fax4_ins_mux_a0_3_Q
21431 
    );
21432 
  fax4_ins_a0_mux0000_1_11 : LUT4_D
21433 
    generic map(
21434 
      INIT => X"078F"
21435 
    )
21436 
    port map (
21437 
      I0 => fax4_ins_vertical_mode_cmp_le0000213_1363,
21438 
      I1 => fax4_ins_vertical_mode_cmp_le00002169_1364,
21439 
      I2 => N248,
21440 
      I3 => N249,
21441 
      LO => N490,
21442 
      O => fax4_ins_N01
21443 
    );
21444 
  fax4_ins_a0_mux0000_9_SW0 : LUT4_L
21445 
    generic map(
21446 
      INIT => X"207F"
21447 
    )
21448 
    port map (
21449 
      I0 => fax4_ins_vertical_mode_cmp_le0000213_1363,
21450 
      I1 => N252,
21451 
      I2 => fax4_ins_vertical_mode_cmp_le00002169_1364,
21452 
      I3 => N251,
21453 
      LO => N93
21454 
    );
21455 
  fax4_ins_a0_mux0000_5_SW0 : LUT4_L
21456 
    generic map(
21457 
      INIT => X"207F"
21458 
    )
21459 
    port map (
21460 
      I0 => fax4_ins_vertical_mode_cmp_le0000213_1363,
21461 
      I1 => N255,
21462 
      I2 => fax4_ins_vertical_mode_cmp_le00002169_1364,
21463 
      I3 => N254,
21464 
      LO => N95
21465 
    );
21466 
  fax4_ins_a0_mux0000_4_SW0 : LUT4_L
21467 
    generic map(
21468 
      INIT => X"207F"
21469 
    )
21470 
    port map (
21471 
      I0 => fax4_ins_vertical_mode_cmp_le0000213_1363,
21472 
      I1 => N258,
21473 
      I2 => fax4_ins_vertical_mode_cmp_le00002169_1364,
21474 
      I3 => N257,
21475 
      LO => N97
21476 
    );
21477 
  fax4_ins_a0_mux0000_3_SW0 : LUT4_L
21478 
    generic map(
21479 
      INIT => X"207F"
21480 
    )
21481 
    port map (
21482 
      I0 => fax4_ins_vertical_mode_cmp_le0000213_1363,
21483 
      I1 => N261,
21484 
      I2 => fax4_ins_vertical_mode_cmp_le00002169_1364,
21485 
      I3 => N260,
21486 
      LO => N99
21487 
    );
21488 
  fax4_ins_a0_mux0000_2_SW0 : LUT4_L
21489 
    generic map(
21490 
      INIT => X"207F"
21491 
    )
21492 
    port map (
21493 
      I0 => fax4_ins_vertical_mode_cmp_le0000213_1363,
21494 
      I1 => N264,
21495 
      I2 => fax4_ins_vertical_mode_cmp_le00002169_1364,
21496 
      I3 => N263,
21497 
      LO => N101
21498 
    );
21499 
  fax4_ins_a0_mux0000_0_SW0 : LUT4_L
21500 
    generic map(
21501 
      INIT => X"207F"
21502 
    )
21503 
    port map (
21504 
      I0 => fax4_ins_vertical_mode_cmp_le0000213_1363,
21505 
      I1 => N267,
21506 
      I2 => fax4_ins_vertical_mode_cmp_le00002169_1364,
21507 
      I3 => N266,
21508 
      LO => N103
21509 
    );
21510 
  fax4_ins_mux_b1_0_and000021 : LUT4_D
21511 
    generic map(
21512 
      INIT => X"0001"
21513 
    )
21514 
    port map (
21515 
      I0 => fax4_ins_pix_changed_1319,
21516 
      I1 => fax4_ins_state_FSM_FFd8_1338,
21517 
      I2 => fax4_ins_Mcompar_pass_mode_cmp_lt0000_cy(9),
21518 
      I3 => fax4_ins_EOL,
21519 
      LO => N491,
21520 
      O => fax4_ins_pass_mode
21521 
    );
21522 
  fax4_ins_mux_b1_0_and0000 : LUT4_D
21523 
    generic map(
21524 
      INIT => X"0060"
21525 
    )
21526 
    port map (
21527 
      I0 => fax4_ins_fifo_out_prev2_to_white_1252,
21528 
      I1 => fax4_ins_a0_to_white_946,
21529 
      I2 => N75,
21530 
      I3 => fax4_ins_Mcompar_mux_b1_0_cmp_gt0000_cy(9),
21531 
      LO => N492,
21532 
      O => fax4_ins_mux_b1(0)
21533 
    );
21534 
  fax4_ins_mux_b1_3_and0000 : LUT4_D
21535 
    generic map(
21536 
      INIT => X"0C04"
21537 
    )
21538 
    port map (
21539 
      I0 => fax4_ins_Mcompar_mux_b1_3_cmp_gt0000_cy(9),
21540 
      I1 => fax4_ins_fifo_out2_valid,
21541 
      I2 => N77,
21542 
      I3 => fax4_ins_EOL,
21543 
      LO => N493,
21544 
      O => fax4_ins_mux_b1(3)
21545 
    );
21546 
  fax4_ins_vertical_mode_cmp_le00002199_SW3 : LUT4_L
21547 
    generic map(
21548 
      INIT => X"FEFF"
21549 
    )
21550 
    port map (
21551 
      I0 => N269,
21552 
      I1 => fax4_ins_mux_a0_0_Q,
21553 
      I2 => fax4_ins_state_FSM_FFd8_1338,
21554 
      I3 => fax4_ins_vertical_mode_cmp_le0000213_1363,
21555 
      LO => N243
21556 
    );
21557 
  fax4_ins_vertical_mode_cmp_le00002199_SW9_SW0 : LUT4_D
21558 
    generic map(
21559 
      INIT => X"FF57"
21560 
    )
21561 
    port map (
21562 
      I0 => fax4_ins_a1b1(10),
21563 
      I1 => fax4_ins_vertical_mode_addsub0000(7),
21564 
      I2 => fax4_ins_vertical_mode_addsub0000(6),
21565 
      I3 => fax4_ins_vertical_mode_addsub0000(10),
21566 
      LO => N494,
21567 
      O => N271
21568 
    );
21569 
  fax4_ins_FIFO1_multi_read_ins_mux3_and0000 : LUT4_D
21570 
    generic map(
21571 
      INIT => X"0001"
21572 
    )
21573 
    port map (
21574 
      I0 => fax4_ins_EOL,
21575 
      I1 => fax4_ins_FIFO1_multi_read_ins_N4,
21576 
      I2 => fax4_ins_FIFO1_multi_read_ins_used(0),
21577 
      I3 => N341,
21578 
      LO => N495,
21579 
      O => fax4_ins_FIFO1_multi_read_ins_mux3
21580 
    );
21581 
  fax4_ins_mode_indicator_o_3_rstpot_SW0 : LUT4_L
21582 
    generic map(
21583 
      INIT => X"FFFE"
21584 
    )
21585 
    port map (
21586 
      I0 => fax4_ins_pass_mode,
21587 
      I1 => fax4_ins_load_a1_or0001,
21588 
      I2 => N142,
21589 
      I3 => fax4_ins_mode_indicator_o(3),
21590 
      LO => N179
21591 
    );
21592 
  fax4_ins_a0_mux0000_1_11_SW0 : LUT4_D
21593 
    generic map(
21594 
      INIT => X"7FFF"
21595 
    )
21596 
    port map (
21597 
      I0 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
21598 
      I1 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
21599 
      I2 => fax4_ins_pix_changed_1319,
21600 
      I3 => fax4_ins_state_FSM_FFd8_1338,
21601 
      LO => N496,
21602 
      O => N115
21603 
    );
21604 
  fax4_ins_mux_b1_2_and000019 : LUT4_L
21605 
    generic map(
21606 
      INIT => X"569A"
21607 
    )
21608 
    port map (
21609 
      I0 => fax4_ins_a0_to_white_946,
21610 
      I1 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
21611 
      I2 => fax4_ins_FIFO2_multi_read_ins_to_white1_o_683,
21612 
      I3 => fax4_ins_FIFO1_multi_read_ins_to_white1_o_441,
21613 
      LO => fax4_ins_mux_b1_2_and000019_1310
21614 
    );
21615 
  fax4_ins_a1b1_1_1 : LUT4_D
21616 
    generic map(
21617 
      INIT => X"EC4C"
21618 
    )
21619 
    port map (
21620 
      I0 => fax4_ins_counter_xy_v2_ins_frame_valid_1206,
21621 
      I1 => fax4_ins_a1b1_addsub0001(1),
21622 
      I2 => fax4_ins_counter_xy_v2_ins_line_valid_1210,
21623 
      I3 => fax4_ins_a1b1_addsub0000(1),
21624 
      LO => N497,
21625 
      O => fax4_ins_a1b1(1)
21626 
    );
21627 
  fax4_ins_mux_b1_2_and000032 : LUT4_D
21628 
    generic map(
21629 
      INIT => X"00D8"
21630 
    )
21631 
    port map (
21632 
      I0 => NlwRenamedSig_OI_fax4_ins_counter_xy_v2_ins_counter_y_ins_cnt(0),
21633 
      I1 => fax4_ins_FIFO1_multi_read_ins_valid1_o_456,
21634 
      I2 => fax4_ins_FIFO2_multi_read_ins_valid1_o_698,
21635 
      I3 => N381,
21636 
      LO => N498,
21637 
      O => fax4_ins_mux_b1(2)
21638 
    );
21639 
  huffman_ins_v2_Mshreg_pass_vert_code_width_3_0 : SRL16
21640 
    generic map(
21641 
      INIT => X"0000"
21642 
    )
21643 
    port map (
21644 
      A0 => NlwRenamedSig_OI_run_len_code_o(26),
21645 
      A1 => NlwRenamedSig_OI_run_len_code_o(26),
21646 
      A2 => NlwRenamedSig_OI_run_len_code_o(26),
21647 
      A3 => NlwRenamedSig_OI_run_len_code_o(26),
21648 
      CLK => pclk_i,
21649 
      D => huffman_ins_v2_pass_vert_code_width_1_0_Q,
21650 
      Q => huffman_ins_v2_Mshreg_pass_vert_code_width_3_0_1400
21651 
    );
21652 
  huffman_ins_v2_pass_vert_code_width_3_0 : FD
21653 
    generic map(
21654 
      INIT => '0'
21655 
    )
21656 
    port map (
21657 
      C => pclk_i,
21658 
      D => huffman_ins_v2_Mshreg_pass_vert_code_width_3_0_1400,
21659 
      Q => huffman_ins_v2_pass_vert_code_width_3_0_Q
21660 
    );
21661 
  huffman_ins_v2_Mshreg_frame_finished_o : SRL16
21662 
    generic map(
21663 
      INIT => X"0000"
21664 
    )
21665 
    port map (
21666 
      A0 => NlwRenamedSig_OI_run_len_code_o(26),
21667 
      A1 => N1,
21668 
      A2 => NlwRenamedSig_OI_run_len_code_o(26),
21669 
      A3 => NlwRenamedSig_OI_run_len_code_o(26),
21670 
      CLK => pclk_i,
21671 
      D => frame_finished_wire,
21672 
      Q => huffman_ins_v2_Mshreg_frame_finished_o_1395
21673 
    );
21674 
  huffman_ins_v2_frame_finished_o : FD
21675 
    generic map(
21676 
      INIT => '0'
21677 
    )
21678 
    port map (
21679 
      C => pclk_i,
21680 
      D => huffman_ins_v2_Mshreg_frame_finished_o_1395,
21681 
      Q => huffman_ins_v2_frame_finished_o_1814
21682 
    );
21683 
  huffman_ins_v2_Mshreg_pass_vert_code_width_3_2 : SRL16
21684 
    generic map(
21685 
      INIT => X"0000"
21686 
    )
21687 
    port map (
21688 
      A0 => NlwRenamedSig_OI_run_len_code_o(26),
21689 
      A1 => NlwRenamedSig_OI_run_len_code_o(26),
21690 
      A2 => NlwRenamedSig_OI_run_len_code_o(26),
21691 
      A3 => NlwRenamedSig_OI_run_len_code_o(26),
21692 
      CLK => pclk_i,
21693 
      D => huffman_ins_v2_pass_vert_code_width_1_2_Q,
21694 
      Q => huffman_ins_v2_Mshreg_pass_vert_code_width_3_2_1401
21695 
    );
21696 
  huffman_ins_v2_pass_vert_code_width_3_2 : FD
21697 
    generic map(
21698 
      INIT => '0'
21699 
    )
21700 
    port map (
21701 
      C => pclk_i,
21702 
      D => huffman_ins_v2_Mshreg_pass_vert_code_width_3_2_1401,
21703 
      Q => huffman_ins_v2_pass_vert_code_width_3_2_Q
21704 
    );
21705 
  huffman_ins_v2_Mshreg_pass_vert_code_3_2 : SRL16
21706 
    generic map(
21707 
      INIT => X"0001"
21708 
    )
21709 
    port map (
21710 
      A0 => NlwRenamedSig_OI_run_len_code_o(26),
21711 
      A1 => NlwRenamedSig_OI_run_len_code_o(26),
21712 
      A2 => NlwRenamedSig_OI_run_len_code_o(26),
21713 
      A3 => NlwRenamedSig_OI_run_len_code_o(26),
21714 
      CLK => pclk_i,
21715 
      D => huffman_ins_v2_pass_vert_code_1(2),
21716 
      Q => huffman_ins_v2_Mshreg_pass_vert_code_3_2_1399
21717 
    );
21718 
  huffman_ins_v2_pass_vert_code_3_2 : FD
21719 
    generic map(
21720 
      INIT => '1'
21721 
    )
21722 
    port map (
21723 
      C => pclk_i,
21724 
      D => huffman_ins_v2_Mshreg_pass_vert_code_3_2_1399,
21725 
      Q => huffman_ins_v2_pass_vert_code_3(2)
21726 
    );
21727 
  huffman_ins_v2_Mshreg_pass_vert_code_3_1 : SRL16
21728 
    generic map(
21729 
      INIT => X"0000"
21730 
    )
21731 
    port map (
21732 
      A0 => NlwRenamedSig_OI_run_len_code_o(26),
21733 
      A1 => NlwRenamedSig_OI_run_len_code_o(26),
21734 
      A2 => NlwRenamedSig_OI_run_len_code_o(26),
21735 
      A3 => NlwRenamedSig_OI_run_len_code_o(26),
21736 
      CLK => pclk_i,
21737 
      D => huffman_ins_v2_pass_vert_code_1(1),
21738 
      Q => huffman_ins_v2_Mshreg_pass_vert_code_3_1_1398
21739 
    );
21740 
  huffman_ins_v2_pass_vert_code_3_1 : FD
21741 
    generic map(
21742 
      INIT => '0'
21743 
    )
21744 
    port map (
21745 
      C => pclk_i,
21746 
      D => huffman_ins_v2_Mshreg_pass_vert_code_3_1_1398,
21747 
      Q => huffman_ins_v2_pass_vert_code_3(1)
21748 
    );
21749 
  huffman_ins_v2_Mshreg_pass_vert_code_3_0 : SRL16
21750 
    generic map(
21751 
      INIT => X"0000"
21752 
    )
21753 
    port map (
21754 
      A0 => NlwRenamedSig_OI_run_len_code_o(26),
21755 
      A1 => NlwRenamedSig_OI_run_len_code_o(26),
21756 
      A2 => NlwRenamedSig_OI_run_len_code_o(26),
21757 
      A3 => NlwRenamedSig_OI_run_len_code_o(26),
21758 
      CLK => pclk_i,
21759 
      D => huffman_ins_v2_pass_vert_code_1(0),
21760 
      Q => huffman_ins_v2_Mshreg_pass_vert_code_3_0_1397
21761 
    );
21762 
  huffman_ins_v2_pass_vert_code_3_0 : FD
21763 
    generic map(
21764 
      INIT => '0'
21765 
    )
21766 
    port map (
21767 
      C => pclk_i,
21768 
      D => huffman_ins_v2_Mshreg_pass_vert_code_3_0_1397,
21769 
      Q => huffman_ins_v2_pass_vert_code_3(0)
21770 
    );
21771 
  huffman_ins_v2_Mshreg_run_len_code_valid_o : SRL16
21772 
    generic map(
21773 
      INIT => X"0000"
21774 
    )
21775 
    port map (
21776 
      A0 => N1,
21777 
      A1 => NlwRenamedSig_OI_run_len_code_o(26),
21778 
      A2 => NlwRenamedSig_OI_run_len_code_o(26),
21779 
      A3 => NlwRenamedSig_OI_run_len_code_o(26),
21780 
      CLK => pclk_i,
21781 
      D => fax4_ins_output_valid_o_1311,
21782 
      Q => huffman_ins_v2_Mshreg_run_len_code_valid_o_1402
21783 
    );
21784 
  huffman_ins_v2_run_len_code_valid_o : FD
21785 
    generic map(
21786 
      INIT => '0'
21787 
    )
21788 
    port map (
21789 
      C => pclk_i,
21790 
      D => huffman_ins_v2_Mshreg_run_len_code_valid_o_1402,
21791 
      Q => huffman_ins_v2_run_len_code_valid_o_2082
21792 
    );
21793 
  huffman_ins_v2_Mshreg_horizontal_mode_3 : SRL16
21794 
    generic map(
21795 
      INIT => X"0000"
21796 
    )
21797 
    port map (
21798 
      A0 => NlwRenamedSig_OI_run_len_code_o(26),
21799 
      A1 => NlwRenamedSig_OI_run_len_code_o(26),
21800 
      A2 => NlwRenamedSig_OI_run_len_code_o(26),
21801 
      A3 => NlwRenamedSig_OI_run_len_code_o(26),
21802 
      CLK => pclk_i,
21803 
      D => huffman_ins_v2_horizontal_mode_1_2060,
21804 
      Q => huffman_ins_v2_Mshreg_horizontal_mode_3_1396
21805 
    );
21806 
  huffman_ins_v2_horizontal_mode_3 : FD
21807 
    generic map(
21808 
      INIT => '0'
21809 
    )
21810 
    port map (
21811 
      C => pclk_i,
21812 
      D => huffman_ins_v2_Mshreg_horizontal_mode_3_1396,
21813 
      Q => huffman_ins_v2_horizontal_mode_3_2063
21814 
    );
21815 
  huffman_ins_v2_Mshreg_a0_value_2 : SRL16
21816 
    generic map(
21817 
      INIT => X"0000"
21818 
    )
21819 
    port map (
21820 
      A0 => NlwRenamedSig_OI_run_len_code_o(26),
21821 
      A1 => NlwRenamedSig_OI_run_len_code_o(26),
21822 
      A2 => NlwRenamedSig_OI_run_len_code_o(26),
21823 
      A3 => NlwRenamedSig_OI_run_len_code_o(26),
21824 
      CLK => pclk_i,
21825 
      D => fax4_ins_a0_value_o_950,
21826 
      Q => huffman_ins_v2_Mshreg_a0_value_2_1394
21827 
    );
21828 
  huffman_ins_v2_a0_value_2 : FD
21829 
    generic map(
21830 
      INIT => '0'
21831 
    )
21832 
    port map (
21833 
      C => pclk_i,
21834 
      D => huffman_ins_v2_Mshreg_a0_value_2_1394,
21835 
      Q => huffman_ins_v2_a0_value_2_1510
21836 
    );
21837 
 
21838 
end Structure;
21839 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.