URL https://opencores.org/ocsvn/bw_tiff_compression/bw_tiff_compression/trunk

Subversion Repositories bw_tiff_compression

[/] [bw_tiff_compression/] [trunk/] [capture_manager.vhd] - Blame information for rev 8

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----------------------------------------------------------------------------------
-- Company:        
-- Engineer:       Aart Mulder
-- 
-- Version:        V2.0
-- Create Date:    13:27:31 08/17/2012 
-- Design Name:    Tiff compression and transmission
-- Module Name:    capture_manager - Behavioral 
-- Project Name:   Tiff compression and transmission
----------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity capture_manager is
        Generic (
                COLUMNS_G                       : integer := 752;
                ROWS_G                          : integer := 480;
                COL_INDEX_WIDTH_G               : integer := 10; --Width to represent the column index
                ROW_INDEX_WIDTH_G               : integer := 9; --Width to represent the row index
 
                MAX_CODE_LEN_G                  : integer := 28;
                MAX_CODE_LEN_WIDTH_G            : integer := 5;
                SEG_OUTPUT_WIDTH_G              : integer := 8;
 
                TX_MEMORY_SIZE_G                : integer := 4000;
                TX_MEMORY_ADDRESS_WIDTH_G       : integer := 12;
                TX_MEMORY_WIDTH_G               : integer := 8;
 
                --@26.6MHz
                BAUD_DIVIDE_G                   : integer := 15;        --115200 baud
                BAUD_RATE_G                     : integer := 231
        );
        Port
        (
                reset_i   : in  STD_LOGIC;
 
                fsync_i   : in  STD_LOGIC;
                rsync_i   : in  STD_LOGIC;
                pclk_i    : in  STD_LOGIC;
                pix_data_i: in  STD_LOGIC_VECTOR(7 downto 0);
 
                vga_fsync_o : out STD_LOGIC;
                vga_rsync_o : out STD_LOGIC;
                vgaRed      : out STD_LOGIC_VECTOR(7 downto 5);
                vgaGreen    : out STD_LOGIC_VECTOR(7 downto 5);
                vgaBlue     : out STD_LOGIC_VECTOR(7 downto 6);
 
                TX_o    : out STD_LOGIC;
                RX_i    : in STD_LOGIC;
 
                led0_o  : out STD_LOGIC;
                led1_o  : out STD_LOGIC;
                led2_o  : out STD_LOGIC;
                led3_o  : out STD_LOGIC;
 
                sw_i : in STD_LOGIC_VECTOR(6 downto 0);
 
                --Testbench connections
                CCITT4_run_len_code_o       : out STD_LOGIC_VECTOR (MAX_CODE_LEN_G-1 downto 0);
                CCITT4_run_len_code_width_o : out STD_LOGIC_VECTOR (MAX_CODE_LEN_WIDTH_G-1 downto 0);
                CCITT4_run_len_code_valid_o : out STD_LOGIC;
                CCITT4_frame_finished_o     : out STD_LOGIC
        );
end capture_manager;
 
architecture Behavioral of capture_manager is
        type state_type is (S_Start, S_WaitForChar, S_WaitForNewFrame, S_CaptureStoreFrame,
                        S_SendSizeB1, S_SendSizeB1WaitRdy,
                        S_SendSizeB2, S_SendSizeB2WaitRdy,
                        S_SendStreamByte, S_SendStreamByteWaitAccepted, S_SendStreamByteWaitRdy,
                        S_Unknown);
 
        constant CHAR_CAP_S            : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(83, 8));
--      constant CHAR_S                : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(115, 8));
        constant START_NEW_FRAME_CHAR  : std_logic_vector(7 downto 0) := CHAR_CAP_S;
 
        constant ZERO_PADDING_C : std_logic_vector(15 downto 0) := (others => '0');
 
        function boolean2sl(x : boolean)
                        return std_logic is
        begin
                if x then
                        return '1';
                else
                        return '0';
                end if;
        end boolean2sl;
 
        function sl2boolean(x : std_logic)
                        return boolean is
        begin
                if x = '1' then
                        return TRUE;
                else
                        return FALSE;
                end if;
        end sl2boolean;
 
        --State machine signals
        signal state, state_next : state_type := S_Start;
 
        --Signals to connect the CCITT4 module
        signal run_len_code_CCITT4       : STD_LOGIC_VECTOR(MAX_CODE_LEN_G - 1 downto 0)       := (others => '0');
        signal run_len_code_width_CCITT4 : STD_LOGIC_VECTOR(MAX_CODE_LEN_WIDTH_G - 1 downto 0) := (others => '0');
        signal run_len_code_valid_CCITT4 : STD_LOGIC                                           := '0';
        signal frame_finished_CCITT4     : STD_LOGIC                                           := '0';
        signal pix                       : STD_LOGIC                                           := '0';
        signal fax4_x : unsigned(COL_INDEX_WIDTH_G-1 downto 0) := (others => '0');
        signal fax4_y : unsigned(ROW_INDEX_WIDTH_G-1 downto 0) := (others => '0');
 
        --Signals to connect the byte segmentation module
        signal seg_d1, seg_d2, seg_d3, seg_d4 : STD_LOGIC_VECTOR(SEG_OUTPUT_WIDTH_G-1 downto 0)  := (others => '0');
        signal seg_d_rdy1, seg_d_rdy2, seg_d_rdy3, seg_d_rdy4 : STD_LOGIC                        := '0';
        signal seg_frame_finished_in       : STD_LOGIC                                           := '0';
        signal seg_frame_finished_out      : STD_LOGIC                                           := '0';
        signal seg_reset                   : STD_LOGIC                                           := '0';
 
        --Signals to connect the UART module
        signal tx_data, rx_data                              : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
        signal rx_available, tx_buf_empty, tx_buf_empty_prev : STD_LOGIC                    := '0';
        signal rx_trigger, tx_trigger                        : STD_LOGIC                    := '0';
        signal uart_reset                                    : STD_LOGIC                    := '0';
 
        -- Tx memory
        signal tx_mem_reset         : STD_LOGIC                                              := '0';
        signal tx_mem_d_out         : STD_LOGIC_VECTOR(TX_MEMORY_WIDTH_G-1 downto 0)         := (others => '0');
        signal tx_mem_read_addr     : std_logic_vector(TX_MEMORY_ADDRESS_WIDTH_G-1 downto 0) := (others => '0');
        signal tx_mem_used          : unsigned(TX_MEMORY_ADDRESS_WIDTH_G-1 downto 0)         := (others => '0');
 
                --Other signals
        signal fsync_prev                    : STD_LOGIC             := '0';
        signal tx_mem_overflow               : std_logic             := '0';
 
begin
        CCITT4_ins : entity work.CCITT4_v2
        Port Map(
                pclk_i    => pclk_i,
                fsync_i  => fsync_i,
                rsync_i  => rsync_i,
                pix_i  => pix,
                run_len_code_o  => run_len_code_CCITT4,
                run_len_code_width_o  => run_len_code_width_CCITT4,
                run_len_code_valid_o  => run_len_code_valid_CCITT4,
                frame_finished_o  => frame_finished_CCITT4
        );
 
        byte_segmentation_ins_v5 : entity work.byte_segmentation_v5
        Generic Map(
                INPUT_WIDTH_G =>  MAX_CODE_LEN_G,
                OUTPUT_WIDTH_G => SEG_OUTPUT_WIDTH_G,
                INDEX_WIDTH_G =>  MAX_CODE_LEN_WIDTH_G
        )
        Port Map(
                reset_i => seg_reset,
                clk_i => pclk_i,
                pclk_i => pclk_i,
                d_i => run_len_code_CCITT4,
                d_width_i => run_len_code_width_CCITT4,
                d_rdy_i => run_len_code_valid_CCITT4,
                d1_o => seg_d1,
                d_rdy1_o => seg_d_rdy1,
                d2_o => seg_d2,
                d_rdy2_o => seg_d_rdy2,
                d3_o => seg_d3,
                d_rdy3_o => seg_d_rdy3,
                d4_o => seg_d4,
                d_rdy4_o => seg_d_rdy4,
                frame_finished_i => seg_frame_finished_in,
                frame_finished_o => seg_frame_finished_out
        );
        seg_frame_finished_in <= frame_finished_CCITT4;
 
        var_width_RAM_ins : entity work.var_width_RAM
        generic map(
                MEM_SIZE_G => TX_MEMORY_SIZE_G,
                MEM_INDEX_WIDTH_G => TX_MEMORY_ADDRESS_WIDTH_G,
                DATA_WIDTH_G  => TX_MEMORY_WIDTH_G
        )
        port map(
                reset_i   => tx_mem_reset,
                clk_i     => pclk_i,
                wr1_i     => seg_d_rdy1,
                d1_i      => seg_d1,
                wr2_i     => seg_d_rdy2,
                d2_i      => seg_d2,
                wr3_i     => seg_d_rdy3,
                d3_i      => seg_d3,
                wr4_i     => seg_d_rdy4,
                d4_i      => seg_d4,
                rd_addr_i => tx_mem_read_addr,
                d_o       => tx_mem_d_out,
                used_o    => tx_mem_used
        );
 
        UART_ins : entity work.UartComponent
        Generic Map(
                BAUD_DIVIDE_G => BAUD_DIVIDE_G,
                BAUD_RATE_G => BAUD_RATE_G
        )
        Port Map(
                TXD     => TX_o,
                RXD     => RX_i,
                CLK     => pclk_i,
                DBIN    => tx_data,
                DBOUT   => rx_data,
                RDA         => rx_available,
                TBE         => tx_buf_empty,
                RD              => rx_trigger,
                WR              => tx_trigger,
                PE              => open,
                FE              => open,
                OE              => open,
                RST         => uart_reset
        );
 
        decode_state_process : process(reset_i, pclk_i)
        begin
                if reset_i = '1' then
                        state <= S_Start;
                elsif pclk_i'event and pclk_i = '1' then
                        state <= state_next;
                else
                        state <= state;
                end if;
        end process decode_state_process;
 
        decode_next_state : process (reset_i, pclk_i, fsync_i, tx_buf_empty)
        begin
                if pclk_i'event and pclk_i = '1' then
                        fsync_prev <= fsync_i;
                        uart_reset <= '0';
                        rx_trigger <= '0';
                        tx_trigger <= '0';
                        tx_buf_empty_prev <= tx_buf_empty;
 
                        case (state) is
                                when S_Start =>
                                        state_next <= S_WaitForChar;
                                        uart_reset <= '1';
 
                                when S_WaitForChar =>
                                        if rx_available = '1' and rx_data = START_NEW_FRAME_CHAR then
                                                state_next <= S_WaitForNewFrame;
                                                rx_trigger <= '1';
                                        elsif rx_available = '1' then
                                                rx_trigger <= '1';
                                                tx_data <= rx_data;
                                                tx_trigger <= '1';
                                                state_next <= state_next;
                                        else
                                                state_next <= state_next;
                                        end if;
 
                                when S_WaitForNewFrame =>
                                        if fsync_prev = '0' and fsync_i = '1' then
                                                state_next <= S_CaptureStoreFrame;
                                        else
                                                state_next <= state_next;
                                        end if;
 
                                when S_CaptureStoreFrame =>
                                        if seg_frame_finished_out = '1' then
                                                state_next <= S_SendSizeB1;
                                        else
                                                state_next <= state_next;
                                        end if;
 
                                when S_SendSizeB1 =>
                                        state_next <= S_SendSizeB1WaitRdy;
                                        tx_data <= std_logic_vector(tx_mem_used(7 downto 0));
                                        tx_trigger <= '1';
                                when S_SendSizeB1WaitRdy =>
                                        if tx_buf_empty_prev = '0' and tx_buf_empty = '1' then
                                                state_next <= S_SendSizeB2;
                                        else
                                                state_next <= state_next;
                                        end if;
                                when S_SendSizeB2 =>
                                        state_next <= S_SendSizeB2WaitRdy;
                                        tx_data <= ZERO_PADDING_C(16-1 downto TX_MEMORY_ADDRESS_WIDTH_G) & std_logic_vector(tx_mem_used(TX_MEMORY_ADDRESS_WIDTH_G-1 downto 8));
                                        tx_trigger <= '1';
 
                                when S_SendSizeB2WaitRdy =>
                                        if tx_buf_empty_prev = '0' and tx_buf_empty = '1' then
                                                state_next <= S_SendStreamByte;
                                        else
                                                state_next <= state_next;
                                        end if;
 
                                when S_SendStreamByte =>
                                        state_next <= S_SendStreamByteWaitAccepted;
                                        tx_data <= tx_mem_d_out;
                                        tx_trigger <= '1';
                                when S_SendStreamByteWaitAccepted =>
                                        if tx_buf_empty = '0' then
                                                state_next <= S_SendStreamByteWaitRdy;
                                        end if;
 
                                when S_SendStreamByteWaitRdy =>
                                        if tx_buf_empty = '1' then
                                                if unsigned(tx_mem_read_addr) = tx_mem_used then
                                                        state_next <= S_Start;
                                                else
                                                        state_next <= S_SendStreamByte;
                                                end if;
                                        else
                                                state_next <= state_next;
                                        end if;
 
                                when S_Unknown =>
 
                                when others =>
                                        state_next <= S_Unknown;
                        end case;
                end if;
        end process decode_next_state;
 
        -- Detection of memory overflow and notification to the user.
        mem_overflow_detection_process : process(pclk_i)
        begin
                if pclk_i'event and pclk_i = '1' then
                        if reset_i = '1' then
                                tx_mem_overflow <= '0';
                        elsif tx_mem_used >= to_unsigned(TX_MEMORY_SIZE_G, 16) then
                                tx_mem_overflow <= '1';
                        else
                                tx_mem_overflow <= tx_mem_overflow;
                        end if;
                end if;
        end process mem_overflow_detection_process;
 
        led0_o <= boolean2sl(state = S_WaitForChar);
        led1_o <= boolean2sl(state = S_CaptureStoreFrame);
        led2_o <= boolean2sl(state = S_SendSizeB1)
                                or boolean2sl(state = S_SendSizeB2)
                                or boolean2sl(state = S_SendSizeB1WaitRdy)
                                or boolean2sl(state = S_SendSizeB2WaitRdy)
                                or boolean2sl(state = S_SendStreamByte)
                                or boolean2sl(state = S_SendStreamByteWaitAccepted)
                                or boolean2sl(state = S_SendStreamByteWaitRdy);
        led3_o <= tx_mem_overflow;
 
        pix <= pix_data_i(7)
                        when unsigned(tx_mem_used) < (to_unsigned(TX_MEMORY_SIZE_G, TX_MEMORY_ADDRESS_WIDTH_G) - to_unsigned(ROWS_G, TX_MEMORY_ADDRESS_WIDTH_G))
                        else '1';
 
        --Data segmentation tasks
        seg_reset <= '0' when state = S_CaptureStoreFrame else '1';
        tx_mem_reset <= '1' when state = S_WaitForNewFrame else '0';
 
        --Transmission memory read pointer incrementation
        tx_mem_read_write_pos_process : process(pclk_i)
        begin
                if pclk_i'event and pclk_i = '1' then
                        if state = S_WaitForNewFrame then
                                tx_mem_read_addr <= (others => '0');
                        elsif (tx_trigger = '1')
                                        and unsigned(tx_mem_read_addr) /= tx_mem_used
                                        and state = S_SendStreamByte then
                                tx_mem_read_addr <= std_logic_vector(unsigned(tx_mem_read_addr) + to_unsigned(1, TX_MEMORY_ADDRESS_WIDTH_G));
                        else
                                tx_mem_read_addr <= tx_mem_read_addr;
                        end if;
                end if;
        end process tx_mem_read_write_pos_process;
 
        -- Other tasks
        vgaRed <= pix_data_i(7 downto 5) when sw_i(0) = '0' else pix_data_i(7) & pix_data_i(7) & pix_data_i(7);
        vgaGreen <= pix_data_i(7 downto 5) when sw_i(0) = '0' else pix_data_i(7) & pix_data_i(7) & pix_data_i(7);
        vgaBlue <= pix_data_i(7 downto 6) when sw_i(0) = '0' else pix_data_i(7) & pix_data_i(7);
        vga_fsync_o <= fsync_i;
        vga_rsync_o <= rsync_i;
 
        CCITT4_run_len_code_o <= run_len_code_CCITT4;
        CCITT4_run_len_code_width_o <= run_len_code_width_CCITT4;
        CCITT4_run_len_code_valid_o <= run_len_code_valid_CCITT4;
        CCITT4_frame_finished_o <= frame_finished_CCITT4;
 
end Behavioral;

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Subversion Repositories bw_tiff_compression

[/] [bw_tiff_compression/] [trunk/] [capture_manager.vhd] - Blame information for rev 8

Line No.	Rev	Author	Line
1	2	amulder	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer: Aart Mulder`
4			`--`
5			`-- Version: V2.0`
6			`-- Create Date: 13:27:31 08/17/2012`
7			`-- Design Name: Tiff compression and transmission`
8			`-- Module Name: capture_manager - Behavioral`
9			`-- Project Name: Tiff compression and transmission`
10			`----------------------------------------------------------------------------------`
11
12			`library IEEE;`
13			`use IEEE.STD_LOGIC_1164.ALL;`
14			`use IEEE.NUMERIC_STD.ALL;`
15
16			`entity capture_manager is`
17			`Generic (`
18			`COLUMNS_G : integer := 752;`
19			`ROWS_G : integer := 480;`
20			`COL_INDEX_WIDTH_G : integer := 10; --Width to represent the column index`
21			`ROW_INDEX_WIDTH_G : integer := 9; --Width to represent the row index`
22
23			`MAX_CODE_LEN_G : integer := 28;`
24			`MAX_CODE_LEN_WIDTH_G : integer := 5;`
25			`SEG_OUTPUT_WIDTH_G : integer := 8;`
26
27	8	amulder	`TX_MEMORY_SIZE_G : integer := 4000;`
28	2	amulder	`TX_MEMORY_ADDRESS_WIDTH_G : integer := 12;`
29			`TX_MEMORY_WIDTH_G : integer := 8;`
30
31			`--@26.6MHz`
32			`BAUD_DIVIDE_G : integer := 15; --115200 baud`
33			`BAUD_RATE_G : integer := 231`
34			`);`
35			`Port`
36			`(`
37			`reset_i : in STD_LOGIC;`
38
39			`fsync_i : in STD_LOGIC;`
40			`rsync_i : in STD_LOGIC;`
41			`pclk_i : in STD_LOGIC;`
42			`pix_data_i: in STD_LOGIC_VECTOR(7 downto 0);`
43
44			`vga_fsync_o : out STD_LOGIC;`
45			`vga_rsync_o : out STD_LOGIC;`
46			`vgaRed : out STD_LOGIC_VECTOR(7 downto 5);`
47			`vgaGreen : out STD_LOGIC_VECTOR(7 downto 5);`
48			`vgaBlue : out STD_LOGIC_VECTOR(7 downto 6);`
49
50			`TX_o : out STD_LOGIC;`
51			`RX_i : in STD_LOGIC;`
52
53			`led0_o : out STD_LOGIC;`
54			`led1_o : out STD_LOGIC;`
55			`led2_o : out STD_LOGIC;`
56			`led3_o : out STD_LOGIC;`
57
58	8	amulder	`sw_i : in STD_LOGIC_VECTOR(6 downto 0);`
59
60			`--Testbench connections`
61			`CCITT4_run_len_code_o : out STD_LOGIC_VECTOR (MAX_CODE_LEN_G-1 downto 0);`
62			`CCITT4_run_len_code_width_o : out STD_LOGIC_VECTOR (MAX_CODE_LEN_WIDTH_G-1 downto 0);`
63			`CCITT4_run_len_code_valid_o : out STD_LOGIC;`
64			`CCITT4_frame_finished_o : out STD_LOGIC`
65	2	amulder	`);`
66			`end capture_manager;`
67
68			`architecture Behavioral of capture_manager is`
69			`type state_type is (S_Start, S_WaitForChar, S_WaitForNewFrame, S_CaptureStoreFrame,`
70			`S_SendSizeB1, S_SendSizeB1WaitRdy,`
71			`S_SendSizeB2, S_SendSizeB2WaitRdy,`
72			`S_SendStreamByte, S_SendStreamByteWaitAccepted, S_SendStreamByteWaitRdy,`
73			`S_Unknown);`
74
75			`constant CHAR_CAP_S : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(83, 8));`
76			`-- constant CHAR_S : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(115, 8));`
77			`constant START_NEW_FRAME_CHAR : std_logic_vector(7 downto 0) := CHAR_CAP_S;`
78
79			`constant ZERO_PADDING_C : std_logic_vector(15 downto 0) := (others => '0');`
80
81			`function boolean2sl(x : boolean)`
82			`return std_logic is`
83			`begin`
84			`if x then`
85			`return '1';`
86			`else`
87			`return '0';`
88			`end if;`
89			`end boolean2sl;`
90
91			`function sl2boolean(x : std_logic)`
92			`return boolean is`
93			`begin`
94			`if x = '1' then`
95			`return TRUE;`
96			`else`
97			`return FALSE;`
98			`end if;`
99			`end sl2boolean;`
100
101			`--State machine signals`
102			`signal state, state_next : state_type := S_Start;`
103
104			`--Signals to connect the CCITT4 module`
105			`signal run_len_code_CCITT4 : STD_LOGIC_VECTOR(MAX_CODE_LEN_G - 1 downto 0) := (others => '0');`
106			`signal run_len_code_width_CCITT4 : STD_LOGIC_VECTOR(MAX_CODE_LEN_WIDTH_G - 1 downto 0) := (others => '0');`
107			`signal run_len_code_valid_CCITT4 : STD_LOGIC := '0';`
108			`signal frame_finished_CCITT4 : STD_LOGIC := '0';`
109			`signal pix : STD_LOGIC := '0';`
110			`signal fax4_x : unsigned(COL_INDEX_WIDTH_G-1 downto 0) := (others => '0');`
111			`signal fax4_y : unsigned(ROW_INDEX_WIDTH_G-1 downto 0) := (others => '0');`
112
113			`--Signals to connect the byte segmentation module`
114			`signal seg_d1, seg_d2, seg_d3, seg_d4 : STD_LOGIC_VECTOR(SEG_OUTPUT_WIDTH_G-1 downto 0) := (others => '0');`
115			`signal seg_d_rdy1, seg_d_rdy2, seg_d_rdy3, seg_d_rdy4 : STD_LOGIC := '0';`
116			`signal seg_frame_finished_in : STD_LOGIC := '0';`
117			`signal seg_frame_finished_out : STD_LOGIC := '0';`
118			`signal seg_reset : STD_LOGIC := '0';`
119
120			`--Signals to connect the UART module`
121			`signal tx_data, rx_data : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');`
122			`signal rx_available, tx_buf_empty, tx_buf_empty_prev : STD_LOGIC := '0';`
123			`signal rx_trigger, tx_trigger : STD_LOGIC := '0';`
124			`signal uart_reset : STD_LOGIC := '0';`
125
126			`-- Tx memory`
127			`signal tx_mem_reset : STD_LOGIC := '0';`
128			`signal tx_mem_d_out : STD_LOGIC_VECTOR(TX_MEMORY_WIDTH_G-1 downto 0) := (others => '0');`
129			`signal tx_mem_read_addr : std_logic_vector(TX_MEMORY_ADDRESS_WIDTH_G-1 downto 0) := (others => '0');`
130			`signal tx_mem_used : unsigned(TX_MEMORY_ADDRESS_WIDTH_G-1 downto 0) := (others => '0');`
131
132			`--Other signals`
133			`signal fsync_prev : STD_LOGIC := '0';`
134			`signal tx_mem_overflow : std_logic := '0';`
135
136			`begin`
137	8	amulder	`CCITT4_ins : entity work.CCITT4_v2`
138	2	amulder	`Port Map(`
139			`pclk_i => pclk_i,`
140			`fsync_i => fsync_i,`
141			`rsync_i => rsync_i,`
142			`pix_i => pix,`
143			`run_len_code_o => run_len_code_CCITT4,`
144			`run_len_code_width_o => run_len_code_width_CCITT4,`
145			`run_len_code_valid_o => run_len_code_valid_CCITT4,`
146	8	amulder	`frame_finished_o => frame_finished_CCITT4`
147	2	amulder	`);`
148
149			`byte_segmentation_ins_v5 : entity work.byte_segmentation_v5`
150			`Generic Map(`
151			`INPUT_WIDTH_G => MAX_CODE_LEN_G,`
152			`OUTPUT_WIDTH_G => SEG_OUTPUT_WIDTH_G,`
153			`INDEX_WIDTH_G => MAX_CODE_LEN_WIDTH_G`
154			`)`
155			`Port Map(`
156			`reset_i => seg_reset,`
157			`clk_i => pclk_i,`
158			`pclk_i => pclk_i,`
159			`d_i => run_len_code_CCITT4,`
160			`d_width_i => run_len_code_width_CCITT4,`
161			`d_rdy_i => run_len_code_valid_CCITT4,`
162			`d1_o => seg_d1,`
163			`d_rdy1_o => seg_d_rdy1,`
164			`d2_o => seg_d2,`
165			`d_rdy2_o => seg_d_rdy2,`
166			`d3_o => seg_d3,`
167			`d_rdy3_o => seg_d_rdy3,`
168			`d4_o => seg_d4,`
169			`d_rdy4_o => seg_d_rdy4,`
170			`frame_finished_i => seg_frame_finished_in,`
171			`frame_finished_o => seg_frame_finished_out`
172			`);`
173			`seg_frame_finished_in <= frame_finished_CCITT4;`
174
175			`var_width_RAM_ins : entity work.var_width_RAM`
176			`generic map(`
177			`MEM_SIZE_G => TX_MEMORY_SIZE_G,`
178			`MEM_INDEX_WIDTH_G => TX_MEMORY_ADDRESS_WIDTH_G,`
179			`DATA_WIDTH_G => TX_MEMORY_WIDTH_G`
180			`)`
181			`port map(`
182			`reset_i => tx_mem_reset,`
183			`clk_i => pclk_i,`
184			`wr1_i => seg_d_rdy1,`
185			`d1_i => seg_d1,`
186			`wr2_i => seg_d_rdy2,`
187			`d2_i => seg_d2,`
188			`wr3_i => seg_d_rdy3,`
189			`d3_i => seg_d3,`
190			`wr4_i => seg_d_rdy4,`
191			`d4_i => seg_d4,`
192			`rd_addr_i => tx_mem_read_addr,`
193			`d_o => tx_mem_d_out,`
194			`used_o => tx_mem_used`
195			`);`
196
197			`UART_ins : entity work.UartComponent`
198			`Generic Map(`
199			`BAUD_DIVIDE_G => BAUD_DIVIDE_G,`
200			`BAUD_RATE_G => BAUD_RATE_G`
201			`)`
202			`Port Map(`
203			`TXD => TX_o,`
204			`RXD => RX_i,`
205			`CLK => pclk_i,`
206			`DBIN => tx_data,`
207			`DBOUT => rx_data,`
208			`RDA => rx_available,`
209			`TBE => tx_buf_empty,`
210			`RD => rx_trigger,`
211			`WR => tx_trigger,`
212			`PE => open,`
213			`FE => open,`
214			`OE => open,`
215			`RST => uart_reset`
216			`);`
217
218			`decode_state_process : process(reset_i, pclk_i)`
219			`begin`
220			`if reset_i = '1' then`
221			`state <= S_Start;`
222			`elsif pclk_i'event and pclk_i = '1' then`
223			`state <= state_next;`
224			`else`
225			`state <= state;`
226			`end if;`
227			`end process decode_state_process;`
228
229			`decode_next_state : process (reset_i, pclk_i, fsync_i, tx_buf_empty)`
230			`begin`
231			`if pclk_i'event and pclk_i = '1' then`
232			`fsync_prev <= fsync_i;`
233			`uart_reset <= '0';`
234			`rx_trigger <= '0';`
235			`tx_trigger <= '0';`
236			`tx_buf_empty_prev <= tx_buf_empty;`
237
238			`case (state) is`
239			`when S_Start =>`
240			`state_next <= S_WaitForChar;`
241			`uart_reset <= '1';`
242
243			`when S_WaitForChar =>`
244			`if rx_available = '1' and rx_data = START_NEW_FRAME_CHAR then`
245			`state_next <= S_WaitForNewFrame;`
246			`rx_trigger <= '1';`
247			`elsif rx_available = '1' then`
248			`rx_trigger <= '1';`
249			`tx_data <= rx_data;`
250			`tx_trigger <= '1';`
251			`state_next <= state_next;`
252			`else`
253			`state_next <= state_next;`
254			`end if;`
255
256			`when S_WaitForNewFrame =>`
257			`if fsync_prev = '0' and fsync_i = '1' then`
258			`state_next <= S_CaptureStoreFrame;`
259			`else`
260			`state_next <= state_next;`
261			`end if;`
262
263			`when S_CaptureStoreFrame =>`
264			`if seg_frame_finished_out = '1' then`
265			`state_next <= S_SendSizeB1;`
266			`else`
267			`state_next <= state_next;`
268			`end if;`
269
270			`when S_SendSizeB1 =>`
271			`state_next <= S_SendSizeB1WaitRdy;`
272			`tx_data <= std_logic_vector(tx_mem_used(7 downto 0));`
273			`tx_trigger <= '1';`
274			`when S_SendSizeB1WaitRdy =>`
275			`if tx_buf_empty_prev = '0' and tx_buf_empty = '1' then`
276			`state_next <= S_SendSizeB2;`
277			`else`
278			`state_next <= state_next;`
279			`end if;`
280			`when S_SendSizeB2 =>`
281			`state_next <= S_SendSizeB2WaitRdy;`
282			`tx_data <= ZERO_PADDING_C(16-1 downto TX_MEMORY_ADDRESS_WIDTH_G) & std_logic_vector(tx_mem_used(TX_MEMORY_ADDRESS_WIDTH_G-1 downto 8));`
283			`tx_trigger <= '1';`
284
285			`when S_SendSizeB2WaitRdy =>`
286			`if tx_buf_empty_prev = '0' and tx_buf_empty = '1' then`
287			`state_next <= S_SendStreamByte;`
288			`else`
289			`state_next <= state_next;`
290			`end if;`
291
292			`when S_SendStreamByte =>`
293			`state_next <= S_SendStreamByteWaitAccepted;`
294			`tx_data <= tx_mem_d_out;`
295			`tx_trigger <= '1';`
296			`when S_SendStreamByteWaitAccepted =>`
297			`if tx_buf_empty = '0' then`
298			`state_next <= S_SendStreamByteWaitRdy;`
299			`end if;`
300
301			`when S_SendStreamByteWaitRdy =>`
302			`if tx_buf_empty = '1' then`
303			`if unsigned(tx_mem_read_addr) = tx_mem_used then`
304			`state_next <= S_Start;`
305			`else`
306			`state_next <= S_SendStreamByte;`
307			`end if;`
308			`else`
309			`state_next <= state_next;`
310			`end if;`
311
312			`when S_Unknown =>`
313
314			`when others =>`
315			`state_next <= S_Unknown;`
316			`end case;`
317			`end if;`
318			`end process decode_next_state;`
319
320			`-- Detection of memory overflow and notification to the user.`
321			`mem_overflow_detection_process : process(pclk_i)`
322			`begin`
323			`if pclk_i'event and pclk_i = '1' then`
324			`if reset_i = '1' then`
325			`tx_mem_overflow <= '0';`
326			`elsif tx_mem_used >= to_unsigned(TX_MEMORY_SIZE_G, 16) then`
327			`tx_mem_overflow <= '1';`
328			`else`
329			`tx_mem_overflow <= tx_mem_overflow;`
330			`end if;`
331			`end if;`
332			`end process mem_overflow_detection_process;`
333
334			`led0_o <= boolean2sl(state = S_WaitForChar);`
335			`led1_o <= boolean2sl(state = S_CaptureStoreFrame);`
336			`led2_o <= boolean2sl(state = S_SendSizeB1)`
337			`or boolean2sl(state = S_SendSizeB2)`
338			`or boolean2sl(state = S_SendSizeB1WaitRdy)`
339			`or boolean2sl(state = S_SendSizeB2WaitRdy)`
340			`or boolean2sl(state = S_SendStreamByte)`
341			`or boolean2sl(state = S_SendStreamByteWaitAccepted)`
342			`or boolean2sl(state = S_SendStreamByteWaitRdy);`
343			`led3_o <= tx_mem_overflow;`
344
345			`pix <= pix_data_i(7)`
346			`when unsigned(tx_mem_used) < (to_unsigned(TX_MEMORY_SIZE_G, TX_MEMORY_ADDRESS_WIDTH_G) - to_unsigned(ROWS_G, TX_MEMORY_ADDRESS_WIDTH_G))`
347			`else '1';`
348
349			`--Data segmentation tasks`
350			`seg_reset <= '0' when state = S_CaptureStoreFrame else '1';`
351			`tx_mem_reset <= '1' when state = S_WaitForNewFrame else '0';`
352
353			`--Transmission memory read pointer incrementation`
354			`tx_mem_read_write_pos_process : process(pclk_i)`
355			`begin`
356			`if pclk_i'event and pclk_i = '1' then`
357			`if state = S_WaitForNewFrame then`
358			`tx_mem_read_addr <= (others => '0');`
359			`elsif (tx_trigger = '1')`
360			`and unsigned(tx_mem_read_addr) /= tx_mem_used`
361			`and state = S_SendStreamByte then`
362			`tx_mem_read_addr <= std_logic_vector(unsigned(tx_mem_read_addr) + to_unsigned(1, TX_MEMORY_ADDRESS_WIDTH_G));`
363			`else`
364			`tx_mem_read_addr <= tx_mem_read_addr;`
365			`end if;`
366			`end if;`
367			`end process tx_mem_read_write_pos_process;`
368
369			`-- Other tasks`
370			`vgaRed <= pix_data_i(7 downto 5) when sw_i(0) = '0' else pix_data_i(7) & pix_data_i(7) & pix_data_i(7);`
371			`vgaGreen <= pix_data_i(7 downto 5) when sw_i(0) = '0' else pix_data_i(7) & pix_data_i(7) & pix_data_i(7);`
372			`vgaBlue <= pix_data_i(7 downto 6) when sw_i(0) = '0' else pix_data_i(7) & pix_data_i(7);`
373			`vga_fsync_o <= fsync_i;`
374			`vga_rsync_o <= rsync_i;`
375	8	amulder
376			`CCITT4_run_len_code_o <= run_len_code_CCITT4;`
377			`CCITT4_run_len_code_width_o <= run_len_code_width_CCITT4;`
378			`CCITT4_run_len_code_valid_o <= run_len_code_valid_CCITT4;`
379			`CCITT4_frame_finished_o <= frame_finished_CCITT4;`
380	2	amulder
381			`end Behavioral;`