OpenCores
URL https://opencores.org/ocsvn/c0or1k/c0or1k/trunk

Subversion Repositories c0or1k

[/] [c0or1k/] [trunk/] [conts/] [libdev/] [timer/] [omap/] [timer.c] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 drasko
/*
2
 * omap GP timer driver honoring generic
3
 * timer library API
4
 *
5
 * Copyright (C) 2010 B Labs Ltd.
6
 *
7
 * Author: Bahadir Balban
8
 */
9
 
10
#include <libdev/io.h>
11
#include <l4lib/types.h>
12
#include "timer.h"
13
 
14
#define OMAP_TIMER_MAT_IT_FLAG  (1 << 0)
15
#define OMAP_TIMER_OVR_IT_FLAG  (1 << 1)
16
#define OMAP_TIMER_TCAR_IT_FLAG (1 << 2)
17
u32 timer_periodic_intr_status(unsigned long timer_base)
18
{
19
        volatile u32 reg = read(timer_base + OMAP_TIMER_TISR);
20
        return (reg & OMAP_TIMER_OVR_IT_FLAG);
21
}
22
 
23
#define OMAP_TIMER_SOFT_RESET   (1 << 1)
24
void timer_reset(unsigned long timer_base)
25
{
26
        /* Reset Timer */
27
        write(OMAP_TIMER_SOFT_RESET, timer_base + OMAP_TIMER_TIOCP);
28
 
29
        /* Wait for reset completion */
30
        while (!read(timer_base + OMAP_TIMER_TSTAT));
31
}
32
 
33
void timer_load(unsigned long timer_base, u32 value)
34
{
35
        write(value, timer_base + OMAP_TIMER_TLDR);
36
        write(value, timer_base + OMAP_TIMER_TCRR);
37
}
38
 
39
u32 timer_read(unsigned long timer_base)
40
{
41
        return read(timer_base + OMAP_TIMER_TCRR);
42
}
43
 
44
#define OMAP_TIMER_START        (1 << 0)
45
void timer_start(unsigned long timer_base)
46
{
47
        volatile u32 reg = read(timer_base + OMAP_TIMER_TCLR);
48
        reg |= OMAP_TIMER_START;
49
        write(reg, timer_base + OMAP_TIMER_TCLR);
50
}
51
 
52
void timer_stop(unsigned long timer_base)
53
{
54
        volatile u32 reg = read(timer_base + OMAP_TIMER_TCLR);
55
        reg &= (~OMAP_TIMER_START);
56
        write(reg, timer_base + OMAP_TIMER_TCLR);
57
}
58
 
59
void timer_init_periodic(unsigned long timer_base)
60
{
61
        volatile u32 reg;
62
 
63
        /* Reset the timer */
64
        timer_reset(timer_base);
65
 
66
        /* Set timer to autoreload mode */
67
        reg = read(timer_base + OMAP_TIMER_TCLR);
68
        reg |= (1 << OMAP_TIMER_MODE_AUTORELAOD);
69
        write(reg, timer_base + OMAP_TIMER_TCLR);
70
 
71
        /*
72
        * Beagle Board RevC manual:
73
        * overflow period = (0xffffffff - TLDR + 1)*PS*(1/TIMER_FCLK)
74
        * where,
75
        * PS: Prescaler divisor (we are not using this)
76
        *
77
        * Beagle board manual says, 26MHz oscillator present on board.
78
        * U-Boot divides the sys_clock by 2 if sys_clk is >19MHz,
79
        * so,we have sys_clk frequency = 13MHz
80
        *
81
        * TIMER_FCLK = 13MHz
82
        * So, for 1ms period, TLDR = 0xffffcd38
83
        *
84
        */
85
        timer_load(timer_base, 0xffffcd38);
86
 
87
        /* Clear pending Interrupts, if any */
88
        write(7, timer_base + OMAP_TIMER_TISR);
89
 
90
        /* Enable inteerupts */
91
        write((1 << OMAP_TIMER_INTR_OVERFLOW), timer_base + OMAP_TIMER_TIER);
92
}
93
 
94
void timer_init(unsigned long timer_base)
95
{
96
        timer_init_periodic(timer_base);
97
}

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.