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.TH L4_CACHE_CONTROL 7 2009-11-07 "Codezero" "Codezero Programmer's Manual"

.SH NAME

.nf

.BR "l4_cache_control" " - Cache/TLB manipulation"

.SH SYNOPSIS

.nf

.B #include 

.B #include 

.BI "int l4_cache_control (unsigned int " "start" ", unsigned int " "end" ", unsigned int " "flags");

.SH DESCRIPTION

.B l4_cache_control()

enables a thread to invalidate and clean the cache memory.

.TP

.fi

.I start

denotes the start address(virtual memory address) of memory region to be invalidated/cleaned. This is not used in case of armv5.

.TP

.fi

.I end

denotes the end address(virtual memory address) of memory region to be invalidated/cleaned. This is not used in case of armv5.

.TP

.fi

.I flags

denotes the operation to be performed.

.TP

.BR L4_INVALIDATE_CACHE

Invalidate/flush both I and D caches.

.TP

.BR L4_INVALIDATE_ICACHE

Invalidate/flush I cache.

.TP

.BR L4_INVALIDATE_DCACHE

Invalidate/flush D cache.

.TP

.BR L4_CLEAN_DCACHE

Clean D cache.

.TP

.BR L4_CLEAN_INVALIDATE_DCACHE

Clean and Invalidate D cache.

.TP

.BR L4_CLEAN_INVALIDATE_CACHE

Invalidate/flush both I and D cache and Clean D cache.

.TP

.BR L4_DRAIN_WRITEBUFFER

Drain Write Buffer.

.TP

.BR L4_INVALIDATE_TLB

Invalidate/flush TLB.

.TP

.BR L4_INVALIDATE_ITLB

Invalidate/flush I TLB.

.TP

.BR L4_INVALIDATE_DTLB

Invalidate/flush D TLB.

.SH RETURN VALUE

.IR "l4_cache_control"()

Returns 0 on success, and negative value on failure. See below for error codes.

.SH ERRORS

.TP

.B -EINVAL

when a

.IR "flag"

is passed with invalid fields.