| 1 |
2 |
drasko |
/*
|
| 2 |
|
|
*
|
| 3 |
|
|
* Describes physical memory layout of Beagle Boards.
|
| 4 |
|
|
* We have rev3 boards.
|
| 5 |
|
|
*
|
| 6 |
|
|
* Copyright (C) 2007 Bahadir Balban
|
| 7 |
|
|
*/
|
| 8 |
|
|
|
| 9 |
|
|
#ifndef __PLATFORM_BEAGLE_OFFSETS_H__
|
| 10 |
|
|
#define __PLATFORM_BEAGLE_OFFSETS_H__
|
| 11 |
|
|
|
| 12 |
|
|
/*
|
| 13 |
|
|
* Physical memory base
|
| 14 |
|
|
* FIXME: Somewhere its written: Rev 1 and 2
|
| 15 |
|
|
* of Beagleboard has 128MB SDRAM while Rev 3 has 256MB
|
| 16 |
|
|
* SDRAM which is detected automatically on intiliazation,
|
| 17 |
|
|
* we have Rev3 boards, so hardcoding this only.
|
| 18 |
|
|
*/
|
| 19 |
|
|
#define PLATFORM_PHYS_MEM_START 0x80000000 /* inclusive */
|
| 20 |
|
|
#define PLATFORM_PHYS_MEM_END 0x90000000 /* 256MB, exclusive */
|
| 21 |
|
|
|
| 22 |
|
|
/*
|
| 23 |
|
|
* Device offsets in physical memory
|
| 24 |
|
|
* Naming of devices done starting with 0 subscript,
|
| 25 |
|
|
* as we use these names for device capability
|
| 26 |
|
|
*/
|
| 27 |
|
|
#define PLATFORM_WKUP_CM_BASE 0x48004C00 /* Wake up clock manager */
|
| 28 |
|
|
#define PLATFORM_PERCM_BASE 0x48005000 /* Peripheral Clock Manager */
|
| 29 |
|
|
#define PLATFORM_UART0_BASE 0x4806A000 /* UART 0 */
|
| 30 |
|
|
#define PLATFORM_UART1_BASE 0x4806C000 /* UART 1 */
|
| 31 |
|
|
#define PLATFORM_UART2_BASE 0x49020000 /* UART 2 */
|
| 32 |
|
|
#define PLATFORM_TIMER0_BASE 0x48318000 /* GPTIMER1 */
|
| 33 |
|
|
#define PLATFORM_TIMER1_BASE 0x49032000 /* GPTIMER2 */
|
| 34 |
|
|
#define PLATFORM_TIMER2_BASE 0x49034000 /* GPTIMER3 */
|
| 35 |
|
|
#define PLATFORM_TIMER3_BASE 0x49036000 /* GPTIMER4 */
|
| 36 |
|
|
#define PLATFORM_TIMER4_BASE 0x49038000 /* GPTIMER5 */
|
| 37 |
|
|
#define PLATFORM_TIMER5_BASE 0x4903A000 /* GPTIMER6 */
|
| 38 |
|
|
#define PLATFORM_TIMER6_BASE 0x4903C000 /* GPTIMER7 */
|
| 39 |
|
|
#define PLATFORM_TIMER7_BASE 0x4903E000 /* GPTIMER8 */
|
| 40 |
|
|
#define PLATFORM_TIMER8_BASE 0x49040000 /* GPTIMER9 */
|
| 41 |
|
|
#define PLATFORM_TIMER9_BASE 0x48086000 /* GPTIMER10 */
|
| 42 |
|
|
#define PLATFORM_TIMER10_BASE 0x48088000 /* GPTIMER11 */
|
| 43 |
|
|
#define PLATFORM_TIMER11_BASE 0x48304000 /* GPTIMER12 */
|
| 44 |
|
|
#define PLATFORM_INTC_BASE 0x48200000 /* Interrupt controller */
|
| 45 |
|
|
|
| 46 |
|
|
/*
|
| 47 |
|
|
* Virtual Memory base address, where devices will be mapped.
|
| 48 |
|
|
* Each Device will take one page in virtual memory.
|
| 49 |
|
|
* Nice and smooth.
|
| 50 |
|
|
*/
|
| 51 |
|
|
#define DEVICE_PAGE 0x1000
|
| 52 |
|
|
|
| 53 |
|
|
#define PLATFORM_WKUP_CM_VBASE (IO_AREA0_VADDR + (0 * DEVICE_PAGE))
|
| 54 |
|
|
#define PLATFORM_CONSOLE_VBASE (IO_AREA0_VADDR + (1 * DEVICE_PAGE))
|
| 55 |
|
|
#define PLATFORM_TIMER0_VBASE (IO_AREA0_VADDR + (2 * DEVICE_PAGE))
|
| 56 |
|
|
#define PLATFORM_INTC_VBASE (IO_AREA0_VADDR + (3 * DEVICE_PAGE))
|
| 57 |
|
|
#define PLATFORM_PERCM_VBASE (IO_AREA0_VADDR + (4 * DEVICE_PAGE))
|
| 58 |
|
|
|
| 59 |
|
|
/* Add userspace devices here as they become necessary for irqs */
|
| 60 |
|
|
#define PLATFORM_TIMER1_VBASE (IO_AREA0_VADDR + (5 * DEVICE_PAGE))
|
| 61 |
|
|
|
| 62 |
|
|
/* Add size of various user space devices, to be used in capability generation */
|
| 63 |
|
|
#define PLATFORM_TIMER1_SIZE DEVICE_PAGE
|
| 64 |
|
|
|
| 65 |
|
|
#endif /* __PLATFORM_BEAGLE_OFFSETS_H__ */
|
| 66 |
|
|
|
