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[/] [c0or1k/] [trunk/] [include/] [l4/] [platform/] [eb/] [offsets.h] - Blame information for rev 7

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Line No. Rev Author Line
1 2 drasko
/*
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 * Describes physical memory layout of EB platform.
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 *
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 * This only include physical and memory offsets that
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 * are not included in realview/offsets.h
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 *
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 * Copyright (C) 2009 B Labs Ltd.
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 * Author: Prem Mallappa <prem.mallappa@b-labs.co.uk>
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 */
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#ifndef __PLATFORM_EB_OFFSETS_H__
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#define __PLATFORM_EB_OFFSETS_H__
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#include <l4/platform/realview/offsets.h>
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/* Device offsets in physical memory */
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#define PLATFORM_GIC1_BASE              0x10040000 /* GIC 1 */
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#define PLATFORM_GIC2_BASE              0x10050000 /* GIC 2 */
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#define PLATFORM_GIC3_BASE              0x10060000 /* GIC 3 */
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#define PLATFORM_GIC4_BASE              0x10070000 /* GIC 4 */
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/*
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 * Virtual device offsets for EB platform - starting from
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 * the last common realview virtual device offset
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 */
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#define MPCORE_PRIVATE_VBASE            (IO_AREA0_VADDR + (14 * DEVICE_PAGE))
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#if defined (CONFIG_CPU_CORTEXA9)
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#define MPCORE_PRIVATE_BASE             0x1F000000
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#endif  /* End CORTEXA9 */
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#if defined (CONFIG_CPU_ARM11MPCORE)
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#if defined REV_C || defined REV_D
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#define MPCORE_PRIVATE_BASE             0x1F000000
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#else  /* REV_B and QEMU */
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#define MPCORE_PRIVATE_BASE             0x10100000
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#endif /* End REV_B and QEMU */
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#endif /* End ARM11MPCORE */
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#if defined (CONFIG_CPU_CORTEXA9) || defined (CONFIG_CPU_ARM11MPCORE)
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/* MPCore private memory region */
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#define SCU_BASE                MPCORE_PRIVATE_BASE
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#define SCU_VBASE               MPCORE_PRIVATE_VBASE
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#define GIC0_CPU_VBASE          (MPCORE_PRIVATE_VBASE + 0x100)
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#define GIC0_DIST_VBASE         (MPCORE_PRIVATE_VBASE + 0x1000)
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#endif /* End CORTEXA9 || ARM11MPCORE */
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#define GIC1_CPU_VBASE          (PLATFORM_GIC1_VBASE + 0x0)
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#define GIC2_CPU_VBASE          (PLATFORM_GIC2_VBASE + 0x0)
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#define GIC3_CPU_VBASE          (PLATFORM_GIC3_VBASE + 0x0)
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#define GIC4_CPU_VBASE          (PLATFORM_GIC4_VBASE + 0x0)
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#define GIC1_DIST_VBASE         (PLATFORM_GIC1_VBASE + 0x1000)
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#define GIC2_DIST_VBASE         (PLATFORM_GIC2_VBASE + 0x1000)
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#define GIC3_DIST_VBASE         (PLATFORM_GIC3_VBASE + 0x1000)
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#define GIC4_DIST_VBASE         (PLATFORM_GIC4_VBASE + 0x1000)
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#if defined (CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
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#define PLATFORM_IRQCTRL0_VIRTUAL               EB_GIC0_VBASE
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#endif
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#define PLATFORM_IRQCTRL1_VIRTUAL               EB_GIC1_VBASE
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#endif /* __PLATFORM_EB_OFFSETS_H__ */
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