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drasko |
/*
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* ARM v5 specific init routines
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*
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* Copyright (C) 2007 - 2010 B Labs Ltd.
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*/
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#include <l4/generic/tcb.h>
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#include <l4/generic/scheduler.h>
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#include <l4/generic/platform.h>
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#include INC_SUBARCH(mm.h)
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#include INC_SUBARCH(mmu_ops.h)
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#include INC_GLUE(memory.h)
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#include INC_GLUE(mapping.h)
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#include INC_ARCH(linker.h)
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SECTION(".data.pgd") ALIGN(PGD_SIZE) pgd_table_t init_pgd;
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struct address_space init_space;
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void system_identify(void)
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{
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}
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void jump(struct ktcb *task)
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{
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__asm__ __volatile__ (
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"mov lr, %0\n" /* Load pointer to context area */
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"ldr r0, [lr]\n" /* Load spsr value to r0 */
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"msr spsr, r0\n" /* Set SPSR as ARM_MODE_USR */
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"add sp, lr, %1\n" /* Reset SVC stack */
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"sub sp, sp, %2\n" /* Align to stack alignment */
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"ldmib lr, {r0-r14}^\n" /* Load all USR registers */
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"nop \n" /* Spec says dont touch banked registers
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* right after LDM {no-pc}^ for one instruction */
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"add lr, lr, #64\n" /* Manually move to PC location. */
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"ldr lr, [lr]\n" /* Load the PC_USR to LR */
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"movs pc, lr\n" /* Jump to userspace, also switching SPSR/CPSR */
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:
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: "r" (task), "r" (PAGE_SIZE), "r" (STACK_ALIGNMENT)
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);
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}
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void switch_to_user(struct ktcb *task)
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{
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arm_clean_invalidate_cache();
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arm_invalidate_tlb();
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arm_set_ttb(virt_to_phys(TASK_PGD(task)));
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arm_invalidate_tlb();
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jump(task);
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}
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/* Maps the early memory regions needed to bootstrap the system */
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void init_kernel_mappings(void)
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{
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//memset((void *)virt_to_phys(&init_pgd), 0, sizeof(pgd_table_t));
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/* Map kernel area to its virtual region */
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add_section_mapping_init(align(virt_to_phys(_start_text), SZ_1MB),
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align((unsigned int)_start_text, SZ_1MB), 1,
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cacheable | bufferable);
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/* Map kernel one-to-one to its physical region */
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add_section_mapping_init(align(virt_to_phys(_start_text), SZ_1MB),
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align(virt_to_phys(_start_text), SZ_1MB),
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1, 0);
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}
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/*
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* Enable virtual memory using kernel's pgd
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* and continue execution on virtual addresses.
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*/
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void start_virtual_memory()
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{
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/*
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* TTB must be 16K aligned. This is because first level tables are
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* sized 16K.
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*/
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if ((unsigned int)&init_pgd & 0x3FFF)
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dprintk("kspace not properly aligned for ttb:",
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(u32)&init_pgd);
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// memset((void *)&kspace, 0, sizeof(pgd_table_t));
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arm_set_ttb(virt_to_phys(&init_pgd));
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/*
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* This sets all 16 domains to zero and domain 0 to 1. The outcome
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* is that page table access permissions are in effect for domain 0.
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* All other domains have no access whatsoever.
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*/
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arm_set_domain(1);
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/* Enable everything before mmu permissions are in place */
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arm_enable_caches();
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arm_enable_wbuffer();
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arm_enable_high_vectors();
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/*
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* Leave the past behind. Tlbs are invalidated, write buffer is drained.
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* The whole of I + D caches are invalidated unconditionally. This is
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* important to ensure that the cache is free of previously loaded
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* values. Otherwise unpredictable data aborts may occur at arbitrary
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* times, each time a load/store operation hits one of the invalid
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* entries and those entries are cleaned to main memory.
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*/
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arm_invalidate_cache();
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arm_drain_writebuffer();
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arm_invalidate_tlb();
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arm_enable_mmu();
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/* Jump to virtual memory addresses */
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__asm__ __volatile__ (
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"add sp, sp, %0 \n" /* Update stack pointer */
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"add fp, fp, %0 \n" /* Update frame pointer */
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/* On the next instruction below, r0 gets
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* current PC + KOFFSET + 2 instructions after itself. */
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"add r0, pc, %0 \n"
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/* Special symbol that is extracted and included in the loader.
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* Debuggers can break on it to load the virtual symbol table */
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".global break_virtual;\n"
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"break_virtual:\n"
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"mov pc, r0 \n" /* (r0 has next instruction) */
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:
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: "r" (KERNEL_OFFSET)
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: "r0"
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);
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/*
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* Restore link register (LR) for this function.
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*
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* NOTE: LR values are pushed onto the stack at each function call,
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* which means the restored return values will be physical for all
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* functions in the call stack except this function. So the caller
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* of this function must never return but initiate scheduling etc.
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*/
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__asm__ __volatile__ (
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"add %0, %0, %1 \n"
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"mov pc, %0 \n"
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:: "r" (__builtin_return_address(0)), "r" (KERNEL_OFFSET)
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);
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/* should never come here */
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while(1);
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}
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