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[/] [c0or1k/] [trunk/] [src/] [platform/] [realview/] [cpuperf.S.ARM] - Blame information for rev 6

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Line No. Rev Author Line
1 2 drasko
/*
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 * CPU cycles per timer tick
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 *
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 * Copyright (C) 2010 B Labs Ltd.
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 *
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 * Author: Bahadir Balban
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 */
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#define CPUOP_NOOP      0
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#define CPUOP_MEMORY    1
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#include INC_ARCH(asm.h)
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        .section .text
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/*
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 * Default:
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 * Go for 1000 CPU cycles on no ops and calculate
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 * how many timer ticks it takes.
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 *
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 * By default timer is expected to tick per 1/1,000,000 second,
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 * has been preloaded, and initialized for enabling. All we do
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 * here is enable it, do our ops and read back the counter
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 * difference.
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 *
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 * r0 = timer enable address
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 * r1 = timer value address
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 * r2 = op type
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 * r3 = op count
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 * return = how many timer ticks
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 */
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BEGIN_PROC(cpu_do_cycles_and_tick)
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        stmfd sp!, {r4, lr}     @ Make room for new data in r4-5
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        ldr r4, [r1]            @ Load timer value to r5
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        str r2, [r0]            @ Start the timer.
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1:
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        subs r3, r3, #1         @ Decrement count
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        bhi 1b
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finish:
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        ldr r0, [r1, #4]        @ Load current value, from load register + 4
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        sub r0, r4, r0          @ Return difference between original and read
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        ldmfd sp!, {r4, pc}     @ Restore R4-R5, pc
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BEGIN_PROC(busy_loop)
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        subs r0, r0, #1
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        bhi busy_loop
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        mov pc, lr
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END_PROC(busy_loop)
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