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[/] [c16/] [tags/] [V10/] [vhdl/] [cpu.vhd] - Blame information for rev 26

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
use work.cpu_pack.ALL;
 
library UNISIM;
use UNISIM.VComponents.all;
 
entity cpu16 is
        PORT(   CLK_I                   : in  STD_LOGIC;
                        T2                              : out STD_LOGIC;
                        SWITCH                  : in  STD_LOGIC_VECTOR (9 downto 0);
 
                        SER_IN                  : in  STD_LOGIC;
                        SER_OUT                 : out STD_LOGIC;
 
                        TEMP_SPO                : in  STD_LOGIC;
                        TEMP_SPI                : out STD_LOGIC;
 
                        TEMP_CE                 : out STD_LOGIC;
                        TEMP_SCLK               : out STD_LOGIC;
                        SEG1                    : out STD_LOGIC_VECTOR (7 downto 0);
                        SEG2                    : out STD_LOGIC_VECTOR (7 downto 0);
                        LED                             : out STD_LOGIC_VECTOR( 7 downto 0);
 
                        XM_ADR                  : out STD_LOGIC_VECTOR(15 downto 0);
                        XM_RDAT                 : in  STD_LOGIC_VECTOR( 7 downto 0);
                        XM_WDAT                 : out STD_LOGIC_VECTOR( 7 downto 0);
                        XM_WE                   : out STD_LOGIC;
                        XM_CE                   : out STD_LOGIC
            );
end cpu16;
 
architecture behavioral of cpu16 is
 
        COMPONENT bin_to_7segment
        PORT(   CLK_I : IN std_logic;
                        T2    : IN std_logic;
                        PC    : IN std_logic_vector(15 downto 0);
                        SEG1  : OUT std_logic_vector(7 downto 1);
                        SEG2  : OUT std_logic_vector(7 downto 0)
                );
        END COMPONENT;
 
        COMPONENT cpu_engine
        PORT(   CLK_I    : in  std_logic;
                        T2       : out std_logic;
                        CLR      : in  std_logic;
                        Q_PC   : out std_logic_vector(15 downto 0);
                        Q_OPC  : out std_logic_vector( 7 downto 0);
                        Q_CAT  : out op_category;
                        Q_IMM  : out std_logic_vector(15 downto 0);
                        Q_CYC  : out cycle;
 
                        -- input/output
                        INT      : in  std_logic;
                        IO_ADR   : out std_logic_vector(7 downto 0);
                        IO_RD    : out std_logic;
                        IO_WR    : out std_logic;
                        IO_RDAT  : in  std_logic_vector( 7 downto 0);
 
                        -- memory
                        XM_ADR   : out std_logic_vector(15 downto 0);
                        XM_RDAT  : in  std_logic_vector( 7 downto 0);
                        XM_WDAT  : out std_logic_vector( 7 downto 0);
                        XM_WE    : out std_logic;
                        XM_CE    : out std_logic;
 
                        -- select signals
                        Q_SX    : out std_logic_vector(1 downto 0);
                        Q_SY    : out std_logic_vector(3 downto 0);
                        Q_OP    : out std_logic_vector(4 downto 0);
                        Q_SA    : out std_logic_vector(4 downto 0);
                        Q_SMQ   : out std_logic;
 
                        -- write enable/select signal
                        Q_WE_RR  : out std_logic;
                        Q_WE_LL  : out std_logic;
                        Q_WE_SP  : out SP_OP;
 
                        Q_RR     : out std_logic_vector(15 downto 0);
                        Q_LL     : out std_logic_vector(15 downto 0);
                        Q_SP     : out std_logic_vector(15 downto 0);
                        HALT     : out std_logic
                );
        END COMPONENT;
 
        COMPONENT input_output
        PORT(   CLK_I        : IN std_logic;
                        T2           : IN std_logic;
                        CLR          : OUT std_logic;
 
                        TEMP_SPO     : IN  std_logic;
                        TEMP_SPI     : OUT std_logic;
                        TEMP_CE      : OUT std_logic;
                        TEMP_SCLK    : OUT std_logic;
 
                        SER_IN       : IN  std_logic;
                        SER_OUT      : OUT std_logic;
 
                        SWITCH       : IN  std_logic_vector(9 downto 0);
                        LED          : OUT std_logic_vector(7 downto 0);
 
                        IO_RD        : IN  std_logic;
                        IO_WR        : IN  std_logic;
                        IO_ADR       : IN  std_logic_vector(7 downto 0);
                        IO_WDAT      : IN  std_logic_vector(7 downto 0);
                        IO_RDAT      : OUT std_logic_vector(7 downto 0);
                        INT          : OUT std_logic;
                        HALT         : in  std_logic
                );
        END COMPONENT;
 
        signal CLR      : std_logic;
        signal LT2      : std_logic;
 
        signal ADR      : std_logic_vector(15 downto 0);
 
        signal HALT     : std_logic;
        signal INT      : std_logic;
        signal IO_RD    : std_logic;
        signal IO_WR    : std_logic;
        signal IO_ADR   : std_logic_vector( 7 downto 0);
        signal IO_RDAT  : std_logic_vector( 7 downto 0);
        signal IOM_WDAT : std_logic_vector( 7 downto 0);
        signal PC       : std_logic_vector(15 downto 0);
 
        signal Q_C_SX    : std_logic_vector(1 downto 0);
        signal Q_C_SY    : std_logic_vector(3 downto 0);
        signal Q_C_OP    : std_logic_vector(4 downto 0);
        signal Q_C_SA    : std_logic_vector(4 downto 0);
        signal Q_C_SMQ   : std_logic;
 
        signal Q_C_WE_RR : std_logic;
        signal Q_C_WE_LL : std_logic;
        signal Q_C_WE_SP : SP_OP;
 
        signal Q_C_RR    : std_logic_vector(15 downto 0);
        signal Q_C_LL    : std_logic_vector(15 downto 0);
        signal Q_C_SP    : std_logic_vector(15 downto 0);
 
        signal Q_C_OPC   : std_logic_vector( 7 downto 0);
        signal Q_C_CAT   : op_category;
        signal Q_C_IMM   : std_logic_vector(15 downto 0);
        signal Q_C_CYC   : cycle;
 
begin
 
        T2      <= LT2;
        SEG1(0) <= HALT;
        XM_ADR  <= ADR;
        XM_WDAT <= IOM_WDAT;
 
        seg7: bin_to_7segment
        PORT MAP(       CLK_I => CLK_I,
                                T2    => LT2,
                                PC    => PC,
                                SEG1  => SEG1(7 downto 1),
                                SEG2  => SEG2
                        );
 
        eng: cpu_engine
        PORT MAP(       CLK_I     => CLK_I,
                                T2        => LT2,
                                CLR       => CLR,       -- SW-1 (RESET)
                                Q_PC      => PC,
                                Q_OPC     => Q_C_OPC,
                                Q_CAT     => Q_C_CAT,
                                Q_IMM     => Q_C_IMM,
                                Q_CYC     => Q_C_CYC,
 
                                INT       => INT,
                                IO_ADR    => IO_ADR,
                                IO_RD     => IO_RD,
                                IO_WR     => IO_WR,
                                IO_RDAT   => IO_RDAT,
 
                                XM_ADR    => ADR,
                                XM_RDAT   => XM_RDAT,
                                XM_WDAT   => IOM_WDAT,
                                XM_WE     => XM_WE,
                                XM_CE     => XM_CE,
 
                                Q_SX      => Q_C_SX,
                                Q_SY      => Q_C_SY,
                                Q_OP      => Q_C_OP,
                                Q_SA      => Q_C_SA,
                                Q_SMQ     => Q_C_SMQ,
 
                                Q_WE_RR   => Q_C_WE_RR,
                                Q_WE_LL   => Q_C_WE_LL,
                                Q_WE_SP   => Q_C_WE_SP,
 
                                Q_RR      => Q_C_RR,
                                Q_LL      => Q_C_LL,
                                Q_SP      => Q_C_SP,
                                HALT      => HALT
                        );
 
        io: input_output
        PORT MAP(       CLK_I        => CLK_I,
                                T2           => LT2,
                                CLR          => CLR,
 
                                TEMP_SPO     => TEMP_SPO,
                                TEMP_SPI     => TEMP_SPI,
                                TEMP_CE      => TEMP_CE,
                                TEMP_SCLK    => TEMP_SCLK,
 
                                SER_IN       => SER_IN,
                                SER_OUT      => SER_OUT,
 
                                SWITCH       => SWITCH,
                                LED          => LED,
 
                                IO_RD        => IO_RD,
                                IO_WR        => IO_WR,
                                IO_ADR       => IO_ADR,
                                IO_RDAT      => IO_RDAT,
                                IO_WDAT      => IOM_WDAT,
                                INT          => INT,
                                HALT         => HALT
                        );
 
end behavioral;

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[/] [c16/] [tags/] [V10/] [vhdl/] [cpu.vhd] - Blame information for rev 26

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3			`use IEEE.std_logic_unsigned.all;`
4
5			`use work.cpu_pack.ALL;`
6
7			`library UNISIM;`
8			`use UNISIM.VComponents.all;`
9
10			`entity cpu16 is`
11			`PORT( CLK_I : in STD_LOGIC;`
12			`T2 : out STD_LOGIC;`
13			`SWITCH : in STD_LOGIC_VECTOR (9 downto 0);`
14
15			`SER_IN : in STD_LOGIC;`
16			`SER_OUT : out STD_LOGIC;`
17
18			`TEMP_SPO : in STD_LOGIC;`
19			`TEMP_SPI : out STD_LOGIC;`
20
21			`TEMP_CE : out STD_LOGIC;`
22			`TEMP_SCLK : out STD_LOGIC;`
23			`SEG1 : out STD_LOGIC_VECTOR (7 downto 0);`
24			`SEG2 : out STD_LOGIC_VECTOR (7 downto 0);`
25			`LED : out STD_LOGIC_VECTOR( 7 downto 0);`
26
27			`XM_ADR : out STD_LOGIC_VECTOR(15 downto 0);`
28			`XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);`
29			`XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);`
30			`XM_WE : out STD_LOGIC;`
31			`XM_CE : out STD_LOGIC`
32			`);`
33			`end cpu16;`
34
35			`architecture behavioral of cpu16 is`
36
37			`COMPONENT bin_to_7segment`
38			`PORT( CLK_I : IN std_logic;`
39			`T2 : IN std_logic;`
40			`PC : IN std_logic_vector(15 downto 0);`
41			`SEG1 : OUT std_logic_vector(7 downto 1);`
42			`SEG2 : OUT std_logic_vector(7 downto 0)`
43			`);`
44			`END COMPONENT;`
45
46			`COMPONENT cpu_engine`
47			`PORT( CLK_I : in std_logic;`
48			`T2 : out std_logic;`
49			`CLR : in std_logic;`
50			`Q_PC : out std_logic_vector(15 downto 0);`
51			`Q_OPC : out std_logic_vector( 7 downto 0);`
52			`Q_CAT : out op_category;`
53			`Q_IMM : out std_logic_vector(15 downto 0);`
54			`Q_CYC : out cycle;`
55
56			`-- input/output`
57			`INT : in std_logic;`
58			`IO_ADR : out std_logic_vector(7 downto 0);`
59			`IO_RD : out std_logic;`
60			`IO_WR : out std_logic;`
61			`IO_RDAT : in std_logic_vector( 7 downto 0);`
62
63			`-- memory`
64			`XM_ADR : out std_logic_vector(15 downto 0);`
65			`XM_RDAT : in std_logic_vector( 7 downto 0);`
66			`XM_WDAT : out std_logic_vector( 7 downto 0);`
67			`XM_WE : out std_logic;`
68			`XM_CE : out std_logic;`
69
70			`-- select signals`
71			`Q_SX : out std_logic_vector(1 downto 0);`
72			`Q_SY : out std_logic_vector(3 downto 0);`
73			`Q_OP : out std_logic_vector(4 downto 0);`
74			`Q_SA : out std_logic_vector(4 downto 0);`
75			`Q_SMQ : out std_logic;`
76
77			`-- write enable/select signal`
78			`Q_WE_RR : out std_logic;`
79			`Q_WE_LL : out std_logic;`
80			`Q_WE_SP : out SP_OP;`
81
82			`Q_RR : out std_logic_vector(15 downto 0);`
83			`Q_LL : out std_logic_vector(15 downto 0);`
84			`Q_SP : out std_logic_vector(15 downto 0);`
85			`HALT : out std_logic`
86			`);`
87			`END COMPONENT;`
88
89			`COMPONENT input_output`
90			`PORT( CLK_I : IN std_logic;`
91			`T2 : IN std_logic;`
92			`CLR : OUT std_logic;`
93
94			`TEMP_SPO : IN std_logic;`
95			`TEMP_SPI : OUT std_logic;`
96			`TEMP_CE : OUT std_logic;`
97			`TEMP_SCLK : OUT std_logic;`
98
99			`SER_IN : IN std_logic;`
100			`SER_OUT : OUT std_logic;`
101
102			`SWITCH : IN std_logic_vector(9 downto 0);`
103			`LED : OUT std_logic_vector(7 downto 0);`
104
105			`IO_RD : IN std_logic;`
106			`IO_WR : IN std_logic;`
107			`IO_ADR : IN std_logic_vector(7 downto 0);`
108			`IO_WDAT : IN std_logic_vector(7 downto 0);`
109			`IO_RDAT : OUT std_logic_vector(7 downto 0);`
110			`INT : OUT std_logic;`
111			`HALT : in std_logic`
112			`);`
113			`END COMPONENT;`
114
115			`signal CLR : std_logic;`
116			`signal LT2 : std_logic;`
117
118			`signal ADR : std_logic_vector(15 downto 0);`
119
120			`signal HALT : std_logic;`
121			`signal INT : std_logic;`
122			`signal IO_RD : std_logic;`
123			`signal IO_WR : std_logic;`
124			`signal IO_ADR : std_logic_vector( 7 downto 0);`
125			`signal IO_RDAT : std_logic_vector( 7 downto 0);`
126			`signal IOM_WDAT : std_logic_vector( 7 downto 0);`
127			`signal PC : std_logic_vector(15 downto 0);`
128
129			`signal Q_C_SX : std_logic_vector(1 downto 0);`
130			`signal Q_C_SY : std_logic_vector(3 downto 0);`
131			`signal Q_C_OP : std_logic_vector(4 downto 0);`
132			`signal Q_C_SA : std_logic_vector(4 downto 0);`
133			`signal Q_C_SMQ : std_logic;`
134
135			`signal Q_C_WE_RR : std_logic;`
136			`signal Q_C_WE_LL : std_logic;`
137			`signal Q_C_WE_SP : SP_OP;`
138
139			`signal Q_C_RR : std_logic_vector(15 downto 0);`
140			`signal Q_C_LL : std_logic_vector(15 downto 0);`
141			`signal Q_C_SP : std_logic_vector(15 downto 0);`
142
143			`signal Q_C_OPC : std_logic_vector( 7 downto 0);`
144			`signal Q_C_CAT : op_category;`
145			`signal Q_C_IMM : std_logic_vector(15 downto 0);`
146			`signal Q_C_CYC : cycle;`
147
148			`begin`
149
150			`T2 <= LT2;`
151			`SEG1(0) <= HALT;`
152			`XM_ADR <= ADR;`
153			`XM_WDAT <= IOM_WDAT;`
154
155			`seg7: bin_to_7segment`
156			`PORT MAP( CLK_I => CLK_I,`
157			`T2 => LT2,`
158			`PC => PC,`
159			`SEG1 => SEG1(7 downto 1),`
160			`SEG2 => SEG2`
161			`);`
162
163			`eng: cpu_engine`
164			`PORT MAP( CLK_I => CLK_I,`
165			`T2 => LT2,`
166			`CLR => CLR, -- SW-1 (RESET)`
167			`Q_PC => PC,`
168			`Q_OPC => Q_C_OPC,`
169			`Q_CAT => Q_C_CAT,`
170			`Q_IMM => Q_C_IMM,`
171			`Q_CYC => Q_C_CYC,`
172
173			`INT => INT,`
174			`IO_ADR => IO_ADR,`
175			`IO_RD => IO_RD,`
176			`IO_WR => IO_WR,`
177			`IO_RDAT => IO_RDAT,`
178
179			`XM_ADR => ADR,`
180			`XM_RDAT => XM_RDAT,`
181			`XM_WDAT => IOM_WDAT,`
182			`XM_WE => XM_WE,`
183			`XM_CE => XM_CE,`
184
185			`Q_SX => Q_C_SX,`
186			`Q_SY => Q_C_SY,`
187			`Q_OP => Q_C_OP,`
188			`Q_SA => Q_C_SA,`
189			`Q_SMQ => Q_C_SMQ,`
190
191			`Q_WE_RR => Q_C_WE_RR,`
192			`Q_WE_LL => Q_C_WE_LL,`
193			`Q_WE_SP => Q_C_WE_SP,`
194
195			`Q_RR => Q_C_RR,`
196			`Q_LL => Q_C_LL,`
197			`Q_SP => Q_C_SP,`
198			`HALT => HALT`
199			`);`
200
201			`io: input_output`
202			`PORT MAP( CLK_I => CLK_I,`
203			`T2 => LT2,`
204			`CLR => CLR,`
205
206			`TEMP_SPO => TEMP_SPO,`
207			`TEMP_SPI => TEMP_SPI,`
208			`TEMP_CE => TEMP_CE,`
209			`TEMP_SCLK => TEMP_SCLK,`
210
211			`SER_IN => SER_IN,`
212			`SER_OUT => SER_OUT,`
213
214			`SWITCH => SWITCH,`
215			`LED => LED,`
216
217			`IO_RD => IO_RD,`
218			`IO_WR => IO_WR,`
219			`IO_ADR => IO_ADR,`
220			`IO_RDAT => IO_RDAT,`
221			`IO_WDAT => IOM_WDAT,`
222			`INT => INT,`
223			`HALT => HALT`
224			`);`
225
226			`end behavioral;`