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jsauermann |
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity bin_to_7segment is
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Port( CLK_I : in std_logic;
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PC : in std_logic_vector(15 downto 0);
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SEG1 : out std_logic_vector(7 downto 1);
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SEG2 : out std_logic_vector(7 downto 0));
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end bin_to_7segment;
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architecture Behavioral of bin_to_7segment is
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-- +------- middle upper
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-- |+------- right upper
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-- ||+------ right lower
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-- |||+----- middle lower
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-- ||||+---- left lower
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-- |||||+--- left upper
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-- ||||||+-- middle middle
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-- |||||||
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constant LEDV_0 : std_logic_vector(6 downto 0):= "1111110";-- 0
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constant LEDV_1 : std_logic_vector(6 downto 0):= "0110000";-- 1
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constant LEDV_2 : std_logic_vector(6 downto 0):= "1101101";-- 2
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constant LEDV_3 : std_logic_vector(6 downto 0):= "1111001";-- 3
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constant LEDV_4 : std_logic_vector(6 downto 0):= "0110011";-- 4
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constant LEDV_5 : std_logic_vector(6 downto 0):= "1011011";-- 5
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constant LEDV_6 : std_logic_vector(6 downto 0):= "1011111";-- 6
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constant LEDV_7 : std_logic_vector(6 downto 0):= "1110000";-- 7
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constant LEDV_8 : std_logic_vector(6 downto 0):= "1111111";-- 8
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constant LEDV_9 : std_logic_vector(6 downto 0):= "1111011";-- 9
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constant LEDV_A : std_logic_vector(6 downto 0):= "1110111";-- A
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constant LEDV_b : std_logic_vector(6 downto 0):= "0011111";-- b
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constant LEDV_C : std_logic_vector(6 downto 0):= "1001110";-- C
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constant LEDV_d : std_logic_vector(6 downto 0):= "0111101";-- d
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constant LEDV_E : std_logic_vector(6 downto 0):= "1001111";-- E
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constant LEDV_F : std_logic_vector(6 downto 0):= "1000111";-- F
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9 |
jsauermann |
signal LED_CNT : std_logic_vector(25 downto 0);
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2 |
jsauermann |
signal LED_VAL : std_logic_vector(15 downto 0);
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begin
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process(CLK_I)
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variable LED4H, LED4L : std_logic_vector(3 downto 0);
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begin
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if (rising_edge(CLK_I)) then
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jsauermann |
if (LED_CNT(25) = '0') then
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LED4H := LED_VAL( 7 downto 4);
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LED4L := LED_VAL( 3 downto 0);
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else
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LED4H := LED_VAL(15 downto 12);
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LED4L := LED_VAL(11 downto 8);
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end if;
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2 |
jsauermann |
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jsauermann |
if (LED_CNT = 0) then LED_VAL <= PC; end if;
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LED_CNT <= LED_CNT + 1;
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jsauermann |
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jsauermann |
case LED4H is
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when X"0" => SEG1 <= LEDV_0;
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when X"1" => SEG1 <= LEDV_1;
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when X"2" => SEG1 <= LEDV_2;
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when X"3" => SEG1 <= LEDV_3;
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when X"4" => SEG1 <= LEDV_4;
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when X"5" => SEG1 <= LEDV_5;
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when X"6" => SEG1 <= LEDV_6;
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when X"7" => SEG1 <= LEDV_7;
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when X"8" => SEG1 <= LEDV_8;
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when X"9" => SEG1 <= LEDV_9;
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when X"A" => SEG1 <= LEDV_A;
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when X"B" => SEG1 <= LEDV_b;
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when X"C" => SEG1 <= LEDV_c;
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when X"D" => SEG1 <= LEDV_d;
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when X"E" => SEG1 <= LEDV_E;
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when others => SEG1 <= LEDV_F;
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end case;
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2 |
jsauermann |
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9 |
jsauermann |
case LED4L is
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when X"0" => SEG2(7 downto 1) <= LEDV_0;
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when X"1" => SEG2(7 downto 1) <= LEDV_1;
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when X"2" => SEG2(7 downto 1) <= LEDV_2;
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when X"3" => SEG2(7 downto 1) <= LEDV_3;
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when X"4" => SEG2(7 downto 1) <= LEDV_4;
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when X"5" => SEG2(7 downto 1) <= LEDV_5;
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when X"6" => SEG2(7 downto 1) <= LEDV_6;
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when X"7" => SEG2(7 downto 1) <= LEDV_7;
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when X"8" => SEG2(7 downto 1) <= LEDV_8;
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when X"9" => SEG2(7 downto 1) <= LEDV_9;
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when X"A" => SEG2(7 downto 1) <= LEDV_A;
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when X"B" => SEG2(7 downto 1) <= LEDV_b;
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when X"C" => SEG2(7 downto 1) <= LEDV_c;
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when X"D" => SEG2(7 downto 1) <= LEDV_d;
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when X"E" => SEG2(7 downto 1) <= LEDV_E;
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when others => SEG2(7 downto 1) <= LEDV_F;
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end case;
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2 |
jsauermann |
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jsauermann |
SEG2(0) <= LED_CNT(25);
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2 |
jsauermann |
end if;
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end process;
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end Behavioral;
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