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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
use work.cpu_pack.ALL;
 
library UNISIM;
use UNISIM.VComponents.all;
 
entity cpu is
        PORT(   CLK_I                   : in  STD_LOGIC;
                        SWITCH                  : in  STD_LOGIC_VECTOR (9 downto 0);
 
                        SER_IN                  : in  STD_LOGIC;
                        SER_OUT                 : out STD_LOGIC;
 
                        TEMP_SPO                : in  STD_LOGIC;
                        TEMP_SPI                : out STD_LOGIC;
 
                        TEMP_CE                 : out STD_LOGIC;
                        TEMP_SCLK               : out STD_LOGIC;
                        SEG1                    : out STD_LOGIC_VECTOR (7 downto 0);
                        SEG2                    : out STD_LOGIC_VECTOR (7 downto 0);
                        LED                             : out STD_LOGIC_VECTOR( 7 downto 0);
 
                        XM_ADR                  : out STD_LOGIC_VECTOR(15 downto 0);
                        XM_RDAT                 : in  STD_LOGIC_VECTOR( 7 downto 0);
                        XM_WDAT                 : out STD_LOGIC_VECTOR( 7 downto 0);
                        XM_WE                   : out STD_LOGIC;
                        XM_CE                   : out STD_LOGIC
            );
end cpu;
 
architecture behavioral of cpu is
 
        COMPONENT bin_to_7segment
        PORT(   CLK_I : IN std_logic;
                        PC    : IN std_logic_vector(15 downto 0);
                        SEG1  : OUT std_logic_vector(7 downto 1);
                        SEG2  : OUT std_logic_vector(7 downto 0)
                );
        END COMPONENT;
 
        COMPONENT cpu_engine
        PORT(   CLK_I    : in  std_logic;
                        DAT_I    : in  std_logic_vector( 7 downto 0);
                        DAT_O    : out std_logic_vector( 7 downto 0);
                        RST_I    : in  std_logic;
                        ACK_I    : in  std_logic;
                        ADR_O    : out std_logic_vector(15 downto 0);
                        CYC_O    : out std_logic;
                        STB_O    : out std_logic;
                        TGA_O    : out std_logic_vector(0 downto 0);
                        WE_O     : out std_logic;
 
                        INT      : in  std_logic;
                        HALT     : out std_logic;
 
                        -- debug signals
                        --
                        Q_PC   : out std_logic_vector(15 downto 0);
                        Q_OPC  : out std_logic_vector( 7 downto 0);
                        Q_CAT  : out op_category;
                        Q_IMM  : out std_logic_vector(15 downto 0);
                        Q_CYC  : out cycle;
 
                        -- select signals
                        Q_SX    : out std_logic_vector(1 downto 0);
                        Q_SY    : out std_logic_vector(3 downto 0);
                        Q_OP    : out std_logic_vector(4 downto 0);
                        Q_SA    : out std_logic_vector(4 downto 0);
                        Q_SMQ   : out std_logic;
 
                        -- write enable/select signal
                        Q_WE_RR  : out std_logic;
                        Q_WE_LL  : out std_logic;
                        Q_WE_SP  : out SP_OP;
 
                        Q_RR     : out std_logic_vector(15 downto 0);
                        Q_LL     : out std_logic_vector(15 downto 0);
                        Q_SP     : out std_logic_vector(15 downto 0)
                );
        END COMPONENT;
 
        COMPONENT input_output
        PORT(   CLK_I        : IN std_logic;
                        CYC_I        : IN  std_logic;
                        RST_O        : OUT std_logic;
                        STB_I        : IN  std_logic;
                        ACK_O        : OUT std_logic;
                        IO           : IN  std_logic;
                        WE_I         : IN  std_logic;
                        ADR_I        : IN  std_logic_vector(7 downto 0);
 
                        TEMP_SPO     : IN  std_logic;
                        TEMP_SPI     : OUT std_logic;
                        TEMP_CE      : OUT std_logic;
                        TEMP_SCLK    : OUT std_logic;
 
                        SER_IN       : IN  std_logic;
                        SER_OUT      : OUT std_logic;
 
                        SWITCH       : IN  std_logic_vector(9 downto 0);
                        LED          : OUT std_logic_vector(7 downto 0);
 
                        IO_WDAT      : IN  std_logic_vector(7 downto 0);
                        IO_RDAT      : OUT std_logic_vector(7 downto 0);
                        INT          : OUT std_logic;
                        HALT         : in  std_logic
                );
        END COMPONENT;
 
        signal CLR      : std_logic;
 
        signal ADR      : std_logic_vector(15 downto 0);
        signal CYC      : std_logic;
        signal STB      : std_logic;
        signal XM_STB   : std_logic;
        signal IO_STB   : std_logic;
        signal ACK      : std_logic;
        signal XM_ACK   : std_logic;
        signal IO_ACK   : std_logic;
 
        signal HALT     : std_logic;
        signal INT      : std_logic;
        signal IO       : std_logic;
        signal WE       : std_logic;
        signal IO_RDAT  : std_logic_vector( 7 downto 0);
        signal WDAT     : std_logic_vector( 7 downto 0);
        signal RDAT     : std_logic_vector( 7 downto 0);
 
        signal PC       : std_logic_vector(15 downto 0);
        signal Q_C_SX    : std_logic_vector(1 downto 0);
        signal Q_C_SY    : std_logic_vector(3 downto 0);
        signal Q_C_OP    : std_logic_vector(4 downto 0);
        signal Q_C_SA    : std_logic_vector(4 downto 0);
        signal Q_C_SMQ   : std_logic;
 
        signal Q_C_WE_RR : std_logic;
        signal Q_C_WE_LL : std_logic;
        signal Q_C_WE_SP : SP_OP;
 
        signal Q_C_RR    : std_logic_vector(15 downto 0);
        signal Q_C_LL    : std_logic_vector(15 downto 0);
        signal Q_C_SP    : std_logic_vector(15 downto 0);
 
        signal Q_C_OPC   : std_logic_vector( 7 downto 0);
        signal Q_C_CAT   : op_category;
        signal Q_C_IMM   : std_logic_vector(15 downto 0);
        signal Q_C_CYC   : cycle;
 
begin
 
        SEG1(0) <= HALT;
        XM_ADR  <= ADR;
        XM_WDAT <= WDAT;
        XM_WE   <= WE;
        XM_STB  <= STB and not IO;
        IO_STB  <= STB and IO;
        XM_ACK  <= XM_STB;
        XM_CE   <= CYC and not IO;
        RDAT    <= IO_RDAT when (IO = '1') else XM_RDAT;
        ACK     <= IO_ACK  when (IO = '1') else XM_ACK;
 
        seg7: bin_to_7segment
        PORT MAP(       CLK_I => CLK_I,
                                PC    => PC,
                                SEG1  => SEG1(7 downto 1),              -- SEG1(0) is HALT
                                SEG2  => SEG2
                        );
 
        eng: cpu_engine
        PORT MAP(       CLK_I     => CLK_I,
                                DAT_I     => RDAT,
                                DAT_O     => WDAT,
                                RST_I     => CLR,       -- SW-1 (RESET)
                                ACK_I     => ACK,
                                CYC_O     => CYC,
                                STB_O     => STB,
                                ADR_O     => ADR,
                                TGA_O(0)  => IO,
                                WE_O      => WE,
 
                                INT       => INT,
                                HALT      => HALT,
 
                                Q_PC      => PC,
                                Q_OPC     => Q_C_OPC,
                                Q_CAT     => Q_C_CAT,
                                Q_IMM     => Q_C_IMM,
                                Q_CYC     => Q_C_CYC,
 
                                Q_SX      => Q_C_SX,
                                Q_SY      => Q_C_SY,
                                Q_OP      => Q_C_OP,
                                Q_SA      => Q_C_SA,
                                Q_SMQ     => Q_C_SMQ,
 
                                Q_WE_RR   => Q_C_WE_RR,
                                Q_WE_LL   => Q_C_WE_LL,
                                Q_WE_SP   => Q_C_WE_SP,
 
                                Q_RR      => Q_C_RR,
                                Q_LL      => Q_C_LL,
                                Q_SP      => Q_C_SP
                        );
 
        ino: input_output
        PORT MAP(       CLK_I        => CLK_I,
                                CYC_I        => CYC,
                                RST_O        => CLR,
                                STB_I        => IO_STB,
                                ACK_O        => IO_ACK,
 
                                TEMP_SPO     => TEMP_SPO,
                                TEMP_SPI     => TEMP_SPI,
                                TEMP_CE      => TEMP_CE,
                                TEMP_SCLK    => TEMP_SCLK,
 
                                SER_IN       => SER_IN,
                                SER_OUT      => SER_OUT,
 
                                SWITCH       => SWITCH,
                                LED          => LED,
 
                                IO           => IO,
                                WE_I         => WE,
                                ADR_I        => ADR(7 downto 0),
                                IO_RDAT      => IO_RDAT,
                                IO_WDAT      => WDAT,
                                INT          => INT,
                                HALT         => HALT
                        );
 
end behavioral;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3			`use IEEE.std_logic_unsigned.all;`
4
5			`use work.cpu_pack.ALL;`
6
7			`library UNISIM;`
8			`use UNISIM.VComponents.all;`
9
10	9	jsauermann	`entity cpu is`
11	2	jsauermann	`PORT( CLK_I : in STD_LOGIC;`
12			`SWITCH : in STD_LOGIC_VECTOR (9 downto 0);`
13
14			`SER_IN : in STD_LOGIC;`
15			`SER_OUT : out STD_LOGIC;`
16
17			`TEMP_SPO : in STD_LOGIC;`
18			`TEMP_SPI : out STD_LOGIC;`
19
20			`TEMP_CE : out STD_LOGIC;`
21			`TEMP_SCLK : out STD_LOGIC;`
22			`SEG1 : out STD_LOGIC_VECTOR (7 downto 0);`
23			`SEG2 : out STD_LOGIC_VECTOR (7 downto 0);`
24			`LED : out STD_LOGIC_VECTOR( 7 downto 0);`
25
26			`XM_ADR : out STD_LOGIC_VECTOR(15 downto 0);`
27			`XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);`
28			`XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);`
29			`XM_WE : out STD_LOGIC;`
30			`XM_CE : out STD_LOGIC`
31			`);`
32	9	jsauermann	`end cpu;`
33	2	jsauermann
34	9	jsauermann	`architecture behavioral of cpu is`
35	2	jsauermann
36			`COMPONENT bin_to_7segment`
37			`PORT( CLK_I : IN std_logic;`
38			`PC : IN std_logic_vector(15 downto 0);`
39			`SEG1 : OUT std_logic_vector(7 downto 1);`
40			`SEG2 : OUT std_logic_vector(7 downto 0)`
41			`);`
42			`END COMPONENT;`
43
44			`COMPONENT cpu_engine`
45			`PORT( CLK_I : in std_logic;`
46	9	jsauermann	`DAT_I : in std_logic_vector( 7 downto 0);`
47			`DAT_O : out std_logic_vector( 7 downto 0);`
48			`RST_I : in std_logic;`
49			`ACK_I : in std_logic;`
50			`ADR_O : out std_logic_vector(15 downto 0);`
51			`CYC_O : out std_logic;`
52			`STB_O : out std_logic;`
53			`TGA_O : out std_logic_vector(0 downto 0);`
54			`WE_O : out std_logic;`
55
56			`INT : in std_logic;`
57			`HALT : out std_logic;`
58
59			`-- debug signals`
60			`--`
61	2	jsauermann	`Q_PC : out std_logic_vector(15 downto 0);`
62			`Q_OPC : out std_logic_vector( 7 downto 0);`
63			`Q_CAT : out op_category;`
64			`Q_IMM : out std_logic_vector(15 downto 0);`
65			`Q_CYC : out cycle;`
66
67			`-- select signals`
68			`Q_SX : out std_logic_vector(1 downto 0);`
69			`Q_SY : out std_logic_vector(3 downto 0);`
70			`Q_OP : out std_logic_vector(4 downto 0);`
71			`Q_SA : out std_logic_vector(4 downto 0);`
72			`Q_SMQ : out std_logic;`
73
74			`-- write enable/select signal`
75			`Q_WE_RR : out std_logic;`
76			`Q_WE_LL : out std_logic;`
77			`Q_WE_SP : out SP_OP;`
78
79			`Q_RR : out std_logic_vector(15 downto 0);`
80			`Q_LL : out std_logic_vector(15 downto 0);`
81	9	jsauermann	`Q_SP : out std_logic_vector(15 downto 0)`
82	2	jsauermann	`);`
83			`END COMPONENT;`
84
85			`COMPONENT input_output`
86			`PORT( CLK_I : IN std_logic;`
87	9	jsauermann	`CYC_I : IN std_logic;`
88			`RST_O : OUT std_logic;`
89			`STB_I : IN std_logic;`
90			`ACK_O : OUT std_logic;`
91			`IO : IN std_logic;`
92			`WE_I : IN std_logic;`
93			`ADR_I : IN std_logic_vector(7 downto 0);`
94	2	jsauermann
95			`TEMP_SPO : IN std_logic;`
96			`TEMP_SPI : OUT std_logic;`
97			`TEMP_CE : OUT std_logic;`
98			`TEMP_SCLK : OUT std_logic;`
99
100			`SER_IN : IN std_logic;`
101			`SER_OUT : OUT std_logic;`
102
103			`SWITCH : IN std_logic_vector(9 downto 0);`
104			`LED : OUT std_logic_vector(7 downto 0);`
105
106			`IO_WDAT : IN std_logic_vector(7 downto 0);`
107			`IO_RDAT : OUT std_logic_vector(7 downto 0);`
108			`INT : OUT std_logic;`
109			`HALT : in std_logic`
110			`);`
111			`END COMPONENT;`
112
113			`signal CLR : std_logic;`
114
115			`signal ADR : std_logic_vector(15 downto 0);`
116	9	jsauermann	`signal CYC : std_logic;`
117			`signal STB : std_logic;`
118			`signal XM_STB : std_logic;`
119			`signal IO_STB : std_logic;`
120			`signal ACK : std_logic;`
121			`signal XM_ACK : std_logic;`
122			`signal IO_ACK : std_logic;`
123	2	jsauermann
124			`signal HALT : std_logic;`
125			`signal INT : std_logic;`
126	9	jsauermann	`signal IO : std_logic;`
127			`signal WE : std_logic;`
128	2	jsauermann	`signal IO_RDAT : std_logic_vector( 7 downto 0);`
129	9	jsauermann	`signal WDAT : std_logic_vector( 7 downto 0);`
130			`signal RDAT : std_logic_vector( 7 downto 0);`
131
132	2	jsauermann	`signal PC : std_logic_vector(15 downto 0);`
133			`signal Q_C_SX : std_logic_vector(1 downto 0);`
134			`signal Q_C_SY : std_logic_vector(3 downto 0);`
135			`signal Q_C_OP : std_logic_vector(4 downto 0);`
136			`signal Q_C_SA : std_logic_vector(4 downto 0);`
137			`signal Q_C_SMQ : std_logic;`
138
139			`signal Q_C_WE_RR : std_logic;`
140			`signal Q_C_WE_LL : std_logic;`
141			`signal Q_C_WE_SP : SP_OP;`
142
143			`signal Q_C_RR : std_logic_vector(15 downto 0);`
144			`signal Q_C_LL : std_logic_vector(15 downto 0);`
145			`signal Q_C_SP : std_logic_vector(15 downto 0);`
146
147			`signal Q_C_OPC : std_logic_vector( 7 downto 0);`
148			`signal Q_C_CAT : op_category;`
149			`signal Q_C_IMM : std_logic_vector(15 downto 0);`
150			`signal Q_C_CYC : cycle;`
151
152			`begin`
153
154			`SEG1(0) <= HALT;`
155			`XM_ADR <= ADR;`
156	9	jsauermann	`XM_WDAT <= WDAT;`
157			`XM_WE <= WE;`
158			`XM_STB <= STB and not IO;`
159			`IO_STB <= STB and IO;`
160			`XM_ACK <= XM_STB;`
161			`XM_CE <= CYC and not IO;`
162			`RDAT <= IO_RDAT when (IO = '1') else XM_RDAT;`
163			`ACK <= IO_ACK when (IO = '1') else XM_ACK;`
164	2	jsauermann
165			`seg7: bin_to_7segment`
166			`PORT MAP( CLK_I => CLK_I,`
167			`PC => PC,`
168	9	jsauermann	`SEG1 => SEG1(7 downto 1), -- SEG1(0) is HALT`
169	2	jsauermann	`SEG2 => SEG2`
170			`);`
171
172			`eng: cpu_engine`
173			`PORT MAP( CLK_I => CLK_I,`
174	9	jsauermann	`DAT_I => RDAT,`
175			`DAT_O => WDAT,`
176			`RST_I => CLR, -- SW-1 (RESET)`
177			`ACK_I => ACK,`
178			`CYC_O => CYC,`
179			`STB_O => STB,`
180			`ADR_O => ADR,`
181			`TGA_O(0) => IO,`
182			`WE_O => WE,`
183
184			`INT => INT,`
185			`HALT => HALT,`
186
187	2	jsauermann	`Q_PC => PC,`
188			`Q_OPC => Q_C_OPC,`
189			`Q_CAT => Q_C_CAT,`
190			`Q_IMM => Q_C_IMM,`
191			`Q_CYC => Q_C_CYC,`
192
193			`Q_SX => Q_C_SX,`
194			`Q_SY => Q_C_SY,`
195			`Q_OP => Q_C_OP,`
196			`Q_SA => Q_C_SA,`
197			`Q_SMQ => Q_C_SMQ,`
198
199			`Q_WE_RR => Q_C_WE_RR,`
200			`Q_WE_LL => Q_C_WE_LL,`
201			`Q_WE_SP => Q_C_WE_SP,`
202
203			`Q_RR => Q_C_RR,`
204			`Q_LL => Q_C_LL,`
205	9	jsauermann	`Q_SP => Q_C_SP`
206	2	jsauermann	`);`
207
208	9	jsauermann	`ino: input_output`
209	2	jsauermann	`PORT MAP( CLK_I => CLK_I,`
210	9	jsauermann	`CYC_I => CYC,`
211			`RST_O => CLR,`
212			`STB_I => IO_STB,`
213			`ACK_O => IO_ACK,`
214	2	jsauermann
215			`TEMP_SPO => TEMP_SPO,`
216			`TEMP_SPI => TEMP_SPI,`
217			`TEMP_CE => TEMP_CE,`
218			`TEMP_SCLK => TEMP_SCLK,`
219
220			`SER_IN => SER_IN,`
221			`SER_OUT => SER_OUT,`
222
223			`SWITCH => SWITCH,`
224			`LED => LED,`
225
226	9	jsauermann	`IO => IO,`
227			`WE_I => WE,`
228			`ADR_I => ADR(7 downto 0),`
229	2	jsauermann	`IO_RDAT => IO_RDAT,`
230	9	jsauermann	`IO_WDAT => WDAT,`
231	2	jsauermann	`INT => INT,`
232			`HALT => HALT`
233			`);`
234
235			`end behavioral;`

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[/] [c16/] [trunk/] [vhdl/] [cpu.vhd] - Blame information for rev 31