Subversion Repositories c16

JDF F

// Created by Project Navigator ver 1.0

PROJECT cpu16

DESIGN cpu16 Normal

DEVFAM virtexe

DEVFAMTIME 1064066933

DEVICE xcv100e

DEVICETIME 1064066933

DEVPKG pq240

DEVPKGTIME 1064066933

DEVSPEED -6

DEVSPEEDTIME 1064065691

FLOW XST VHDL

FLOWTIME 0

STIMULUS test.vhd Normal

STIMULUS cpu_test.vhd Normal

MODULE memory.vhd

MODSTYLE memory Normal

MODULE uart_rx.vhd

MODSTYLE uart_rx Normal

MODULE uart_tx.vhd

MODSTYLE uart_tx Normal

MODULE alu8.vhd

MODSTYLE alu8 Normal

MODULE cpu.vhd

MODSTYLE cpu16 Normal

MODULE temperature.vhd

MODSTYLE temperature Normal

MODULE cpu_engine.vhd

MODSTYLE cpu_engine Normal

MODULE data_core.vhd

MODSTYLE data_core Normal

MODULE uart.vhd

MODSTYLE uart Normal

MODULE uart._baudgen.vhd

MODSTYLE uart_baudgen Normal

MODULE opcode_decoder.vhd

MODSTYLE opcode_decoder Normal

MODULE opcode_fetch.vhd

MODSTYLE opcode_fetch Normal

MODULE select_yy.vhd

MODSTYLE select_yy Normal

MODULE Board_cpu.vhd

MODSTYLE board_cpu Normal

MODULE BaudGen.vhd

MODSTYLE baudgen Normal

MODULE input_output.vhd

MODSTYLE input_output Normal

MODULE ds1722.vhd

MODSTYLE ds1722 Normal

MODULE bin_to_7segment.vhd

MODSTYLE bin_to_7segment Normal

LIBFILE mem_content.vhd work ***

LIBFILE cpu_pack.vhd work ***

DEPASSOC board_cpu board_cpu.ucf SYSTEM

[Normal]

p_ModelSimSignalWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False

p_ModelSimStructWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False

_SynthExtractROM=xstvhd, virtexe, Schematic.t_synthesize, 1064066560, False

[STRATEGY-LIST]

Normal=True