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[/] [c16/] [trunk/] [vhdl/] [cpu_engine.vhd] - Blame information for rev 2

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity cpu_engine is
        PORT(   CLK_I    : in  std_logic;
                        T2       : out std_logic;
                        CLR      : in  std_logic;
                        Q_PC   : out std_logic_vector(15 downto 0);
                        Q_OPC  : out std_logic_vector( 7 downto 0);
                        Q_CAT  : out op_category;
                        Q_IMM  : out std_logic_vector(15 downto 0);
                        Q_CYC  : out cycle;
 
                        -- input/output
                        INT      : in  std_logic;
                        IO_ADR   : out std_logic_vector(7 downto 0);
                        IO_RD    : out std_logic;
                        IO_WR    : out std_logic;
                        IO_RDAT  : in  std_logic_vector( 7 downto 0);
 
                        -- external memory
                        XM_ADR  : out std_logic_vector(15 downto 0);
                        XM_RDAT : in  std_logic_vector( 7 downto 0);
                        XM_WDAT : out std_logic_vector( 7 downto 0);
                        XM_WE   : out std_logic;
                        XM_CE   : out std_logic;
 
                        -- select signals
                        Q_SX    : out std_logic_vector(1 downto 0);
                        Q_SY    : out std_logic_vector(3 downto 0);
                        Q_OP    : out std_logic_vector(4 downto 0);
                        Q_SA    : out std_logic_vector(4 downto 0);
                        Q_SMQ   : out std_logic;
 
                        -- write enable/select signal
                        Q_WE_RR  : out std_logic;
                        Q_WE_LL  : out std_logic;
                        Q_WE_SP  : out SP_OP;
 
                        Q_RR     : out std_logic_vector(15 downto 0);
                        Q_LL     : out std_logic_vector(15 downto 0);
                        Q_SP     : out std_logic_vector(15 downto 0);
                        HALT       : out std_logic
                );
end cpu_engine;
 
architecture Behavioral of cpu_engine is
 
        COMPONENT memory
        PORT(   CLK_I : IN  std_logic;
                        T2    : IN  std_logic;
                        CE    : IN  std_logic;
                        PC    : IN  std_logic_vector(15 downto 0);
                        ADR   : IN  std_logic_vector(15 downto 0);
                        WR    : IN  std_logic;
                        WDAT  : IN  std_logic_vector(7 downto 0);
 
                        OPC   : OUT std_logic_vector(7 downto 0);
                        RDAT  : OUT std_logic_vector(7 downto 0)
                );
        END COMPONENT;
 
        COMPONENT opcode_fetch
        PORT(   CLK_I  : IN  std_logic;
                        T2     : IN  std_logic;
                        CLR    : IN  std_logic;
                        CE     : IN  std_logic;
                        PC_OP  : IN  std_logic_vector(2 downto 0);
                        JDATA  : IN  std_logic_vector(15 downto 0);
                        RR     : IN  std_logic_vector(15 downto 0);
                        RDATA  : IN  std_logic_vector(7 downto 0);
                        PC     : OUT std_logic_vector(15 downto 0)
                );
        END COMPONENT;
 
        COMPONENT opcode_decoder
        PORT(   CLK_I  : IN  std_logic;
                        T2     : IN  std_logic;
                        CLR    : IN  std_logic;
                        CE     : IN  std_logic;
                        OPCODE : in std_logic_vector(7 downto 0);
                        OP_CYC : in cycle;
                        INT    : in std_logic;
                        RRZ    : in std_logic;
 
                        OP_CAT : out op_category;
 
                        -- select signals
                        D_SX    : out std_logic_vector(1 downto 0);              -- ALU select X
                        D_SY    : out std_logic_vector(3 downto 0);              -- ALU select Y
                        D_OP    : out std_logic_vector(4 downto 0);              -- ALU operation
                        D_SA    : out std_logic_vector(4 downto 0);              -- select address
                        D_SMQ   : out std_logic;
 
                        -- write enable/select signal
                        D_WE_RR  : out std_logic;
                        D_WE_LL  : out std_logic;
                        D_WE_M   : out std_logic;
                        D_WE_SP  : out SP_OP;
 
                        -- input/output
                        IO_RD    : out std_logic;
                        IO_WR    : out std_logic;
 
                        PC_OP  : out std_logic_vector(2 downto 0);
 
                        LAST_M : out std_logic;
                        HLT    : out std_logic
                );
        END COMPONENT;
 
        COMPONENT data_core
        PORT(   CLK_I : in  std_logic;
                        T2    : in  std_logic;
                        CLR   : in  std_logic;
                        CE    : in  std_logic;
 
                        -- select signals
                        SX    : in  std_logic_vector( 1 downto 0);
                        SY    : in  std_logic_vector( 3 downto 0);
                        OP    : in  std_logic_vector( 4 downto 0);               -- alu op
                        PC    : in  std_logic_vector(15 downto 0);               -- PC
                        QU    : in  std_logic_vector( 3 downto 0);               -- quick operand
                        SA    : in  std_logic_vector(4 downto 0);                        -- select address
                        SMQ   : in  std_logic;                                                  -- select MQ (H/L)
 
                        -- write enable/select signal
                        WE_RR  : in  std_logic;
                        WE_LL  : in  std_logic;
                        WE_SP  : in  SP_OP;
 
                        -- data in signals
                        IMM : in  std_logic_vector(15 downto 0);         -- immediate data
                        M_RDAT : in  std_logic_vector( 7 downto 0);              -- memory data
 
                        -- memory control signals
                        ADR   : out std_logic_vector(15 downto 0);
                        MQ    : out std_logic_vector( 7 downto 0);
 
                        -- input/output
                        IO_RDAT  : in  std_logic_vector( 7 downto 0);
 
                        Q_RR  : out std_logic_vector(15 downto 0);
                        Q_LL  : out std_logic_vector(15 downto 0);
                        Q_SP  : out std_logic_vector(15 downto 0)
                );
        END COMPONENT;
 
        -- global signals
        signal CE      : std_logic;
        signal LT2     : std_logic;
 
        -- memory signals
        signal  MEM_WDAT : std_logic_vector(7 downto 0);
        signal  MEM_RDAT : std_logic_vector(7 downto 0);
        signal  M_PC     : std_logic_vector(15 downto 0);
        signal  M_OPC    : std_logic_vector(7 downto 0);
 
        -- decoder signals
        --
        signal  D_CAT    : op_category;
        signal  D_OPC    : std_logic_vector(7 downto 0);
        signal  D_CYC    : cycle;
        signal  D_PC     : std_logic_vector(15 downto 0);        -- debug signal
        signal  D_PC_OP  : std_logic_vector( 2 downto 0);
        signal  D_LAST_M : std_logic;
        signal  D_IO_RD  : std_logic;
        signal  D_IO_WR  : std_logic;
        -- select signals
        signal  D_SX    : std_logic_vector(1 downto 0);
        signal  D_SY    : std_logic_vector(3 downto 0);
        signal  D_OP    : std_logic_vector(4 downto 0);
        signal  D_SA    : std_logic_vector(4 downto 0);
        signal  D_SMQ   : std_logic;
        -- write enable/select signals
        signal  D_WE_RR  : std_logic;
        signal  D_WE_LL  : std_logic;
        signal  D_WE_SP  : SP_OP;
        signal  D_MEM_WE : std_logic;
        signal  MEM_WE   : std_logic;
 
        -- core signals
        --
        signal  C_IMM  : std_logic_vector(15 downto 0);
        signal  ADR    : std_logic_vector(15 downto 0);
 
        signal  C_CYC    : cycle;                                                               -- debug signal
        signal  C_PC     : std_logic_vector(15 downto 0);                -- debug signal
        signal  C_OPC    : std_logic_vector( 7 downto 0);                -- debug signal
        signal  C_RR     : std_logic_vector(15 downto 0);
 
        signal  RRZ      : std_logic;
        signal  OC_JD    : std_logic_vector(15 downto 0);
        signal  C_MQ     : std_logic_vector(7 downto 0);
 
        -- select signals
        signal  C_SX     : std_logic_vector(1 downto 0);
        signal  C_SY     : std_logic_vector(3 downto 0);
        signal  C_OP     : std_logic_vector(4 downto 0);
        signal  C_SA     : std_logic_vector(4 downto 0);
        signal  C_SMQ    : std_logic;
        signal  C_WE_RR  : std_logic;
        signal  C_WE_LL  : std_logic;
        signal  C_WE_SP  : SP_OP;
 
        signal XM_OPC    : std_logic_vector(7 downto 0);
        signal LM_OPC    : std_logic_vector(7 downto 0);
        signal LM_RDAT   : std_logic_vector(7 downto 0);
        signal LXM_RDAT   : std_logic_vector(7 downto 0);
        signal OPCS      : std_logic;
        signal RDATS     : std_logic;
 
begin
 
        memo: memory
        PORT MAP(       CLK_I => CLK_I,
                                T2    => LT2,
                                CE    => CE,
 
                                -- read in T1
                                PC    => M_PC,
                                OPC   => LM_OPC,
 
                                -- read or written in T2
                                ADR   => ADR,
                                WR    => MEM_WE,
                                WDAT  => MEM_WDAT,
                                RDAT  => LM_RDAT
                        );
 
        ocf: opcode_fetch
         PORT MAP(      CLK_I    => CLK_I,
                                T2       => LT2,
                                CLR      => CLR,
                                CE       => CE,
                                PC_OP    => D_PC_OP,
                                JDATA    => OC_JD,
                                RR       => C_RR,
                                RDATA    => MEM_RDAT,
                                PC       => M_PC
                        );
 
        opdec: opcode_decoder
        PORT MAP(       CLK_I    => CLK_I,
                                T2       => LT2,
                                CLR      => CLR,
                                CE       => CE,
                                OPCODE  => D_OPC,
                                OP_CYC  => D_CYC,
                                INT     => INT,
                                RRZ     => RRZ,
 
                                OP_CAT  => D_CAT,
                                -- select signals
                                D_SX    => D_SX,
                                D_SY    => D_SY,
                                D_OP    => D_OP,
                                D_SA    => D_SA,
                                D_SMQ   => D_SMQ,
 
                                -- write enable/select signal
                                D_WE_RR => D_WE_RR,
                                D_WE_LL => D_WE_LL,
                                D_WE_M  => D_MEM_WE,
                                D_WE_SP => D_WE_SP,
 
                                IO_RD   => D_IO_RD,
                                IO_WR   => D_IO_WR,
 
                                PC_OP   => D_PC_OP,
                                LAST_M  => D_LAST_M,
                                HLT     => HALT
        );
 
        dcore: data_core
        PORT MAP(       CLK_I  => CLK_I,
                                T2     => LT2,
                                CLR    => CLR,
                                CE     => CE,
 
                                -- select signals
                                SX     => C_SX,
                                SY     => C_SY,
                                OP     => C_OP,
                                PC     => C_PC,
                                QU     => C_OPC(3 downto 0),
                                SA     => C_SA,
                                SMQ    => C_SMQ,
 
                                -- write enable/select signal
                                WE_RR  => C_WE_RR,
                                WE_LL  => C_WE_LL,
                                WE_SP  => C_WE_SP,
 
                                IMM    => C_IMM,
                                M_RDAT   => MEM_RDAT,
                                ADR    => ADR,
                                MQ     => MEM_WDAT,
 
                                IO_RDAT => IO_RDAT,
 
                                Q_RR   => C_RR,
                                Q_LL   => Q_LL,
                                Q_SP   => Q_SP
        );
 
        CE     <= '1';
        T2     <= LT2;
 
        IO_ADR <= ADR(7 downto 0);
        Q_RR   <= C_RR;
        RRZ    <= '1' when (C_RR = X"0000") else '0';
        OC_JD  <= M_OPC & C_IMM(7 downto 0);
 
        Q_PC   <= C_PC;
        Q_OPC  <= C_OPC;
        Q_CYC  <= C_CYC;
        Q_IMM  <= C_IMM;
 
        -- select signals
        Q_SX    <= C_SX;
        Q_SY    <= C_SY;
        Q_OP    <= C_OP;
        Q_SA    <= C_SA;
        Q_SMQ   <= C_SMQ;
 
        -- write enable/select signal
        Q_WE_RR <= C_WE_RR;
        Q_WE_LL <= C_WE_LL;
        Q_WE_SP <= C_WE_SP;
 
        XM_WDAT  <= MEM_WDAT;
 
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        LT2 <= not LT2;
                end if;
        end process;
 
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (LT2 = '1') then
                                RDATS    <= ADR(15) or ADR(14) or ADR(13);
                                LXM_RDAT <= XM_RDAT;
                        end if;
                end if;
        end process;
 
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (LT2 = '0') then
                                OPCS   <= M_PC(15) or M_PC(14) or M_PC(13);
                                XM_OPC <= XM_RDAT;
                        end if;
                end if;
        end process;
 
        process(OPCS, LM_OPC, XM_OPC)
        begin
                if (OPCS = '0') then     M_OPC <= LM_OPC;
                else                                    M_OPC <= XM_OPC;
                end if;
        end process;
 
        process(RDATS, LXM_RDAT, LM_RDAT)
        begin
                if (RDATS = '0') then    MEM_RDAT <= LM_RDAT;
                else                                    MEM_RDAT <= LXM_RDAT;
                end if;
        end process;
 
        process(LT2, M_PC, ADR, MEM_WE)
        begin
                if (LT2 = '0') then              -- opcode fetch
                        XM_ADR   <= M_PC;
                        XM_WE    <= '0';
                        XM_CE    <= M_PC(15) or M_PC(14) or M_PC(13);
                else                                    -- data
                        XM_ADR   <= ADR;
                        XM_WE    <= MEM_WE;
                        XM_CE    <= ADR(15) or ADR(14) or ADR(13);
                end if;
        end process;
 
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (LT2 = '1') then
                                if (CLR = '1') then
                                        D_PC  <= X"0000";
                                        D_OPC  <= X"01";
                                        D_CYC  <= M1;
 
                                        C_PC  <= X"0000";
                                        C_OPC <= X"01";
                                        C_CYC <= M1;
                                        C_IMM <= X"FFFF";
 
                                        C_SX    <= "00";
                                        C_SY    <= "0000";
                                        C_OP    <= "00000";
                                        C_SA    <= "00000";
                                        C_SMQ   <= '0';
                                        C_WE_RR <= '0';
                                        C_WE_LL <= '0';
                                        C_WE_SP <= SP_NOP;
                                        MEM_WE  <= '0';
 
                                elsif (CE = '1') then
                                        C_CYC    <= D_CYC;
                                        Q_CAT    <= D_CAT;
                                        C_PC     <= D_PC;
                                        C_OPC    <= D_OPC;
                                        C_SX     <= D_SX;
                                        C_SY     <= D_SY;
                                        C_OP     <= D_OP;
                                        C_SA     <= D_SA;
                                        C_SMQ    <= D_SMQ;
                                        C_WE_RR  <= D_WE_RR;
                                        C_WE_LL  <= D_WE_LL;
                                        C_WE_SP  <= D_WE_SP;
                                        IO_RD    <= D_IO_RD;
                                        IO_WR    <= D_IO_WR;
                                        MEM_WE   <= D_MEM_WE;
 
                                        if (D_LAST_M = '1') then        -- D goes to M1
                                                -- signals valid for entire opcode...
                                                D_OPC <= M_OPC;
                                                D_PC  <= M_PC;
                                                D_CYC <= M1;
                                        else
                                                case D_CYC is
                                                        when M1 =>      D_CYC <= M2;    -- C goes to M1
                                                                                C_IMM <= X"00" & M_OPC;
                                                        when M2 =>      D_CYC <= M3;
                                                                                C_IMM(15 downto 8) <= M_OPC;
                                                        when M3 =>      D_CYC <= M4;
                                                        when M4 =>      D_CYC <= M5;
                                                        when M5 =>      D_CYC <= M1;
                                                end case;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
end Behavioral;

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[/] [c16/] [trunk/] [vhdl/] [cpu_engine.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`-- Uncomment the following lines to use the declarations that are`
7			`-- provided for instantiating Xilinx primitive components.`
8			`--library UNISIM;`
9			`--use UNISIM.VComponents.all;`
10
11			`use work.cpu_pack.ALL;`
12
13			`entity cpu_engine is`
14			`PORT( CLK_I : in std_logic;`
15			`T2 : out std_logic;`
16			`CLR : in std_logic;`
17			`Q_PC : out std_logic_vector(15 downto 0);`
18			`Q_OPC : out std_logic_vector( 7 downto 0);`
19			`Q_CAT : out op_category;`
20			`Q_IMM : out std_logic_vector(15 downto 0);`
21			`Q_CYC : out cycle;`
22
23			`-- input/output`
24			`INT : in std_logic;`
25			`IO_ADR : out std_logic_vector(7 downto 0);`
26			`IO_RD : out std_logic;`
27			`IO_WR : out std_logic;`
28			`IO_RDAT : in std_logic_vector( 7 downto 0);`
29
30			`-- external memory`
31			`XM_ADR : out std_logic_vector(15 downto 0);`
32			`XM_RDAT : in std_logic_vector( 7 downto 0);`
33			`XM_WDAT : out std_logic_vector( 7 downto 0);`
34			`XM_WE : out std_logic;`
35			`XM_CE : out std_logic;`
36
37			`-- select signals`
38			`Q_SX : out std_logic_vector(1 downto 0);`
39			`Q_SY : out std_logic_vector(3 downto 0);`
40			`Q_OP : out std_logic_vector(4 downto 0);`
41			`Q_SA : out std_logic_vector(4 downto 0);`
42			`Q_SMQ : out std_logic;`
43
44			`-- write enable/select signal`
45			`Q_WE_RR : out std_logic;`
46			`Q_WE_LL : out std_logic;`
47			`Q_WE_SP : out SP_OP;`
48
49			`Q_RR : out std_logic_vector(15 downto 0);`
50			`Q_LL : out std_logic_vector(15 downto 0);`
51			`Q_SP : out std_logic_vector(15 downto 0);`
52			`HALT : out std_logic`
53			`);`
54			`end cpu_engine;`
55
56			`architecture Behavioral of cpu_engine is`
57
58			`COMPONENT memory`
59			`PORT( CLK_I : IN std_logic;`
60			`T2 : IN std_logic;`
61			`CE : IN std_logic;`
62			`PC : IN std_logic_vector(15 downto 0);`
63			`ADR : IN std_logic_vector(15 downto 0);`
64			`WR : IN std_logic;`
65			`WDAT : IN std_logic_vector(7 downto 0);`
66
67			`OPC : OUT std_logic_vector(7 downto 0);`
68			`RDAT : OUT std_logic_vector(7 downto 0)`
69			`);`
70			`END COMPONENT;`
71
72			`COMPONENT opcode_fetch`
73			`PORT( CLK_I : IN std_logic;`
74			`T2 : IN std_logic;`
75			`CLR : IN std_logic;`
76			`CE : IN std_logic;`
77			`PC_OP : IN std_logic_vector(2 downto 0);`
78			`JDATA : IN std_logic_vector(15 downto 0);`
79			`RR : IN std_logic_vector(15 downto 0);`
80			`RDATA : IN std_logic_vector(7 downto 0);`
81			`PC : OUT std_logic_vector(15 downto 0)`
82			`);`
83			`END COMPONENT;`
84
85			`COMPONENT opcode_decoder`
86			`PORT( CLK_I : IN std_logic;`
87			`T2 : IN std_logic;`
88			`CLR : IN std_logic;`
89			`CE : IN std_logic;`
90			`OPCODE : in std_logic_vector(7 downto 0);`
91			`OP_CYC : in cycle;`
92			`INT : in std_logic;`
93			`RRZ : in std_logic;`
94
95			`OP_CAT : out op_category;`
96
97			`-- select signals`
98			`D_SX : out std_logic_vector(1 downto 0); -- ALU select X`
99			`D_SY : out std_logic_vector(3 downto 0); -- ALU select Y`
100			`D_OP : out std_logic_vector(4 downto 0); -- ALU operation`
101			`D_SA : out std_logic_vector(4 downto 0); -- select address`
102			`D_SMQ : out std_logic;`
103
104			`-- write enable/select signal`
105			`D_WE_RR : out std_logic;`
106			`D_WE_LL : out std_logic;`
107			`D_WE_M : out std_logic;`
108			`D_WE_SP : out SP_OP;`
109
110			`-- input/output`
111			`IO_RD : out std_logic;`
112			`IO_WR : out std_logic;`
113
114			`PC_OP : out std_logic_vector(2 downto 0);`
115
116			`LAST_M : out std_logic;`
117			`HLT : out std_logic`
118			`);`
119			`END COMPONENT;`
120
121			`COMPONENT data_core`
122			`PORT( CLK_I : in std_logic;`
123			`T2 : in std_logic;`
124			`CLR : in std_logic;`
125			`CE : in std_logic;`
126
127			`-- select signals`
128			`SX : in std_logic_vector( 1 downto 0);`
129			`SY : in std_logic_vector( 3 downto 0);`
130			`OP : in std_logic_vector( 4 downto 0); -- alu op`
131			`PC : in std_logic_vector(15 downto 0); -- PC`
132			`QU : in std_logic_vector( 3 downto 0); -- quick operand`
133			`SA : in std_logic_vector(4 downto 0); -- select address`
134			`SMQ : in std_logic; -- select MQ (H/L)`
135
136			`-- write enable/select signal`
137			`WE_RR : in std_logic;`
138			`WE_LL : in std_logic;`
139			`WE_SP : in SP_OP;`
140
141			`-- data in signals`
142			`IMM : in std_logic_vector(15 downto 0); -- immediate data`
143			`M_RDAT : in std_logic_vector( 7 downto 0); -- memory data`
144
145			`-- memory control signals`
146			`ADR : out std_logic_vector(15 downto 0);`
147			`MQ : out std_logic_vector( 7 downto 0);`
148
149			`-- input/output`
150			`IO_RDAT : in std_logic_vector( 7 downto 0);`
151
152			`Q_RR : out std_logic_vector(15 downto 0);`
153			`Q_LL : out std_logic_vector(15 downto 0);`
154			`Q_SP : out std_logic_vector(15 downto 0)`
155			`);`
156			`END COMPONENT;`
157
158			`-- global signals`
159			`signal CE : std_logic;`
160			`signal LT2 : std_logic;`
161
162			`-- memory signals`
163			`signal MEM_WDAT : std_logic_vector(7 downto 0);`
164			`signal MEM_RDAT : std_logic_vector(7 downto 0);`
165			`signal M_PC : std_logic_vector(15 downto 0);`
166			`signal M_OPC : std_logic_vector(7 downto 0);`
167
168			`-- decoder signals`
169			`--`
170			`signal D_CAT : op_category;`
171			`signal D_OPC : std_logic_vector(7 downto 0);`
172			`signal D_CYC : cycle;`
173			`signal D_PC : std_logic_vector(15 downto 0); -- debug signal`
174			`signal D_PC_OP : std_logic_vector( 2 downto 0);`
175			`signal D_LAST_M : std_logic;`
176			`signal D_IO_RD : std_logic;`
177			`signal D_IO_WR : std_logic;`
178			`-- select signals`
179			`signal D_SX : std_logic_vector(1 downto 0);`
180			`signal D_SY : std_logic_vector(3 downto 0);`
181			`signal D_OP : std_logic_vector(4 downto 0);`
182			`signal D_SA : std_logic_vector(4 downto 0);`
183			`signal D_SMQ : std_logic;`
184			`-- write enable/select signals`
185			`signal D_WE_RR : std_logic;`
186			`signal D_WE_LL : std_logic;`
187			`signal D_WE_SP : SP_OP;`
188			`signal D_MEM_WE : std_logic;`
189			`signal MEM_WE : std_logic;`
190
191			`-- core signals`
192			`--`
193			`signal C_IMM : std_logic_vector(15 downto 0);`
194			`signal ADR : std_logic_vector(15 downto 0);`
195
196			`signal C_CYC : cycle; -- debug signal`
197			`signal C_PC : std_logic_vector(15 downto 0); -- debug signal`
198			`signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal`
199			`signal C_RR : std_logic_vector(15 downto 0);`
200
201			`signal RRZ : std_logic;`
202			`signal OC_JD : std_logic_vector(15 downto 0);`
203			`signal C_MQ : std_logic_vector(7 downto 0);`
204
205			`-- select signals`
206			`signal C_SX : std_logic_vector(1 downto 0);`
207			`signal C_SY : std_logic_vector(3 downto 0);`
208			`signal C_OP : std_logic_vector(4 downto 0);`
209			`signal C_SA : std_logic_vector(4 downto 0);`
210			`signal C_SMQ : std_logic;`
211			`signal C_WE_RR : std_logic;`
212			`signal C_WE_LL : std_logic;`
213			`signal C_WE_SP : SP_OP;`
214
215			`signal XM_OPC : std_logic_vector(7 downto 0);`
216			`signal LM_OPC : std_logic_vector(7 downto 0);`
217			`signal LM_RDAT : std_logic_vector(7 downto 0);`
218			`signal LXM_RDAT : std_logic_vector(7 downto 0);`
219			`signal OPCS : std_logic;`
220			`signal RDATS : std_logic;`
221
222			`begin`
223
224			`memo: memory`
225			`PORT MAP( CLK_I => CLK_I,`
226			`T2 => LT2,`
227			`CE => CE,`
228
229			`-- read in T1`
230			`PC => M_PC,`
231			`OPC => LM_OPC,`
232
233			`-- read or written in T2`
234			`ADR => ADR,`
235			`WR => MEM_WE,`
236			`WDAT => MEM_WDAT,`
237			`RDAT => LM_RDAT`
238			`);`
239
240			`ocf: opcode_fetch`
241			`PORT MAP( CLK_I => CLK_I,`
242			`T2 => LT2,`
243			`CLR => CLR,`
244			`CE => CE,`
245			`PC_OP => D_PC_OP,`
246			`JDATA => OC_JD,`
247			`RR => C_RR,`
248			`RDATA => MEM_RDAT,`
249			`PC => M_PC`
250			`);`
251
252			`opdec: opcode_decoder`
253			`PORT MAP( CLK_I => CLK_I,`
254			`T2 => LT2,`
255			`CLR => CLR,`
256			`CE => CE,`
257			`OPCODE => D_OPC,`
258			`OP_CYC => D_CYC,`
259			`INT => INT,`
260			`RRZ => RRZ,`
261
262			`OP_CAT => D_CAT,`
263			`-- select signals`
264			`D_SX => D_SX,`
265			`D_SY => D_SY,`
266			`D_OP => D_OP,`
267			`D_SA => D_SA,`
268			`D_SMQ => D_SMQ,`
269
270			`-- write enable/select signal`
271			`D_WE_RR => D_WE_RR,`
272			`D_WE_LL => D_WE_LL,`
273			`D_WE_M => D_MEM_WE,`
274			`D_WE_SP => D_WE_SP,`
275
276			`IO_RD => D_IO_RD,`
277			`IO_WR => D_IO_WR,`
278
279			`PC_OP => D_PC_OP,`
280			`LAST_M => D_LAST_M,`
281			`HLT => HALT`
282			`);`
283
284			`dcore: data_core`
285			`PORT MAP( CLK_I => CLK_I,`
286			`T2 => LT2,`
287			`CLR => CLR,`
288			`CE => CE,`
289
290			`-- select signals`
291			`SX => C_SX,`
292			`SY => C_SY,`
293			`OP => C_OP,`
294			`PC => C_PC,`
295			`QU => C_OPC(3 downto 0),`
296			`SA => C_SA,`
297			`SMQ => C_SMQ,`
298
299			`-- write enable/select signal`
300			`WE_RR => C_WE_RR,`
301			`WE_LL => C_WE_LL,`
302			`WE_SP => C_WE_SP,`
303
304			`IMM => C_IMM,`
305			`M_RDAT => MEM_RDAT,`
306			`ADR => ADR,`
307			`MQ => MEM_WDAT,`
308
309			`IO_RDAT => IO_RDAT,`
310
311			`Q_RR => C_RR,`
312			`Q_LL => Q_LL,`
313			`Q_SP => Q_SP`
314			`);`
315
316			`CE <= '1';`
317			`T2 <= LT2;`
318
319			`IO_ADR <= ADR(7 downto 0);`
320			`Q_RR <= C_RR;`
321			`RRZ <= '1' when (C_RR = X"0000") else '0';`
322			`OC_JD <= M_OPC & C_IMM(7 downto 0);`
323
324			`Q_PC <= C_PC;`
325			`Q_OPC <= C_OPC;`
326			`Q_CYC <= C_CYC;`
327			`Q_IMM <= C_IMM;`
328
329			`-- select signals`
330			`Q_SX <= C_SX;`
331			`Q_SY <= C_SY;`
332			`Q_OP <= C_OP;`
333			`Q_SA <= C_SA;`
334			`Q_SMQ <= C_SMQ;`
335
336			`-- write enable/select signal`
337			`Q_WE_RR <= C_WE_RR;`
338			`Q_WE_LL <= C_WE_LL;`
339			`Q_WE_SP <= C_WE_SP;`
340
341			`XM_WDAT <= MEM_WDAT;`
342
343			`process(CLK_I)`
344			`begin`
345			`if (rising_edge(CLK_I)) then`
346			`LT2 <= not LT2;`
347			`end if;`
348			`end process;`
349
350			`process(CLK_I)`
351			`begin`
352			`if (rising_edge(CLK_I)) then`
353			`if (LT2 = '1') then`
354			`RDATS <= ADR(15) or ADR(14) or ADR(13);`
355			`LXM_RDAT <= XM_RDAT;`
356			`end if;`
357			`end if;`
358			`end process;`
359
360			`process(CLK_I)`
361			`begin`
362			`if (rising_edge(CLK_I)) then`
363			`if (LT2 = '0') then`
364			`OPCS <= M_PC(15) or M_PC(14) or M_PC(13);`
365			`XM_OPC <= XM_RDAT;`
366			`end if;`
367			`end if;`
368			`end process;`
369
370			`process(OPCS, LM_OPC, XM_OPC)`
371			`begin`
372			`if (OPCS = '0') then M_OPC <= LM_OPC;`
373			`else M_OPC <= XM_OPC;`
374			`end if;`
375			`end process;`
376
377			`process(RDATS, LXM_RDAT, LM_RDAT)`
378			`begin`
379			`if (RDATS = '0') then MEM_RDAT <= LM_RDAT;`
380			`else MEM_RDAT <= LXM_RDAT;`
381			`end if;`
382			`end process;`
383
384			`process(LT2, M_PC, ADR, MEM_WE)`
385			`begin`
386			`if (LT2 = '0') then -- opcode fetch`
387			`XM_ADR <= M_PC;`
388			`XM_WE <= '0';`
389			`XM_CE <= M_PC(15) or M_PC(14) or M_PC(13);`
390			`else -- data`
391			`XM_ADR <= ADR;`
392			`XM_WE <= MEM_WE;`
393			`XM_CE <= ADR(15) or ADR(14) or ADR(13);`
394			`end if;`
395			`end process;`
396
397			`process(CLK_I)`
398			`begin`
399			`if (rising_edge(CLK_I)) then`
400			`if (LT2 = '1') then`
401			`if (CLR = '1') then`
402			`D_PC <= X"0000";`
403			`D_OPC <= X"01";`
404			`D_CYC <= M1;`
405
406			`C_PC <= X"0000";`
407			`C_OPC <= X"01";`
408			`C_CYC <= M1;`
409			`C_IMM <= X"FFFF";`
410
411			`C_SX <= "00";`
412			`C_SY <= "0000";`
413			`C_OP <= "00000";`
414			`C_SA <= "00000";`
415			`C_SMQ <= '0';`
416			`C_WE_RR <= '0';`
417			`C_WE_LL <= '0';`
418			`C_WE_SP <= SP_NOP;`
419			`MEM_WE <= '0';`
420
421			`elsif (CE = '1') then`
422			`C_CYC <= D_CYC;`
423			`Q_CAT <= D_CAT;`
424			`C_PC <= D_PC;`
425			`C_OPC <= D_OPC;`
426			`C_SX <= D_SX;`
427			`C_SY <= D_SY;`
428			`C_OP <= D_OP;`
429			`C_SA <= D_SA;`
430			`C_SMQ <= D_SMQ;`
431			`C_WE_RR <= D_WE_RR;`
432			`C_WE_LL <= D_WE_LL;`
433			`C_WE_SP <= D_WE_SP;`
434			`IO_RD <= D_IO_RD;`
435			`IO_WR <= D_IO_WR;`
436			`MEM_WE <= D_MEM_WE;`
437
438			`if (D_LAST_M = '1') then -- D goes to M1`
439			`-- signals valid for entire opcode...`
440			`D_OPC <= M_OPC;`
441			`D_PC <= M_PC;`
442			`D_CYC <= M1;`
443			`else`
444			`case D_CYC is`
445			`when M1 => D_CYC <= M2; -- C goes to M1`
446			`C_IMM <= X"00" & M_OPC;`
447			`when M2 => D_CYC <= M3;`
448			`C_IMM(15 downto 8) <= M_OPC;`
449			`when M3 => D_CYC <= M4;`
450			`when M4 => D_CYC <= M5;`
451			`when M5 => D_CYC <= M1;`
452			`end case;`
453			`end if;`
454			`end if;`
455			`end if;`
456			`end if;`
457			`end process;`
458
459			`end Behavioral;`