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[/] [c16/] [trunk/] [vhdl/] [data_core.vhd] - Blame information for rev 2

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity data_core is
        PORT(   CLK_I : in  std_logic;
                        T2    : in  std_logic;
                        CLR   : in  std_logic;
                        CE    : in  std_logic;
 
                        -- select signals
                        SX    : in  std_logic_vector( 1 downto 0);
                        SY    : in  std_logic_vector( 3 downto 0);
                        OP    : in  std_logic_vector( 4 downto 0);               -- alu op
                        PC    : in  std_logic_vector(15 downto 0);               -- PC
                        QU    : in  std_logic_vector( 3 downto 0);                       -- quick operand
                        SA    : in  std_logic_vector(4 downto 0);                        -- select address
                        SMQ   : in  std_logic;                                                  -- select MQ (H/L)
 
                        -- write enable/select signal
                        WE_RR : in  std_logic;
                        WE_LL : in  std_logic;
                        WE_SP : in  SP_OP;
 
                        -- data in signals
                        IMM  : in  std_logic_vector(15 downto 0);                -- immediate data
                        M_RDAT : in  std_logic_vector( 7 downto 0);              -- memory data
 
                        -- memory control signals
                        ADR     : out std_logic_vector(15 downto 0);
                        MQ     : out std_logic_vector( 7 downto 0);
 
                        -- input/output
                        IO_RDAT: in  std_logic_vector( 7 downto 0);
 
                        Q_RR   : out std_logic_vector(15 downto 0);
                        Q_LL   : out std_logic_vector(15 downto 0);
                        Q_SP   : out std_logic_vector(15 downto 0)
                );
end data_core;
 
architecture Behavioral of data_core is
 
        function b8(A : std_logic) return std_logic_vector is
        begin
                return A & A & A & A & A & A & A & A;
        end;
 
        COMPONENT alu8
        PORT(   CLK_I : in  std_logic;
                        T2    : in  std_logic;
                        CE    : in  std_logic;
                        CLR   : in  std_logic;
 
                        ALU_OP : IN  std_logic_vector( 4 downto 0);
                        XX     : IN  std_logic_vector(15 downto 0);
                        YY     : IN  std_logic_vector(15 downto 0);
                        ZZ     : OUT std_logic_vector(15 downto 0)
                );
        END COMPONENT;
 
        COMPONENT select_yy
        PORT(   SY      : IN  std_logic_vector( 3 downto 0);
                        IMM     : IN  std_logic_vector(15 downto 0);
                        QUICK   : IN  std_logic_vector( 3 downto 0);
                        M_RDAT  : IN  std_logic_vector( 7 downto 0);
                        IO_RDAT : IN  std_logic_vector( 7 downto 0);
                        RR      : IN  std_logic_vector(15 downto 0);
                        YY      : OUT std_logic_vector(15 downto 0)
                );
        END COMPONENT;
 
        -- cpu registers
        --
        signal RR     : std_logic_vector(15 downto 0);
        signal LL     : std_logic_vector(15 downto 0);
        signal SP     : std_logic_vector(15 downto 0);
 
        -- internal buses
        --
        signal XX      : std_logic_vector(15 downto 0);
        signal YY      : std_logic_vector(15 downto 0);
        signal ZZ      : std_logic_vector(15 downto 0);
        signal ADR_X   : std_logic_vector(15 downto 0);
        signal ADR_Z   : std_logic_vector(15 downto 0);
        signal ADR_YZ  : std_logic_vector(15 downto 0);
        signal ADR_XYZ : std_logic_vector(15 downto 0);
 
begin
 
        alu_8: alu8
        PORT MAP(       CLK_I  => CLK_I,
                                T2     => T2,
                                CE     => CE,
                                CLR    => CLR,
                                ALU_OP => OP,
                                XX     => XX,
                                YY     => YY,
                                ZZ     => ZZ
        );
 
        selyy: select_yy
        PORT MAP(       SY      => SY,
                                IMM     => IMM,
                                QUICK   => QU,
                                M_RDAT  => M_RDAT,
                                IO_RDAT => IO_RDAT,
                                RR      => RR,
                                YY      => YY
        );
 
        ADR             <= ADR_XYZ;
        MQ      <= ZZ(15 downto 8) when SMQ = '1' else ZZ(7 downto 0);
 
        Q_RR <= RR;
        Q_LL <= LL;
        Q_SP <= SP;
 
        -- memory address
        --
        sel_ax: process(SA(4 downto 3), IMM)
 
                variable SAX : std_logic_vector(4 downto 3);
 
        begin
                SAX := SA(4 downto 3);
 
                case SAX is
 
                        when SA_43_I16 =>       ADR_X <= IMM;
                        when SA_43_I8S =>       ADR_X <= b8(IMM(7)) & IMM(7 downto 0);
                        when others        =>   ADR_X <= b8(SA(3)) & b8(SA(3));
                end case;
        end process;
 
        sel_az: process(SA(2 downto 1), LL, RR, SP)
 
                variable SAZ : std_logic_vector(2 downto 1);
 
        begin
                SAZ := SA(2 downto 1);
 
                case SAZ is
                        when SA_21_0  =>        ADR_Z <= X"0000";
                        when SA_21_LL =>        ADR_Z <= LL;
                        when SA_21_RR =>        ADR_Z <= RR;
                        when others       =>    ADR_Z <= SP;
                end case;
        end process;
 
        sel_ayz: process(SA(0), ADR_Z)
        begin
                ADR_YZ <= ADR_Z + (X"000" & "000" & SA(0));
        end process;
 
        sel_axyz: process(ADR_X, ADR_YZ)
        begin
                ADR_XYZ <= ADR_X + ADR_YZ;
        end process;
 
        sel_xx: process(SX, LL, RR, SP, PC)
        begin
                case SX is
                        when SX_LL      =>      XX <= LL;
                        when SX_RR      =>      XX <= RR;
                        when SX_SP      =>      XX <= SP;
                        when others     =>      XX <= PC;
                end case;
        end process;
 
        regs: process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if    (T2 = '1') then
                                if    (CLR = '1') then
                                        RR  <= X"0000";
                                        LL  <= X"0000";
                                        SP  <= X"0000";
                                elsif (CE  = '1') then
                                        if (WE_RR = '1') then           RR  <= ZZ;              end if;
                                        if (WE_LL = '1') then           LL  <= ZZ;              end if;
 
                                        case WE_SP is
                                                when SP_INC     =>              SP <= ADR_YZ;
                                                when SP_LOAD    =>              SP <= ADR_XYZ;
                                                when SP_NOP             =>              null;
                                        end case;
                                end if;
                        end if;
                end if;
        end process;
 
end Behavioral;

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Subversion Repositories c16

[/] [c16/] [trunk/] [vhdl/] [data_core.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`-- Uncomment the following lines to use the declarations that are`
7			`-- provided for instantiating Xilinx primitive components.`
8			`--library UNISIM;`
9			`--use UNISIM.VComponents.all;`
10
11			`use work.cpu_pack.ALL;`
12
13			`entity data_core is`
14			`PORT( CLK_I : in std_logic;`
15			`T2 : in std_logic;`
16			`CLR : in std_logic;`
17			`CE : in std_logic;`
18
19			`-- select signals`
20			`SX : in std_logic_vector( 1 downto 0);`
21			`SY : in std_logic_vector( 3 downto 0);`
22			`OP : in std_logic_vector( 4 downto 0); -- alu op`
23			`PC : in std_logic_vector(15 downto 0); -- PC`
24			`QU : in std_logic_vector( 3 downto 0); -- quick operand`
25			`SA : in std_logic_vector(4 downto 0); -- select address`
26			`SMQ : in std_logic; -- select MQ (H/L)`
27
28			`-- write enable/select signal`
29			`WE_RR : in std_logic;`
30			`WE_LL : in std_logic;`
31			`WE_SP : in SP_OP;`
32
33			`-- data in signals`
34			`IMM : in std_logic_vector(15 downto 0); -- immediate data`
35			`M_RDAT : in std_logic_vector( 7 downto 0); -- memory data`
36
37			`-- memory control signals`
38			`ADR : out std_logic_vector(15 downto 0);`
39			`MQ : out std_logic_vector( 7 downto 0);`
40
41			`-- input/output`
42			`IO_RDAT: in std_logic_vector( 7 downto 0);`
43
44			`Q_RR : out std_logic_vector(15 downto 0);`
45			`Q_LL : out std_logic_vector(15 downto 0);`
46			`Q_SP : out std_logic_vector(15 downto 0)`
47			`);`
48			`end data_core;`
49
50			`architecture Behavioral of data_core is`
51
52			`function b8(A : std_logic) return std_logic_vector is`
53			`begin`
54			`return A & A & A & A & A & A & A & A;`
55			`end;`
56
57			`COMPONENT alu8`
58			`PORT( CLK_I : in std_logic;`
59			`T2 : in std_logic;`
60			`CE : in std_logic;`
61			`CLR : in std_logic;`
62
63			`ALU_OP : IN std_logic_vector( 4 downto 0);`
64			`XX : IN std_logic_vector(15 downto 0);`
65			`YY : IN std_logic_vector(15 downto 0);`
66			`ZZ : OUT std_logic_vector(15 downto 0)`
67			`);`
68			`END COMPONENT;`
69
70			`COMPONENT select_yy`
71			`PORT( SY : IN std_logic_vector( 3 downto 0);`
72			`IMM : IN std_logic_vector(15 downto 0);`
73			`QUICK : IN std_logic_vector( 3 downto 0);`
74			`M_RDAT : IN std_logic_vector( 7 downto 0);`
75			`IO_RDAT : IN std_logic_vector( 7 downto 0);`
76			`RR : IN std_logic_vector(15 downto 0);`
77			`YY : OUT std_logic_vector(15 downto 0)`
78			`);`
79			`END COMPONENT;`
80
81			`-- cpu registers`
82			`--`
83			`signal RR : std_logic_vector(15 downto 0);`
84			`signal LL : std_logic_vector(15 downto 0);`
85			`signal SP : std_logic_vector(15 downto 0);`
86
87			`-- internal buses`
88			`--`
89			`signal XX : std_logic_vector(15 downto 0);`
90			`signal YY : std_logic_vector(15 downto 0);`
91			`signal ZZ : std_logic_vector(15 downto 0);`
92			`signal ADR_X : std_logic_vector(15 downto 0);`
93			`signal ADR_Z : std_logic_vector(15 downto 0);`
94			`signal ADR_YZ : std_logic_vector(15 downto 0);`
95			`signal ADR_XYZ : std_logic_vector(15 downto 0);`
96
97			`begin`
98
99			`alu_8: alu8`
100			`PORT MAP( CLK_I => CLK_I,`
101			`T2 => T2,`
102			`CE => CE,`
103			`CLR => CLR,`
104			`ALU_OP => OP,`
105			`XX => XX,`
106			`YY => YY,`
107			`ZZ => ZZ`
108			`);`
109
110			`selyy: select_yy`
111			`PORT MAP( SY => SY,`
112			`IMM => IMM,`
113			`QUICK => QU,`
114			`M_RDAT => M_RDAT,`
115			`IO_RDAT => IO_RDAT,`
116			`RR => RR,`
117			`YY => YY`
118			`);`
119
120			`ADR <= ADR_XYZ;`
121			`MQ <= ZZ(15 downto 8) when SMQ = '1' else ZZ(7 downto 0);`
122
123			`Q_RR <= RR;`
124			`Q_LL <= LL;`
125			`Q_SP <= SP;`
126
127			`-- memory address`
128			`--`
129			`sel_ax: process(SA(4 downto 3), IMM)`
130
131			`variable SAX : std_logic_vector(4 downto 3);`
132
133			`begin`
134			`SAX := SA(4 downto 3);`
135
136			`case SAX is`
137
138			`when SA_43_I16 => ADR_X <= IMM;`
139			`when SA_43_I8S => ADR_X <= b8(IMM(7)) & IMM(7 downto 0);`
140			`when others => ADR_X <= b8(SA(3)) & b8(SA(3));`
141			`end case;`
142			`end process;`
143
144			`sel_az: process(SA(2 downto 1), LL, RR, SP)`
145
146			`variable SAZ : std_logic_vector(2 downto 1);`
147
148			`begin`
149			`SAZ := SA(2 downto 1);`
150
151			`case SAZ is`
152			`when SA_21_0 => ADR_Z <= X"0000";`
153			`when SA_21_LL => ADR_Z <= LL;`
154			`when SA_21_RR => ADR_Z <= RR;`
155			`when others => ADR_Z <= SP;`
156			`end case;`
157			`end process;`
158
159			`sel_ayz: process(SA(0), ADR_Z)`
160			`begin`
161			`ADR_YZ <= ADR_Z + (X"000" & "000" & SA(0));`
162			`end process;`
163
164			`sel_axyz: process(ADR_X, ADR_YZ)`
165			`begin`
166			`ADR_XYZ <= ADR_X + ADR_YZ;`
167			`end process;`
168
169			`sel_xx: process(SX, LL, RR, SP, PC)`
170			`begin`
171			`case SX is`
172			`when SX_LL => XX <= LL;`
173			`when SX_RR => XX <= RR;`
174			`when SX_SP => XX <= SP;`
175			`when others => XX <= PC;`
176			`end case;`
177			`end process;`
178
179			`regs: process(CLK_I)`
180			`begin`
181			`if (rising_edge(CLK_I)) then`
182			`if (T2 = '1') then`
183			`if (CLR = '1') then`
184			`RR <= X"0000";`
185			`LL <= X"0000";`
186			`SP <= X"0000";`
187			`elsif (CE = '1') then`
188			`if (WE_RR = '1') then RR <= ZZ; end if;`
189			`if (WE_LL = '1') then LL <= ZZ; end if;`
190
191			`case WE_SP is`
192			`when SP_INC => SP <= ADR_YZ;`
193			`when SP_LOAD => SP <= ADR_XYZ;`
194			`when SP_NOP => null;`
195			`end case;`
196			`end if;`
197			`end if;`
198			`end if;`
199			`end process;`
200
201			`end Behavioral;`