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[/] [c16/] [trunk/] [vhdl/] [data_core.vhd] - Blame information for rev 26

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1 2 jsauermann
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--  Uncomment the following lines to use the declarations that are
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--  provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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use work.cpu_pack.ALL;
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entity data_core is
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        PORT(   CLK_I : in  std_logic;
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                        T2    : in  std_logic;
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                        CLR   : in  std_logic;
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                        CE    : in  std_logic;
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                        -- select signals
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                        SX    : in  std_logic_vector( 1 downto 0);
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                        SY    : in  std_logic_vector( 3 downto 0);
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                        OP    : in  std_logic_vector( 4 downto 0);               -- alu op
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                        PC    : in  std_logic_vector(15 downto 0);               -- PC
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                        QU    : in  std_logic_vector( 3 downto 0);                       -- quick operand
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                        SA    : in  std_logic_vector(4 downto 0);                        -- select address
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                        SMQ   : in  std_logic;                                                  -- select MQ (H/L)
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                        -- write enable/select signal
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                        WE_RR : in  std_logic;
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                        WE_LL : in  std_logic;
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                        WE_SP : in  SP_OP;
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                        -- data in signals
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                        IMM  : in  std_logic_vector(15 downto 0);                -- immediate data
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                        RDAT : in  std_logic_vector( 7 downto 0);                -- memory/IO data
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                        -- memory control signals
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                        ADR     : out std_logic_vector(15 downto 0);
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                        MQ     : out std_logic_vector( 7 downto 0);
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                        Q_RR   : out std_logic_vector(15 downto 0);
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                        Q_LL   : out std_logic_vector(15 downto 0);
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                        Q_SP   : out std_logic_vector(15 downto 0)
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                );
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end data_core;
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architecture Behavioral of data_core is
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        function b8(A : std_logic) return std_logic_vector is
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        begin
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                return A & A & A & A & A & A & A & A;
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        end;
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        COMPONENT alu8
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        PORT(   CLK_I : in  std_logic;
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                        T2    : in  std_logic;
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                        CE    : in  std_logic;
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                        CLR   : in  std_logic;
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                        ALU_OP : IN  std_logic_vector( 4 downto 0);
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                        XX     : IN  std_logic_vector(15 downto 0);
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                        YY     : IN  std_logic_vector(15 downto 0);
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                        ZZ     : OUT std_logic_vector(15 downto 0)
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                );
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        END COMPONENT;
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        COMPONENT select_yy
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        PORT(   SY      : IN  std_logic_vector( 3 downto 0);
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                        IMM     : IN  std_logic_vector(15 downto 0);
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                        QUICK   : IN  std_logic_vector( 3 downto 0);
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                        RDAT    : IN  std_logic_vector( 7 downto 0);
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                        RR      : IN  std_logic_vector(15 downto 0);
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                        YY      : OUT std_logic_vector(15 downto 0)
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                );
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        END COMPONENT;
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        -- cpu registers
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        --
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        signal RR     : std_logic_vector(15 downto 0);
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        signal LL     : std_logic_vector(15 downto 0);
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        signal SP     : std_logic_vector(15 downto 0);
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        -- internal buses
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        --
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        signal XX      : std_logic_vector(15 downto 0);
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        signal YY      : std_logic_vector(15 downto 0);
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        signal ZZ      : std_logic_vector(15 downto 0);
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        signal ADR_X   : std_logic_vector(15 downto 0);
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        signal ADR_Z   : std_logic_vector(15 downto 0);
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        signal ADR_YZ  : std_logic_vector(15 downto 0);
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        signal ADR_XYZ : std_logic_vector(15 downto 0);
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begin
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        alu_8: alu8
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        PORT MAP(       CLK_I  => CLK_I,
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                                T2     => T2,
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                                CE     => CE,
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                                CLR    => CLR,
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                                ALU_OP => OP,
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                                XX     => XX,
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                                YY     => YY,
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                                ZZ     => ZZ
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        );
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        selyy: select_yy
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        PORT MAP(       SY      => SY,
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                                IMM     => IMM,
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                                QUICK   => QU,
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                                RDAT    => RDAT,
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                                RR      => RR,
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                                YY      => YY
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        );
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        ADR             <= ADR_XYZ;
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        MQ      <= ZZ(15 downto 8) when SMQ = '1' else ZZ(7 downto 0);
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        Q_RR <= RR;
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        Q_LL <= LL;
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        Q_SP <= SP;
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        -- memory address
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        --
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        sel_ax: process(SA(4 downto 3), IMM)
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                variable SAX : std_logic_vector(4 downto 3);
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        begin
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                SAX := SA(4 downto 3);
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                case SAX is
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                        when SA_43_I16 =>       ADR_X <= IMM;
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                        when SA_43_I8S =>       ADR_X <= b8(IMM(7)) & IMM(7 downto 0);
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                        when others        =>   ADR_X <= b8(SA(3)) & b8(SA(3));
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                end case;
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        end process;
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        sel_az: process(SA(2 downto 1), LL, RR, SP)
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                variable SAZ : std_logic_vector(2 downto 1);
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        begin
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                SAZ := SA(2 downto 1);
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                case SAZ is
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                        when SA_21_0  =>        ADR_Z <= X"0000";
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                        when SA_21_LL =>        ADR_Z <= LL;
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                        when SA_21_RR =>        ADR_Z <= RR;
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                        when others       =>    ADR_Z <= SP;
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                end case;
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        end process;
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        sel_ayz: process(SA(0), ADR_Z)
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        begin
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                ADR_YZ <= ADR_Z + (X"000" & "000" & SA(0));
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        end process;
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        sel_axyz: process(ADR_X, ADR_YZ)
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        begin
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                ADR_XYZ <= ADR_X + ADR_YZ;
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        end process;
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        sel_xx: process(SX, LL, RR, SP, PC)
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        begin
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                case SX is
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                        when SX_LL      =>      XX <= LL;
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                        when SX_RR      =>      XX <= RR;
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                        when SX_SP      =>      XX <= SP;
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                        when others     =>      XX <= PC;
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                end case;
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        end process;
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        regs: process(CLK_I)
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        begin
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                if (rising_edge(CLK_I)) then
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                        if    (CLR = '1') then
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                                RR  <= X"0000";
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                                LL  <= X"0000";
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                                SP  <= X"0000";
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                        elsif (CE  = '1' and T2 = '1') then
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                                if (WE_RR = '1') then           RR  <= ZZ;              end if;
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                                if (WE_LL = '1') then           LL  <= ZZ;              end if;
184 2 jsauermann
 
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                                case WE_SP is
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                                        when SP_INC     =>              SP <= ADR_YZ;
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                                        when SP_LOAD    =>              SP <= ADR_XYZ;
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                                        when SP_NOP             =>              null;
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                                end case;
190 2 jsauermann
                        end if;
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                end if;
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        end process;
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end Behavioral;

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