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[/] [c16/] [trunk/] [vhdl/] [data_core.vhd] - Blame information for rev 31

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity data_core is
        PORT(   CLK_I : in  std_logic;
                        T2    : in  std_logic;
                        CLR   : in  std_logic;
                        CE    : in  std_logic;
 
                        -- select signals
                        SX    : in  std_logic_vector( 1 downto 0);
                        SY    : in  std_logic_vector( 3 downto 0);
                        OP    : in  std_logic_vector( 4 downto 0);               -- alu op
                        PC    : in  std_logic_vector(15 downto 0);               -- PC
                        QU    : in  std_logic_vector( 3 downto 0);                       -- quick operand
                        SA    : in  std_logic_vector(4 downto 0);                        -- select address
                        SMQ   : in  std_logic;                                                  -- select MQ (H/L)
 
                        -- write enable/select signal
                        WE_RR : in  std_logic;
                        WE_LL : in  std_logic;
                        WE_SP : in  SP_OP;
 
                        -- data in signals
                        IMM  : in  std_logic_vector(15 downto 0);                -- immediate data
                        RDAT : in  std_logic_vector( 7 downto 0);                -- memory/IO data
 
                        -- memory control signals
                        ADR     : out std_logic_vector(15 downto 0);
                        MQ     : out std_logic_vector( 7 downto 0);
 
                        Q_RR   : out std_logic_vector(15 downto 0);
                        Q_LL   : out std_logic_vector(15 downto 0);
                        Q_SP   : out std_logic_vector(15 downto 0)
                );
end data_core;
 
architecture Behavioral of data_core is
 
        function b8(A : std_logic) return std_logic_vector is
        begin
                return A & A & A & A & A & A & A & A;
        end;
 
        COMPONENT alu8
        PORT(   CLK_I : in  std_logic;
                        T2    : in  std_logic;
                        CE    : in  std_logic;
                        CLR   : in  std_logic;
 
                        ALU_OP : IN  std_logic_vector( 4 downto 0);
                        XX     : IN  std_logic_vector(15 downto 0);
                        YY     : IN  std_logic_vector(15 downto 0);
                        ZZ     : OUT std_logic_vector(15 downto 0)
                );
        END COMPONENT;
 
        COMPONENT select_yy
        PORT(   SY      : IN  std_logic_vector( 3 downto 0);
                        IMM     : IN  std_logic_vector(15 downto 0);
                        QUICK   : IN  std_logic_vector( 3 downto 0);
                        RDAT    : IN  std_logic_vector( 7 downto 0);
                        RR      : IN  std_logic_vector(15 downto 0);
                        YY      : OUT std_logic_vector(15 downto 0)
                );
        END COMPONENT;
 
        -- cpu registers
        --
        signal RR     : std_logic_vector(15 downto 0);
        signal LL     : std_logic_vector(15 downto 0);
        signal SP     : std_logic_vector(15 downto 0);
 
        -- internal buses
        --
        signal XX      : std_logic_vector(15 downto 0);
        signal YY      : std_logic_vector(15 downto 0);
        signal ZZ      : std_logic_vector(15 downto 0);
        signal ADR_X   : std_logic_vector(15 downto 0);
        signal ADR_Z   : std_logic_vector(15 downto 0);
        signal ADR_YZ  : std_logic_vector(15 downto 0);
        signal ADR_XYZ : std_logic_vector(15 downto 0);
 
begin
 
        alu_8: alu8
        PORT MAP(       CLK_I  => CLK_I,
                                T2     => T2,
                                CE     => CE,
                                CLR    => CLR,
                                ALU_OP => OP,
                                XX     => XX,
                                YY     => YY,
                                ZZ     => ZZ
        );
 
        selyy: select_yy
        PORT MAP(       SY      => SY,
                                IMM     => IMM,
                                QUICK   => QU,
                                RDAT    => RDAT,
                                RR      => RR,
                                YY      => YY
        );
 
        ADR             <= ADR_XYZ;
        MQ      <= ZZ(15 downto 8) when SMQ = '1' else ZZ(7 downto 0);
 
        Q_RR <= RR;
        Q_LL <= LL;
        Q_SP <= SP;
 
        -- memory address
        --
        sel_ax: process(SA(4 downto 3), IMM)
 
                variable SAX : std_logic_vector(4 downto 3);
 
        begin
                SAX := SA(4 downto 3);
 
                case SAX is
 
                        when SA_43_I16 =>       ADR_X <= IMM;
                        when SA_43_I8S =>       ADR_X <= b8(IMM(7)) & IMM(7 downto 0);
                        when others        =>   ADR_X <= b8(SA(3)) & b8(SA(3));
                end case;
        end process;
 
        sel_az: process(SA(2 downto 1), LL, RR, SP)
 
                variable SAZ : std_logic_vector(2 downto 1);
 
        begin
                SAZ := SA(2 downto 1);
 
                case SAZ is
                        when SA_21_0  =>        ADR_Z <= X"0000";
                        when SA_21_LL =>        ADR_Z <= LL;
                        when SA_21_RR =>        ADR_Z <= RR;
                        when others       =>    ADR_Z <= SP;
                end case;
        end process;
 
        sel_ayz: process(SA(0), ADR_Z)
        begin
                ADR_YZ <= ADR_Z + (X"000" & "000" & SA(0));
        end process;
 
        sel_axyz: process(ADR_X, ADR_YZ)
        begin
                ADR_XYZ <= ADR_X + ADR_YZ;
        end process;
 
        sel_xx: process(SX, LL, RR, SP, PC)
        begin
                case SX is
                        when SX_LL      =>      XX <= LL;
                        when SX_RR      =>      XX <= RR;
                        when SX_SP      =>      XX <= SP;
                        when others     =>      XX <= PC;
                end case;
        end process;
 
        regs: process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if    (CLR = '1') then
                                RR  <= X"0000";
                                LL  <= X"0000";
                                SP  <= X"0000";
                        elsif (CE  = '1' and T2 = '1') then
                                if (WE_RR = '1') then           RR  <= ZZ;              end if;
                                if (WE_LL = '1') then           LL  <= ZZ;              end if;
 
                                case WE_SP is
                                        when SP_INC     =>              SP <= ADR_YZ;
                                        when SP_LOAD    =>              SP <= ADR_XYZ;
                                        when SP_NOP             =>              null;
                                end case;
                        end if;
                end if;
        end process;
 
end Behavioral;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`-- Uncomment the following lines to use the declarations that are`
7			`-- provided for instantiating Xilinx primitive components.`
8			`--library UNISIM;`
9			`--use UNISIM.VComponents.all;`
10
11			`use work.cpu_pack.ALL;`
12
13			`entity data_core is`
14			`PORT( CLK_I : in std_logic;`
15			`T2 : in std_logic;`
16			`CLR : in std_logic;`
17			`CE : in std_logic;`
18
19			`-- select signals`
20			`SX : in std_logic_vector( 1 downto 0);`
21			`SY : in std_logic_vector( 3 downto 0);`
22			`OP : in std_logic_vector( 4 downto 0); -- alu op`
23			`PC : in std_logic_vector(15 downto 0); -- PC`
24			`QU : in std_logic_vector( 3 downto 0); -- quick operand`
25			`SA : in std_logic_vector(4 downto 0); -- select address`
26			`SMQ : in std_logic; -- select MQ (H/L)`
27
28			`-- write enable/select signal`
29			`WE_RR : in std_logic;`
30			`WE_LL : in std_logic;`
31			`WE_SP : in SP_OP;`
32
33			`-- data in signals`
34			`IMM : in std_logic_vector(15 downto 0); -- immediate data`
35	9	jsauermann	`RDAT : in std_logic_vector( 7 downto 0); -- memory/IO data`
36	2	jsauermann
37			`-- memory control signals`
38			`ADR : out std_logic_vector(15 downto 0);`
39			`MQ : out std_logic_vector( 7 downto 0);`
40
41			`Q_RR : out std_logic_vector(15 downto 0);`
42			`Q_LL : out std_logic_vector(15 downto 0);`
43			`Q_SP : out std_logic_vector(15 downto 0)`
44			`);`
45			`end data_core;`
46
47			`architecture Behavioral of data_core is`
48
49			`function b8(A : std_logic) return std_logic_vector is`
50			`begin`
51			`return A & A & A & A & A & A & A & A;`
52			`end;`
53
54			`COMPONENT alu8`
55			`PORT( CLK_I : in std_logic;`
56			`T2 : in std_logic;`
57			`CE : in std_logic;`
58			`CLR : in std_logic;`
59
60			`ALU_OP : IN std_logic_vector( 4 downto 0);`
61			`XX : IN std_logic_vector(15 downto 0);`
62			`YY : IN std_logic_vector(15 downto 0);`
63			`ZZ : OUT std_logic_vector(15 downto 0)`
64			`);`
65			`END COMPONENT;`
66
67			`COMPONENT select_yy`
68			`PORT( SY : IN std_logic_vector( 3 downto 0);`
69			`IMM : IN std_logic_vector(15 downto 0);`
70			`QUICK : IN std_logic_vector( 3 downto 0);`
71	9	jsauermann	`RDAT : IN std_logic_vector( 7 downto 0);`
72	2	jsauermann	`RR : IN std_logic_vector(15 downto 0);`
73			`YY : OUT std_logic_vector(15 downto 0)`
74			`);`
75			`END COMPONENT;`
76
77			`-- cpu registers`
78			`--`
79			`signal RR : std_logic_vector(15 downto 0);`
80			`signal LL : std_logic_vector(15 downto 0);`
81			`signal SP : std_logic_vector(15 downto 0);`
82
83			`-- internal buses`
84			`--`
85			`signal XX : std_logic_vector(15 downto 0);`
86			`signal YY : std_logic_vector(15 downto 0);`
87			`signal ZZ : std_logic_vector(15 downto 0);`
88			`signal ADR_X : std_logic_vector(15 downto 0);`
89			`signal ADR_Z : std_logic_vector(15 downto 0);`
90			`signal ADR_YZ : std_logic_vector(15 downto 0);`
91			`signal ADR_XYZ : std_logic_vector(15 downto 0);`
92
93			`begin`
94
95			`alu_8: alu8`
96			`PORT MAP( CLK_I => CLK_I,`
97			`T2 => T2,`
98			`CE => CE,`
99			`CLR => CLR,`
100			`ALU_OP => OP,`
101			`XX => XX,`
102			`YY => YY,`
103			`ZZ => ZZ`
104			`);`
105
106			`selyy: select_yy`
107			`PORT MAP( SY => SY,`
108			`IMM => IMM,`
109			`QUICK => QU,`
110	9	jsauermann	`RDAT => RDAT,`
111	2	jsauermann	`RR => RR,`
112			`YY => YY`
113			`);`
114
115			`ADR <= ADR_XYZ;`
116			`MQ <= ZZ(15 downto 8) when SMQ = '1' else ZZ(7 downto 0);`
117
118			`Q_RR <= RR;`
119			`Q_LL <= LL;`
120			`Q_SP <= SP;`
121
122			`-- memory address`
123			`--`
124			`sel_ax: process(SA(4 downto 3), IMM)`
125
126			`variable SAX : std_logic_vector(4 downto 3);`
127
128			`begin`
129			`SAX := SA(4 downto 3);`
130
131			`case SAX is`
132
133			`when SA_43_I16 => ADR_X <= IMM;`
134			`when SA_43_I8S => ADR_X <= b8(IMM(7)) & IMM(7 downto 0);`
135			`when others => ADR_X <= b8(SA(3)) & b8(SA(3));`
136			`end case;`
137			`end process;`
138
139			`sel_az: process(SA(2 downto 1), LL, RR, SP)`
140
141			`variable SAZ : std_logic_vector(2 downto 1);`
142
143			`begin`
144			`SAZ := SA(2 downto 1);`
145
146			`case SAZ is`
147			`when SA_21_0 => ADR_Z <= X"0000";`
148			`when SA_21_LL => ADR_Z <= LL;`
149			`when SA_21_RR => ADR_Z <= RR;`
150			`when others => ADR_Z <= SP;`
151			`end case;`
152			`end process;`
153
154			`sel_ayz: process(SA(0), ADR_Z)`
155			`begin`
156			`ADR_YZ <= ADR_Z + (X"000" & "000" & SA(0));`
157			`end process;`
158
159			`sel_axyz: process(ADR_X, ADR_YZ)`
160			`begin`
161			`ADR_XYZ <= ADR_X + ADR_YZ;`
162			`end process;`
163
164			`sel_xx: process(SX, LL, RR, SP, PC)`
165			`begin`
166			`case SX is`
167			`when SX_LL => XX <= LL;`
168			`when SX_RR => XX <= RR;`
169			`when SX_SP => XX <= SP;`
170			`when others => XX <= PC;`
171			`end case;`
172			`end process;`
173
174			`regs: process(CLK_I)`
175			`begin`
176			`if (rising_edge(CLK_I)) then`
177	9	jsauermann	`if (CLR = '1') then`
178			`RR <= X"0000";`
179			`LL <= X"0000";`
180			`SP <= X"0000";`
181			`elsif (CE = '1' and T2 = '1') then`
182			`if (WE_RR = '1') then RR <= ZZ; end if;`
183			`if (WE_LL = '1') then LL <= ZZ; end if;`
184	2	jsauermann
185	9	jsauermann	`case WE_SP is`
186			`when SP_INC => SP <= ADR_YZ;`
187			`when SP_LOAD => SP <= ADR_XYZ;`
188			`when SP_NOP => null;`
189			`end case;`
190	2	jsauermann	`end if;`
191			`end if;`
192			`end process;`
193
194			`end Behavioral;`

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