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[/] [c16/] [trunk/] [vhdl/] [ds1722.vhd] - Blame information for rev 2

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
entity DS1722 is
    Port(       CLK_I:      in          std_logic;
                        T2:         in          std_logic;
                        RESET:      in          std_logic;
 
                        DATA_IN:        in      std_logic_vector(7 downto 0);
                        DATA_OUT:       out     std_logic_vector(7 downto 0);
                        ADDRESS:        in      std_logic_vector(7 downto 0);
 
                        START:          in      std_logic;
                        DONE:           out     std_logic;
 
                        TEMP_SPI:       out     STD_LOGIC;      -- Physical interfaes
                        TEMP_SPO:       in      STD_LOGIC;
                        TEMP_CE:        out     STD_LOGIC;
                        TEMP_SCLK:      out     STD_LOGIC
    );
end DS1722;
 
architecture DS1722_arch of DS1722 is
 
        signal counter    : std_logic_vector(7 downto 0);
        signal data_latch : std_logic_vector(7 downto 0);
 
type BIG_STATE is (     SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,
                                        DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,
                                        NEXT_TO_LAST_ONE, LAST_ONE);
 
        signal state : BIG_STATE;
 
        signal bit_count:  INTEGER range 0 to 7;
 
        signal Write: std_logic;
 
begin
 
        -- Set up counter to sample digital themometer.
        process (CLK_I, RESET)
        begin
                if (RESET = '1') then   --asynchronous RESET active High
                        counter <= "00000000";
                elsif (rising_edge(CLK_I)) then
                        if (T2 = '1') then
                                counter <= counter + "00000001";
                        end if;
                end if;
        end process;
 
        DONE     <= START when (state = LAST_ONE) else '0';
        DATA_OUT <= data_latch;
 
        Write <= ADDRESS(7);
 
        -- process to convert byte commands to SPI and SPI to byte.
        process (CLK_I, RESET)
        begin
                if (RESET='1') then     --asynchronous RESET active High
                        state     <= SET_CE;
                        TEMP_CE   <= '0';
                        TEMP_SCLK <= '0';
                        bit_count <= 0;
                elsif (rising_edge(CLK_I)) then
                        if (T2 = '1') then
                                if (counter = "11111111" and START = '1') then
                                        case state is
                                                when SET_CE =>
                                                        TEMP_SCLK <= '0';
                                                        TEMP_CE <= '1';
                                                        state <= LATCH_ADD;
                                                        bit_count <= 0;
 
                                                when LATCH_ADD =>
                                                        TEMP_SCLK <= '0';
                                                        TEMP_CE <= '1';
                                                        state <= ADD_OUT_1;
                                                        data_latch <= ADDRESS;
 
                                                when ADD_OUT_1 =>
                                                        TEMP_SCLK <= '1';
                                                        TEMP_CE <= '1';
                                                        state <= ADD_OUT_2;
                                                        TEMP_SPI <= data_latch(7);
 
                                                when ADD_OUT_2 =>
                                                        TEMP_SCLK <= '0';
                                                        TEMP_CE <= '1';
                                                        data_latch <= data_latch(6 downto 0) & data_latch(7);
                                                        if bit_count < 7 then
                                                                state <= ADD_OUT_1;
                                                                bit_count <= bit_count + 1;
                                                        else
                                                                state <= DATA;
                                                                bit_count <= 0;
                                                        end if;
 
                                                when DATA =>
                                                        data_latch <= DATA_IN;
                                                        TEMP_SCLK <= '0';
                                                        TEMP_CE <= '1';
                                                        if Write = '0' then
                                                                state <= READ_DATA_1;
                                                        else
                                                                state <= WRITE_DATA_1;
                                                        end if;
 
                                                when WRITE_DATA_1 =>
                                                        TEMP_SCLK <= '1';
                                                        TEMP_CE <= '1';
                                                        state <= WRITE_DATA_2;
                                                        TEMP_SPI <= data_latch(7);
 
                                                when WRITE_DATA_2 =>
                                                        TEMP_SCLK <= '0';
                                                        TEMP_CE <= '1';
                                                        data_latch <=  data_latch(6 downto 0) & data_latch(7);
                                                        if bit_count < 7 then
                                                                state <= WRITE_DATA_1;
                                                                bit_count <= bit_count + 1;
                                                        else
                                                                state <= NEXT_TO_LAST_ONE;
                                                                bit_count <= 0;
                                                        end if;
 
                                                when READ_DATA_1 =>
                                                        TEMP_SCLK <= '1';
                                                        TEMP_CE <= '1';
                                                        state <= READ_DATA_2;
 
                                                when READ_DATA_2 =>
                                                        TEMP_SCLK <= '0';
                                                        TEMP_CE   <= '1';
                                                        data_latch <= data_latch(6 downto 0) & TEMP_SPO;
                                                        if bit_count < 7 then
                                                                state     <= READ_DATA_1;
                                                                bit_count <= bit_count + 1;
                                                        else
                                                                state     <= NEXT_TO_LAST_ONE;
                                                                bit_count <= 0;
                                                        end if;
 
                                                when NEXT_TO_LAST_ONE =>
                                                        TEMP_CE   <= '0';
                                                        TEMP_SCLK <= '0';
                                                        state     <= LAST_ONE;
 
                                                when LAST_ONE =>
                                                        TEMP_CE   <= '0';
                                                        TEMP_SCLK <= '0';
                                                        state     <= SET_CE;
                                        end case;
                                end if;
                        end if;
                end if;
        end process;
 
end DS1722_arch;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3			`use IEEE.std_logic_unsigned.all;`
4
5			`entity DS1722 is`
6			`Port( CLK_I: in std_logic;`
7			`T2: in std_logic;`
8			`RESET: in std_logic;`
9
10			`DATA_IN: in std_logic_vector(7 downto 0);`
11			`DATA_OUT: out std_logic_vector(7 downto 0);`
12			`ADDRESS: in std_logic_vector(7 downto 0);`
13
14			`START: in std_logic;`
15			`DONE: out std_logic;`
16
17			`TEMP_SPI: out STD_LOGIC; -- Physical interfaes`
18			`TEMP_SPO: in STD_LOGIC;`
19			`TEMP_CE: out STD_LOGIC;`
20			`TEMP_SCLK: out STD_LOGIC`
21			`);`
22			`end DS1722;`
23
24			`architecture DS1722_arch of DS1722 is`
25
26			`signal counter : std_logic_vector(7 downto 0);`
27			`signal data_latch : std_logic_vector(7 downto 0);`
28
29			`type BIG_STATE is ( SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,`
30			`DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,`
31			`NEXT_TO_LAST_ONE, LAST_ONE);`
32
33			`signal state : BIG_STATE;`
34
35			`signal bit_count: INTEGER range 0 to 7;`
36
37			`signal Write: std_logic;`
38
39			`begin`
40
41			`-- Set up counter to sample digital themometer.`
42			`process (CLK_I, RESET)`
43			`begin`
44			`if (RESET = '1') then --asynchronous RESET active High`
45			`counter <= "00000000";`
46			`elsif (rising_edge(CLK_I)) then`
47			`if (T2 = '1') then`
48			`counter <= counter + "00000001";`
49			`end if;`
50			`end if;`
51			`end process;`
52
53			`DONE <= START when (state = LAST_ONE) else '0';`
54			`DATA_OUT <= data_latch;`
55
56			`Write <= ADDRESS(7);`
57
58			`-- process to convert byte commands to SPI and SPI to byte.`
59			`process (CLK_I, RESET)`
60			`begin`
61			`if (RESET='1') then --asynchronous RESET active High`
62			`state <= SET_CE;`
63			`TEMP_CE <= '0';`
64			`TEMP_SCLK <= '0';`
65			`bit_count <= 0;`
66			`elsif (rising_edge(CLK_I)) then`
67			`if (T2 = '1') then`
68			`if (counter = "11111111" and START = '1') then`
69			`case state is`
70			`when SET_CE =>`
71			`TEMP_SCLK <= '0';`
72			`TEMP_CE <= '1';`
73			`state <= LATCH_ADD;`
74			`bit_count <= 0;`
75
76			`when LATCH_ADD =>`
77			`TEMP_SCLK <= '0';`
78			`TEMP_CE <= '1';`
79			`state <= ADD_OUT_1;`
80			`data_latch <= ADDRESS;`
81
82			`when ADD_OUT_1 =>`
83			`TEMP_SCLK <= '1';`
84			`TEMP_CE <= '1';`
85			`state <= ADD_OUT_2;`
86			`TEMP_SPI <= data_latch(7);`
87
88			`when ADD_OUT_2 =>`
89			`TEMP_SCLK <= '0';`
90			`TEMP_CE <= '1';`
91			`data_latch <= data_latch(6 downto 0) & data_latch(7);`
92			`if bit_count < 7 then`
93			`state <= ADD_OUT_1;`
94			`bit_count <= bit_count + 1;`
95			`else`
96			`state <= DATA;`
97			`bit_count <= 0;`
98			`end if;`
99
100			`when DATA =>`
101			`data_latch <= DATA_IN;`
102			`TEMP_SCLK <= '0';`
103			`TEMP_CE <= '1';`
104			`if Write = '0' then`
105			`state <= READ_DATA_1;`
106			`else`
107			`state <= WRITE_DATA_1;`
108			`end if;`
109
110			`when WRITE_DATA_1 =>`
111			`TEMP_SCLK <= '1';`
112			`TEMP_CE <= '1';`
113			`state <= WRITE_DATA_2;`
114			`TEMP_SPI <= data_latch(7);`
115
116			`when WRITE_DATA_2 =>`
117			`TEMP_SCLK <= '0';`
118			`TEMP_CE <= '1';`
119			`data_latch <= data_latch(6 downto 0) & data_latch(7);`
120			`if bit_count < 7 then`
121			`state <= WRITE_DATA_1;`
122			`bit_count <= bit_count + 1;`
123			`else`
124			`state <= NEXT_TO_LAST_ONE;`
125			`bit_count <= 0;`
126			`end if;`
127
128			`when READ_DATA_1 =>`
129			`TEMP_SCLK <= '1';`
130			`TEMP_CE <= '1';`
131			`state <= READ_DATA_2;`
132
133			`when READ_DATA_2 =>`
134			`TEMP_SCLK <= '0';`
135			`TEMP_CE <= '1';`
136			`data_latch <= data_latch(6 downto 0) & TEMP_SPO;`
137			`if bit_count < 7 then`
138			`state <= READ_DATA_1;`
139			`bit_count <= bit_count + 1;`
140			`else`
141			`state <= NEXT_TO_LAST_ONE;`
142			`bit_count <= 0;`
143			`end if;`
144
145			`when NEXT_TO_LAST_ONE =>`
146			`TEMP_CE <= '0';`
147			`TEMP_SCLK <= '0';`
148			`state <= LAST_ONE;`
149
150			`when LAST_ONE =>`
151			`TEMP_CE <= '0';`
152			`TEMP_SCLK <= '0';`
153			`state <= SET_CE;`
154			`end case;`
155			`end if;`
156			`end if;`
157			`end if;`
158			`end process;`
159
160			`end DS1722_arch;`

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[/] [c16/] [trunk/] [vhdl/] [ds1722.vhd] - Blame information for rev 2