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[/] [c16/] [trunk/] [vhdl/] [ds1722.vhd] - Blame information for rev 31

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
entity DS1722 is
    Port(       CLK_I:      in          std_logic;
                        RST_I:      in          std_logic;
 
                        DATA_IN:        in      std_logic_vector(7 downto 0);
                        DATA_OUT:       out     std_logic_vector(7 downto 0);
                        ADDRESS:        in      std_logic_vector(7 downto 0);
 
                        START:          in      std_logic;
                        DONE:           out     std_logic;
 
                        TEMP_SPI:       out     STD_LOGIC;      -- Physical interfaes
                        TEMP_SPO:       in      STD_LOGIC;
                        TEMP_CE:        out     STD_LOGIC;
                        TEMP_SCLK:      out     STD_LOGIC
    );
end DS1722;
 
architecture DS1722_arch of DS1722 is
 
        signal counter    : std_logic_vector(7 downto 0);
        signal data_latch : std_logic_vector(7 downto 0);
 
type BIG_STATE is (     SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,
                                        DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,
                                        NEXT_TO_LAST_ONE, LAST_ONE);
 
        signal state : BIG_STATE;
 
        signal bit_count:  INTEGER range 0 to 7;
 
        signal Write: std_logic;
 
begin
 
        -- divide CLK_I by 256
        --
        process (CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (RST_I = '1') then   counter <= "00000000";
                        else                                    counter <= counter + "00000001";
                        end if;
                end if;
        end process;
 
        DONE     <= START when (state = LAST_ONE) else '0';
        DATA_OUT <= data_latch;
 
        Write <= ADDRESS(7);
 
        -- convert byte commands to SPI and SPI to byte.
        --
        process (CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (RST_I = '1') then
                                state     <= SET_CE;
                                TEMP_CE   <= '0';
                                TEMP_SCLK <= '0';
                                bit_count <= 0;
                        elsif (counter = "11111111" and START = '1') then
                                case state is
                                        when SET_CE =>
                                                TEMP_SCLK <= '0';
                                                TEMP_CE <= '1';
                                                state <= LATCH_ADD;
                                                bit_count <= 0;
 
                                        when LATCH_ADD =>
                                                TEMP_SCLK <= '0';
                                                TEMP_CE <= '1';
                                                state <= ADD_OUT_1;
                                                data_latch <= ADDRESS;
 
                                        when ADD_OUT_1 =>
                                                TEMP_SCLK <= '1';
                                                TEMP_CE <= '1';
                                                state <= ADD_OUT_2;
                                                TEMP_SPI <= data_latch(7);
 
                                        when ADD_OUT_2 =>
                                                TEMP_SCLK <= '0';
                                                TEMP_CE <= '1';
                                                data_latch <= data_latch(6 downto 0) & data_latch(7);
                                                if bit_count < 7 then
                                                        state <= ADD_OUT_1;
                                                        bit_count <= bit_count + 1;
                                                else
                                                        state <= DATA;
                                                        bit_count <= 0;
                                                end if;
 
                                        when DATA =>
                                                data_latch <= DATA_IN;
                                                TEMP_SCLK <= '0';
                                                TEMP_CE <= '1';
                                                if Write = '0' then
                                                        state <= READ_DATA_1;
                                                else
                                                        state <= WRITE_DATA_1;
                                                end if;
 
                                        when WRITE_DATA_1 =>
                                                TEMP_SCLK <= '1';
                                                TEMP_CE <= '1';
                                                state <= WRITE_DATA_2;
                                                TEMP_SPI <= data_latch(7);
 
                                        when WRITE_DATA_2 =>
                                                TEMP_SCLK <= '0';
                                                TEMP_CE <= '1';
                                                data_latch <=  data_latch(6 downto 0) & data_latch(7);
                                                if bit_count < 7 then
                                                        state <= WRITE_DATA_1;
                                                        bit_count <= bit_count + 1;
                                                else
                                                        state <= NEXT_TO_LAST_ONE;
                                                        bit_count <= 0;
                                                end if;
 
                                        when READ_DATA_1 =>
                                                TEMP_SCLK <= '1';
                                                TEMP_CE <= '1';
                                                state <= READ_DATA_2;
 
                                        when READ_DATA_2 =>
                                                TEMP_SCLK <= '0';
                                                TEMP_CE   <= '1';
                                                data_latch <= data_latch(6 downto 0) & TEMP_SPO;
                                                if bit_count < 7 then
                                                        state     <= READ_DATA_1;
                                                        bit_count <= bit_count + 1;
                                                else
                                                        state     <= NEXT_TO_LAST_ONE;
                                                        bit_count <= 0;
                                                end if;
 
                                        when NEXT_TO_LAST_ONE =>
                                                TEMP_CE   <= '0';
                                                TEMP_SCLK <= '0';
                                                state     <= LAST_ONE;
 
                                        when LAST_ONE =>
                                                TEMP_CE   <= '0';
                                                TEMP_SCLK <= '0';
                                                state     <= SET_CE;
                                end case;
                        end if;
                end if;
        end process;
 
end DS1722_arch;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3			`use IEEE.std_logic_unsigned.all;`
4
5			`entity DS1722 is`
6			`Port( CLK_I: in std_logic;`
7	9	jsauermann	`RST_I: in std_logic;`
8	2	jsauermann
9			`DATA_IN: in std_logic_vector(7 downto 0);`
10			`DATA_OUT: out std_logic_vector(7 downto 0);`
11			`ADDRESS: in std_logic_vector(7 downto 0);`
12
13			`START: in std_logic;`
14			`DONE: out std_logic;`
15
16			`TEMP_SPI: out STD_LOGIC; -- Physical interfaes`
17			`TEMP_SPO: in STD_LOGIC;`
18			`TEMP_CE: out STD_LOGIC;`
19			`TEMP_SCLK: out STD_LOGIC`
20			`);`
21			`end DS1722;`
22
23			`architecture DS1722_arch of DS1722 is`
24
25			`signal counter : std_logic_vector(7 downto 0);`
26			`signal data_latch : std_logic_vector(7 downto 0);`
27
28			`type BIG_STATE is ( SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,`
29			`DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,`
30			`NEXT_TO_LAST_ONE, LAST_ONE);`
31
32			`signal state : BIG_STATE;`
33
34			`signal bit_count: INTEGER range 0 to 7;`
35
36			`signal Write: std_logic;`
37
38			`begin`
39
40	9	jsauermann	`-- divide CLK_I by 256`
41			`--`
42			`process (CLK_I)`
43	2	jsauermann	`begin`
44	9	jsauermann	`if (rising_edge(CLK_I)) then`
45			`if (RST_I = '1') then counter <= "00000000";`
46			`else counter <= counter + "00000001";`
47	2	jsauermann	`end if;`
48			`end if;`
49			`end process;`
50
51			`DONE <= START when (state = LAST_ONE) else '0';`
52			`DATA_OUT <= data_latch;`
53
54			`Write <= ADDRESS(7);`
55
56	9	jsauermann	`-- convert byte commands to SPI and SPI to byte.`
57			`--`
58			`process (CLK_I)`
59	2	jsauermann	`begin`
60	9	jsauermann	`if (rising_edge(CLK_I)) then`
61			`if (RST_I = '1') then`
62			`state <= SET_CE;`
63			`TEMP_CE <= '0';`
64			`TEMP_SCLK <= '0';`
65			`bit_count <= 0;`
66			`elsif (counter = "11111111" and START = '1') then`
67			`case state is`
68			`when SET_CE =>`
69			`TEMP_SCLK <= '0';`
70			`TEMP_CE <= '1';`
71			`state <= LATCH_ADD;`
72			`bit_count <= 0;`
73	2	jsauermann
74	9	jsauermann	`when LATCH_ADD =>`
75			`TEMP_SCLK <= '0';`
76			`TEMP_CE <= '1';`
77			`state <= ADD_OUT_1;`
78			`data_latch <= ADDRESS;`
79	2	jsauermann
80	9	jsauermann	`when ADD_OUT_1 =>`
81			`TEMP_SCLK <= '1';`
82			`TEMP_CE <= '1';`
83			`state <= ADD_OUT_2;`
84			`TEMP_SPI <= data_latch(7);`
85	2	jsauermann
86	9	jsauermann	`when ADD_OUT_2 =>`
87			`TEMP_SCLK <= '0';`
88			`TEMP_CE <= '1';`
89			`data_latch <= data_latch(6 downto 0) & data_latch(7);`
90			`if bit_count < 7 then`
91			`state <= ADD_OUT_1;`
92			`bit_count <= bit_count + 1;`
93			`else`
94			`state <= DATA;`
95			`bit_count <= 0;`
96			`end if;`
97	2	jsauermann
98	9	jsauermann	`when DATA =>`
99			`data_latch <= DATA_IN;`
100			`TEMP_SCLK <= '0';`
101			`TEMP_CE <= '1';`
102			`if Write = '0' then`
103			`state <= READ_DATA_1;`
104			`else`
105			`state <= WRITE_DATA_1;`
106			`end if;`
107	2	jsauermann
108	9	jsauermann	`when WRITE_DATA_1 =>`
109			`TEMP_SCLK <= '1';`
110			`TEMP_CE <= '1';`
111			`state <= WRITE_DATA_2;`
112			`TEMP_SPI <= data_latch(7);`
113	2	jsauermann
114	9	jsauermann	`when WRITE_DATA_2 =>`
115			`TEMP_SCLK <= '0';`
116			`TEMP_CE <= '1';`
117			`data_latch <= data_latch(6 downto 0) & data_latch(7);`
118			`if bit_count < 7 then`
119			`state <= WRITE_DATA_1;`
120			`bit_count <= bit_count + 1;`
121			`else`
122			`state <= NEXT_TO_LAST_ONE;`
123			`bit_count <= 0;`
124			`end if;`
125	2	jsauermann
126	9	jsauermann	`when READ_DATA_1 =>`
127			`TEMP_SCLK <= '1';`
128			`TEMP_CE <= '1';`
129			`state <= READ_DATA_2;`
130
131			`when READ_DATA_2 =>`
132			`TEMP_SCLK <= '0';`
133			`TEMP_CE <= '1';`
134			`data_latch <= data_latch(6 downto 0) & TEMP_SPO;`
135			`if bit_count < 7 then`
136			`state <= READ_DATA_1;`
137			`bit_count <= bit_count + 1;`
138			`else`
139			`state <= NEXT_TO_LAST_ONE;`
140			`bit_count <= 0;`
141			`end if;`
142	2	jsauermann
143	9	jsauermann	`when NEXT_TO_LAST_ONE =>`
144			`TEMP_CE <= '0';`
145			`TEMP_SCLK <= '0';`
146			`state <= LAST_ONE;`
147	2	jsauermann
148	9	jsauermann	`when LAST_ONE =>`
149			`TEMP_CE <= '0';`
150			`TEMP_SCLK <= '0';`
151			`state <= SET_CE;`
152			`end case;`
153	2	jsauermann	`end if;`
154			`end if;`
155			`end process;`
156
157			`end DS1722_arch;`

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[/] [c16/] [trunk/] [vhdl/] [ds1722.vhd] - Blame information for rev 31