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[/] [c16/] [trunk/] [vhdl/] [input_output.vhd] - Blame information for rev 2

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity input_output is
    PORT (      CLK_I                   : in std_logic;
                        T2                              : in std_logic;
                        SWITCH                  : in  STD_LOGIC_VECTOR (9 downto 0);
 
                        HALT                    : in  STD_LOGIC;
                        SER_IN                  : in  STD_LOGIC;
                        SER_OUT                 : out STD_LOGIC;
 
                        -- temperature
                        TEMP_SPO                : in  STD_LOGIC;
                        TEMP_SPI                : out STD_LOGIC;
                        TEMP_CE                 : out STD_LOGIC;
                        TEMP_SCLK               : out STD_LOGIC;
 
                    LED                         : out STD_LOGIC_VECTOR (7 downto 0);
 
                        CLR                             : out STD_LOGIC;
 
                        -- input/output
                        IO_RD    : in  std_logic;
                        IO_WR    : in  std_logic;
                        IO_ADR   : in  std_logic_vector( 7 downto 0);
                        IO_RDAT  : out std_logic_vector( 7 downto 0);
                        IO_WDAT  : in  std_logic_vector( 7 downto 0);
                    INT      : out STD_LOGIC
        );
end input_output;
 
architecture Behavioral of input_output is
 
        COMPONENT temperature
        PORT(   CLK_I     : IN std_logic;
                        T2        : IN std_logic;
                        CLR       : IN std_logic;
                        TEMP_SPO  : IN std_logic;
                        DATA_OUT  : OUT std_logic_vector(7 downto 0);
                        TEMP_SPI  : OUT std_logic;
                        TEMP_CE   : OUT std_logic;
                        TEMP_SCLK : OUT std_logic
                );
        END COMPONENT;
 
        COMPONENT uart_baudgen
        PORT(   CLK_I     : IN std_logic;
                        T2        : IN std_logic;
                        CLR       : IN std_logic;
                        RD        : IN std_logic;
                        WR        : IN std_logic;
                        TX_DATA   : IN std_logic_vector(7 downto 0);
                        RX_SERIN  : IN std_logic;
                        TX_SEROUT : OUT std_logic;
                        RX_DATA   : OUT std_logic_vector(7 downto 0);
                        RX_READY  : OUT std_logic;
                        TX_BUSY   : OUT std_logic
                );
        END COMPONENT;
 
        signal L_IO_ADR        : std_logic_vector(7 downto 0);
        signal IO_RD_SERIAL    : std_logic;
        signal IO_WR_SERIAL    : std_logic;
        signal RX_READY        : std_logic;
        signal TX_BUSY         : std_logic;
        signal RX_DATA         : std_logic_vector(7 downto 0);
        signal TEMP_DO         : std_logic_vector(7 downto 0);
 
        signal FLAG            : std_logic;
 
        signal LCLR            : std_logic;
        signal C1_N, C2_N      : std_logic;             -- switch debounce, active low
 
        signal RX_INT_ENABLED  : std_logic;
        signal TX_INT_ENABLED  : std_logic;
        signal TIM_INT_ENABLED : std_logic;
        signal TIMER_INT       : std_logic;
        signal TIMER           : std_logic_vector(14 downto 0);
        signal CLK_COUNT       : std_logic_vector(15 downto 0);
 
        signal CLK_COUNT_EN    : std_logic;
        signal CLK_HALT_MSK    : std_logic;
        signal CLK_HALT_VAL    : std_logic;
 
begin
 
        tempr: temperature
        PORT MAP(       CLK_I     => CLK_I,
                                T2        => T2,
                                CLR       => LCLR,
                                DATA_OUT  => TEMP_DO,
                                TEMP_SPI  => TEMP_SPI,
                                TEMP_SPO  => TEMP_SPO,
                                TEMP_CE   => TEMP_CE,
                                TEMP_SCLK => TEMP_SCLK
        );
 
        uart: uart_baudgen
        PORT MAP(       CLK_I     => CLK_I,
                                T2        => T2,
                                CLR       => LCLR,
                                RD        => IO_RD_SERIAL,
                                WR        => IO_WR_SERIAL,
                                TX_DATA   => IO_WDAT,
                                TX_SEROUT => SER_OUT,
                                RX_SERIN  => SER_IN,
                                RX_DATA   => RX_DATA,
                                RX_READY  => RX_READY,
                                TX_BUSY   => TX_BUSY
        );
 
        CLR     <= LCLR;
        INT     <=     (RX_INT_ENABLED  and     RX_READY)
                                or (TX_INT_ENABLED  and not TX_BUSY)
                                or (TIM_INT_ENABLED and     TIMER_INT);
 
        -- IO read process
        --
        process(L_IO_ADR, IO_RD, IO_WR, RX_DATA, TEMP_DO, SWITCH,
                        TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,
                        RX_INT_ENABLED, RX_READY)
        begin
                IO_RD_SERIAL <= '0';
                IO_WR_SERIAL <= '0';
                case L_IO_ADR is
                        when X"00"      =>      IO_RDAT      <= RX_DATA;
                                                        IO_RD_SERIAL <= IO_RD;
                                                        IO_WR_SERIAL <= IO_WR;
                        when X"01"      =>      IO_RDAT <= '0'
                                                                         & (TIM_INT_ENABLED and  TIMER_INT)
                                                                         & (TX_INT_ENABLED  and not TX_BUSY)
                                                                         & (RX_INT_ENABLED  and RX_READY)
                                                                         & '0'
                                                                         & TIMER_INT
                                                                         & TX_BUSY
                                                                         & RX_READY;
                        when X"02"      => IO_RDAT  <= TEMP_DO;
                        when X"03"      => IO_RDAT  <= SWITCH(7 downto 0);
                        when X"05"      => IO_RDAT  <= CLK_COUNT(7 downto 0);
                        when others     => IO_RDAT  <= CLK_COUNT(15 downto 8);
                end case;
        end process;
 
        -- IO write and timer process
        --
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (T2 = '1') then
                                L_IO_ADR <= IO_ADR;
                                if (LCLR = '1') then
                                        LED             <= X"00";
                                        RX_INT_ENABLED  <= '0';
                                        TX_INT_ENABLED  <= '0';
                                        TIM_INT_ENABLED <= '0';
                                        TIMER_INT       <= '0';
                                        TIMER           <= "000" & X"000";
                                else
                                        if (IO_WR = '1') then
                                                case L_IO_ADR is
                                                        when X"00"  =>  -- handled by uart
                                                        when X"01"  =>  -- handled by uart
                                                        when X"02"  => LED <= IO_WDAT;
                                                        when X"03"  =>  RX_INT_ENABLED  <= IO_WDAT(0);
                                                                                        TX_INT_ENABLED  <= IO_WDAT(1);
                                                                                        TIM_INT_ENABLED <= IO_WDAT(2);
                                                        when X"04"  =>  TIMER_INT       <= '0';
                                                        when X"05"  =>  CLK_COUNT_EN    <= '1';
                                                                        CLK_COUNT       <= X"0000";
                                                                                        CLK_HALT_VAL    <= IO_WDAT(0);
                                                                                        CLK_HALT_MSK    <= IO_WDAT(1);
                                                        when X"06"  =>  CLK_COUNT_EN    <= '0';
                                                        when others =>
                                                end case;
                                        end if;
 
                                        TIMER <= TIMER + 1;
                                        if (TIMER = 19999) then         -- 1 ms
                                                TIMER_INT <= '1';
                                                TIMER     <= "000" & X"000";
                                        end if;
 
                                        if (CLK_COUNT_EN = '1' and
                                            (HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then
                                                CLK_COUNT <= CLK_COUNT + 1;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        -- reset debounce process
        --
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (T2 = '1') then
                                -- switch debounce
                                if (SWITCH(8) = '1' or SWITCH(9) = '1') then
                                        LCLR <= '1';
                                        C2_N <= '0';
                                        C1_N <= '0';
                                else
                                        LCLR <= not C2_N;
                                        C2_N   <= C1_N;
                                        C1_N   <= '1';
                                end if;
                        end if;
                end if;
        end process;
 
end Behavioral;

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[/] [c16/] [trunk/] [vhdl/] [input_output.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`-- Uncomment the following lines to use the declarations that are`
7			`-- provided for instantiating Xilinx primitive components.`
8			`--library UNISIM;`
9			`--use UNISIM.VComponents.all;`
10
11			`use work.cpu_pack.ALL;`
12
13			`entity input_output is`
14			`PORT ( CLK_I : in std_logic;`
15			`T2 : in std_logic;`
16			`SWITCH : in STD_LOGIC_VECTOR (9 downto 0);`
17
18			`HALT : in STD_LOGIC;`
19			`SER_IN : in STD_LOGIC;`
20			`SER_OUT : out STD_LOGIC;`
21
22			`-- temperature`
23			`TEMP_SPO : in STD_LOGIC;`
24			`TEMP_SPI : out STD_LOGIC;`
25			`TEMP_CE : out STD_LOGIC;`
26			`TEMP_SCLK : out STD_LOGIC;`
27
28			`LED : out STD_LOGIC_VECTOR (7 downto 0);`
29
30			`CLR : out STD_LOGIC;`
31
32			`-- input/output`
33			`IO_RD : in std_logic;`
34			`IO_WR : in std_logic;`
35			`IO_ADR : in std_logic_vector( 7 downto 0);`
36			`IO_RDAT : out std_logic_vector( 7 downto 0);`
37			`IO_WDAT : in std_logic_vector( 7 downto 0);`
38			`INT : out STD_LOGIC`
39			`);`
40			`end input_output;`
41
42			`architecture Behavioral of input_output is`
43
44			`COMPONENT temperature`
45			`PORT( CLK_I : IN std_logic;`
46			`T2 : IN std_logic;`
47			`CLR : IN std_logic;`
48			`TEMP_SPO : IN std_logic;`
49			`DATA_OUT : OUT std_logic_vector(7 downto 0);`
50			`TEMP_SPI : OUT std_logic;`
51			`TEMP_CE : OUT std_logic;`
52			`TEMP_SCLK : OUT std_logic`
53			`);`
54			`END COMPONENT;`
55
56			`COMPONENT uart_baudgen`
57			`PORT( CLK_I : IN std_logic;`
58			`T2 : IN std_logic;`
59			`CLR : IN std_logic;`
60			`RD : IN std_logic;`
61			`WR : IN std_logic;`
62			`TX_DATA : IN std_logic_vector(7 downto 0);`
63			`RX_SERIN : IN std_logic;`
64			`TX_SEROUT : OUT std_logic;`
65			`RX_DATA : OUT std_logic_vector(7 downto 0);`
66			`RX_READY : OUT std_logic;`
67			`TX_BUSY : OUT std_logic`
68			`);`
69			`END COMPONENT;`
70
71			`signal L_IO_ADR : std_logic_vector(7 downto 0);`
72			`signal IO_RD_SERIAL : std_logic;`
73			`signal IO_WR_SERIAL : std_logic;`
74			`signal RX_READY : std_logic;`
75			`signal TX_BUSY : std_logic;`
76			`signal RX_DATA : std_logic_vector(7 downto 0);`
77			`signal TEMP_DO : std_logic_vector(7 downto 0);`
78
79			`signal FLAG : std_logic;`
80
81			`signal LCLR : std_logic;`
82			`signal C1_N, C2_N : std_logic; -- switch debounce, active low`
83
84			`signal RX_INT_ENABLED : std_logic;`
85			`signal TX_INT_ENABLED : std_logic;`
86			`signal TIM_INT_ENABLED : std_logic;`
87			`signal TIMER_INT : std_logic;`
88			`signal TIMER : std_logic_vector(14 downto 0);`
89			`signal CLK_COUNT : std_logic_vector(15 downto 0);`
90
91			`signal CLK_COUNT_EN : std_logic;`
92			`signal CLK_HALT_MSK : std_logic;`
93			`signal CLK_HALT_VAL : std_logic;`
94
95			`begin`
96
97			`tempr: temperature`
98			`PORT MAP( CLK_I => CLK_I,`
99			`T2 => T2,`
100			`CLR => LCLR,`
101			`DATA_OUT => TEMP_DO,`
102			`TEMP_SPI => TEMP_SPI,`
103			`TEMP_SPO => TEMP_SPO,`
104			`TEMP_CE => TEMP_CE,`
105			`TEMP_SCLK => TEMP_SCLK`
106			`);`
107
108			`uart: uart_baudgen`
109			`PORT MAP( CLK_I => CLK_I,`
110			`T2 => T2,`
111			`CLR => LCLR,`
112			`RD => IO_RD_SERIAL,`
113			`WR => IO_WR_SERIAL,`
114			`TX_DATA => IO_WDAT,`
115			`TX_SEROUT => SER_OUT,`
116			`RX_SERIN => SER_IN,`
117			`RX_DATA => RX_DATA,`
118			`RX_READY => RX_READY,`
119			`TX_BUSY => TX_BUSY`
120			`);`
121
122			`CLR <= LCLR;`
123			`INT <= (RX_INT_ENABLED and RX_READY)`
124			`or (TX_INT_ENABLED and not TX_BUSY)`
125			`or (TIM_INT_ENABLED and TIMER_INT);`
126
127			`-- IO read process`
128			`--`
129			`process(L_IO_ADR, IO_RD, IO_WR, RX_DATA, TEMP_DO, SWITCH,`
130			`TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,`
131			`RX_INT_ENABLED, RX_READY)`
132			`begin`
133			`IO_RD_SERIAL <= '0';`
134			`IO_WR_SERIAL <= '0';`
135			`case L_IO_ADR is`
136			`when X"00" => IO_RDAT <= RX_DATA;`
137			`IO_RD_SERIAL <= IO_RD;`
138			`IO_WR_SERIAL <= IO_WR;`
139			`when X"01" => IO_RDAT <= '0'`
140			`& (TIM_INT_ENABLED and TIMER_INT)`
141			`& (TX_INT_ENABLED and not TX_BUSY)`
142			`& (RX_INT_ENABLED and RX_READY)`
143			`& '0'`
144			`& TIMER_INT`
145			`& TX_BUSY`
146			`& RX_READY;`
147			`when X"02" => IO_RDAT <= TEMP_DO;`
148			`when X"03" => IO_RDAT <= SWITCH(7 downto 0);`
149			`when X"05" => IO_RDAT <= CLK_COUNT(7 downto 0);`
150			`when others => IO_RDAT <= CLK_COUNT(15 downto 8);`
151			`end case;`
152			`end process;`
153
154			`-- IO write and timer process`
155			`--`
156			`process(CLK_I)`
157			`begin`
158			`if (rising_edge(CLK_I)) then`
159			`if (T2 = '1') then`
160			`L_IO_ADR <= IO_ADR;`
161			`if (LCLR = '1') then`
162			`LED <= X"00";`
163			`RX_INT_ENABLED <= '0';`
164			`TX_INT_ENABLED <= '0';`
165			`TIM_INT_ENABLED <= '0';`
166			`TIMER_INT <= '0';`
167			`TIMER <= "000" & X"000";`
168			`else`
169			`if (IO_WR = '1') then`
170			`case L_IO_ADR is`
171			`when X"00" => -- handled by uart`
172			`when X"01" => -- handled by uart`
173			`when X"02" => LED <= IO_WDAT;`
174			`when X"03" => RX_INT_ENABLED <= IO_WDAT(0);`
175			`TX_INT_ENABLED <= IO_WDAT(1);`
176			`TIM_INT_ENABLED <= IO_WDAT(2);`
177			`when X"04" => TIMER_INT <= '0';`
178			`when X"05" => CLK_COUNT_EN <= '1';`
179			`CLK_COUNT <= X"0000";`
180			`CLK_HALT_VAL <= IO_WDAT(0);`
181			`CLK_HALT_MSK <= IO_WDAT(1);`
182			`when X"06" => CLK_COUNT_EN <= '0';`
183			`when others =>`
184			`end case;`
185			`end if;`
186
187			`TIMER <= TIMER + 1;`
188			`if (TIMER = 19999) then -- 1 ms`
189			`TIMER_INT <= '1';`
190			`TIMER <= "000" & X"000";`
191			`end if;`
192
193			`if (CLK_COUNT_EN = '1' and`
194			`(HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then`
195			`CLK_COUNT <= CLK_COUNT + 1;`
196			`end if;`
197			`end if;`
198			`end if;`
199			`end if;`
200			`end process;`
201
202			`-- reset debounce process`
203			`--`
204			`process(CLK_I)`
205			`begin`
206			`if (rising_edge(CLK_I)) then`
207			`if (T2 = '1') then`
208			`-- switch debounce`
209			`if (SWITCH(8) = '1' or SWITCH(9) = '1') then`
210			`LCLR <= '1';`
211			`C2_N <= '0';`
212			`C1_N <= '0';`
213			`else`
214			`LCLR <= not C2_N;`
215			`C2_N <= C1_N;`
216			`C1_N <= '1';`
217			`end if;`
218			`end if;`
219			`end if;`
220			`end process;`
221
222			`end Behavioral;`