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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity input_output is
    PORT (      CLK_I                   : in std_logic;
                        ADR_I                   : in  std_logic_vector( 7 downto 0);
                        CYC_I                   : in  std_logic;
                        STB_I                   : in  std_logic;
                        ACK_O                   : out std_logic;
 
                        RST_O                   : out STD_LOGIC;
 
                        SWITCH                  : in  STD_LOGIC_VECTOR (9 downto 0);
 
                        HALT                    : in  STD_LOGIC;
                        SER_IN                  : in  STD_LOGIC;
                        SER_OUT                 : out STD_LOGIC;
 
                        -- temperature
                        TEMP_SPO                : in  STD_LOGIC;
                        TEMP_SPI                : out STD_LOGIC;
                        TEMP_CE                 : out STD_LOGIC;
                        TEMP_SCLK               : out STD_LOGIC;
 
                    LED                         : out STD_LOGIC_VECTOR (7 downto 0);
 
                        -- input/output
                        IO       : in  std_logic;
                        WE_I     : in  std_logic;
                        IO_RDAT  : out std_logic_vector( 7 downto 0);
                        IO_WDAT  : in  std_logic_vector( 7 downto 0);
                    INT      : out STD_LOGIC
        );
end input_output;
 
architecture Behavioral of input_output is
 
        COMPONENT temperature
        PORT(   CLK_I     : IN std_logic;
                        RST_I     : IN std_logic;
                        TEMP_SPO  : IN std_logic;
                        DATA_OUT  : OUT std_logic_vector(7 downto 0);
                        TEMP_SPI  : OUT std_logic;
                        TEMP_CE   : OUT std_logic;
                        TEMP_SCLK : OUT std_logic
                );
        END COMPONENT;
 
        COMPONENT uart_baudgen
        PORT(   CLK_I     : IN std_logic;
                        RST_I     : IN std_logic;
                        RD        : IN std_logic;
                        WR        : IN std_logic;
                        TX_DATA   : IN std_logic_vector(7 downto 0);
                        RX_SERIN  : IN std_logic;
                        TX_SEROUT : OUT std_logic;
                        RX_DATA   : OUT std_logic_vector(7 downto 0);
                        RX_READY  : OUT std_logic;
                        TX_BUSY   : OUT std_logic
                );
        END COMPONENT;
 
        signal IO_RD_SERIAL    : std_logic;
        signal IO_WR_SERIAL    : std_logic;
        signal RX_READY        : std_logic;
        signal TX_BUSY         : std_logic;
        signal RX_DATA         : std_logic_vector(7 downto 0);
        signal TEMP_DO         : std_logic_vector(7 downto 0);
 
        signal SERDAT          : std_logic;
 
        signal LCLR            : std_logic;
        signal C1_N, C2_N      : std_logic;             -- switch debounce, active low
 
        signal RX_INT_ENABLED  : std_logic;
        signal TX_INT_ENABLED  : std_logic;
        signal TIM_INT_ENABLED : std_logic;
        signal TIMER_INT       : std_logic;
        signal TIMER           : std_logic_vector(15 downto 0);
        signal CLK_COUNT       : std_logic_vector(16 downto 0);
 
        signal CLK_COUNT_EN    : std_logic;
        signal CLK_HALT_MSK    : std_logic;
        signal CLK_HALT_VAL    : std_logic;
 
begin
 
        tempr: temperature
        PORT MAP(       CLK_I     => CLK_I,
                                RST_I     => LCLR,
                                DATA_OUT  => TEMP_DO,
                                TEMP_SPI  => TEMP_SPI,
                                TEMP_SPO  => TEMP_SPO,
                                TEMP_CE   => TEMP_CE,
                                TEMP_SCLK => TEMP_SCLK
        );
 
        uart: uart_baudgen
        PORT MAP(       CLK_I     => CLK_I,
                                RST_I     => LCLR,
                                RD        => IO_RD_SERIAL,
                                WR        => IO_WR_SERIAL,
                                TX_DATA   => IO_WDAT,
                                TX_SEROUT => SER_OUT,
                                RX_SERIN  => SER_IN,
                                RX_DATA   => RX_DATA,
                                RX_READY  => RX_READY,
                                TX_BUSY   => TX_BUSY
        );
 
        RST_O   <= LCLR;
        INT     <=     (RX_INT_ENABLED  and     RX_READY)
                                or (TX_INT_ENABLED  and not TX_BUSY)
                                or (TIM_INT_ENABLED and     TIMER_INT);
 
        SERDAT       <= (IO and CYC_I) when (ADR_I = X"00") else '0';
        IO_RD_SERIAL <= SERDAT and not WE_I;
        IO_WR_SERIAL <= SERDAT and WE_I;
        ACK_O        <= STB_I;
 
        -- IO read process
        --
        process(ADR_I, RX_DATA, TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,
                        RX_INT_ENABLED,  RX_READY, TEMP_DO, SWITCH, CLK_COUNT)
        begin
                case ADR_I is
                        when X"00"      =>      IO_RDAT <= RX_DATA;
                        when X"01"      =>      IO_RDAT <= '0'
                                                                         & (TIM_INT_ENABLED and  TIMER_INT)
                                                                         & (TX_INT_ENABLED  and not TX_BUSY)
                                                                         & (RX_INT_ENABLED  and RX_READY)
                                                                         & '0'
                                                                         & TIMER_INT
                                                                         & TX_BUSY
                                                                         & RX_READY;
                        when X"02"      => IO_RDAT  <= TEMP_DO;
                        when X"03"      => IO_RDAT  <= SWITCH(7 downto 0);
                        when X"05"      => IO_RDAT  <= CLK_COUNT(8 downto 1);
                        when others     => IO_RDAT  <= CLK_COUNT(16 downto 9);
                end case;
        end process;
 
        -- IO write and timer process
        --
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (LCLR = '1') then
                                LED             <= X"00";
                                RX_INT_ENABLED  <= '0';
                                TX_INT_ENABLED  <= '0';
                                TIM_INT_ENABLED <= '0';
                                TIMER_INT       <= '0';
                                TIMER           <= X"0000";
                        else
                                if (IO = '1' and CYC_I = '1' and WE_I = '1') then
                                        case ADR_I is
                                                when X"00"  =>  -- handled by uart
                                                when X"01"  =>  -- handled by uart
                                                when X"02"  =>  LED             <= IO_WDAT;
                                                when X"03"  =>  RX_INT_ENABLED  <= IO_WDAT(0);
                                                                                TX_INT_ENABLED  <= IO_WDAT(1);
                                                                                TIM_INT_ENABLED <= IO_WDAT(2);
                                                when X"04"  =>  TIMER_INT       <= '0';
                                                when X"05"  =>  CLK_COUNT_EN    <= '1';
                                                                CLK_COUNT       <= '0' & X"0000";
                                                                                CLK_HALT_VAL    <= IO_WDAT(0);
                                                                                CLK_HALT_MSK    <= IO_WDAT(1);
                                                when X"06"  =>  CLK_COUNT_EN    <= '0';
                                                when others =>
                                        end case;
                                end if;
 
                                if (TIMER = 39999) then         -- 1 ms at 40 MHz
                                        TIMER_INT <= '1';
                                        TIMER     <= X"0000";
                                else
                                        TIMER <= TIMER + 1;
                                end if;
 
                                if (CLK_COUNT_EN = '1' and
                                    (HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then
                                        CLK_COUNT <= CLK_COUNT + 1;
                                end if;
                        end if;
                end if;
        end process;
 
        -- reset debounce process
        --
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        -- switch debounce
                        if (SWITCH(8) = '1' or SWITCH(9) = '1') then
                                LCLR <= '1';
                                C2_N <= '0';
                                C1_N <= '0';
                        else
                                LCLR <= not C2_N;
                                C2_N   <= C1_N;
                                C1_N   <= '1';
                        end if;
                end if;
        end process;
 
end Behavioral;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`-- Uncomment the following lines to use the declarations that are`
7			`-- provided for instantiating Xilinx primitive components.`
8			`--library UNISIM;`
9			`--use UNISIM.VComponents.all;`
10
11			`use work.cpu_pack.ALL;`
12
13			`entity input_output is`
14			`PORT ( CLK_I : in std_logic;`
15	9	jsauermann	`ADR_I : in std_logic_vector( 7 downto 0);`
16			`CYC_I : in std_logic;`
17			`STB_I : in std_logic;`
18			`ACK_O : out std_logic;`
19
20			`RST_O : out STD_LOGIC;`
21
22	2	jsauermann	`SWITCH : in STD_LOGIC_VECTOR (9 downto 0);`
23
24			`HALT : in STD_LOGIC;`
25			`SER_IN : in STD_LOGIC;`
26			`SER_OUT : out STD_LOGIC;`
27
28			`-- temperature`
29			`TEMP_SPO : in STD_LOGIC;`
30			`TEMP_SPI : out STD_LOGIC;`
31			`TEMP_CE : out STD_LOGIC;`
32			`TEMP_SCLK : out STD_LOGIC;`
33
34			`LED : out STD_LOGIC_VECTOR (7 downto 0);`
35
36			`-- input/output`
37	9	jsauermann	`IO : in std_logic;`
38			`WE_I : in std_logic;`
39	2	jsauermann	`IO_RDAT : out std_logic_vector( 7 downto 0);`
40			`IO_WDAT : in std_logic_vector( 7 downto 0);`
41			`INT : out STD_LOGIC`
42			`);`
43			`end input_output;`
44
45			`architecture Behavioral of input_output is`
46
47			`COMPONENT temperature`
48			`PORT( CLK_I : IN std_logic;`
49	9	jsauermann	`RST_I : IN std_logic;`
50	2	jsauermann	`TEMP_SPO : IN std_logic;`
51			`DATA_OUT : OUT std_logic_vector(7 downto 0);`
52			`TEMP_SPI : OUT std_logic;`
53			`TEMP_CE : OUT std_logic;`
54			`TEMP_SCLK : OUT std_logic`
55			`);`
56			`END COMPONENT;`
57
58			`COMPONENT uart_baudgen`
59			`PORT( CLK_I : IN std_logic;`
60	9	jsauermann	`RST_I : IN std_logic;`
61	2	jsauermann	`RD : IN std_logic;`
62			`WR : IN std_logic;`
63			`TX_DATA : IN std_logic_vector(7 downto 0);`
64			`RX_SERIN : IN std_logic;`
65			`TX_SEROUT : OUT std_logic;`
66			`RX_DATA : OUT std_logic_vector(7 downto 0);`
67			`RX_READY : OUT std_logic;`
68			`TX_BUSY : OUT std_logic`
69			`);`
70			`END COMPONENT;`
71
72			`signal IO_RD_SERIAL : std_logic;`
73			`signal IO_WR_SERIAL : std_logic;`
74			`signal RX_READY : std_logic;`
75			`signal TX_BUSY : std_logic;`
76			`signal RX_DATA : std_logic_vector(7 downto 0);`
77			`signal TEMP_DO : std_logic_vector(7 downto 0);`
78
79	9	jsauermann	`signal SERDAT : std_logic;`
80	2	jsauermann
81			`signal LCLR : std_logic;`
82			`signal C1_N, C2_N : std_logic; -- switch debounce, active low`
83
84			`signal RX_INT_ENABLED : std_logic;`
85			`signal TX_INT_ENABLED : std_logic;`
86			`signal TIM_INT_ENABLED : std_logic;`
87			`signal TIMER_INT : std_logic;`
88	9	jsauermann	`signal TIMER : std_logic_vector(15 downto 0);`
89			`signal CLK_COUNT : std_logic_vector(16 downto 0);`
90	2	jsauermann
91			`signal CLK_COUNT_EN : std_logic;`
92			`signal CLK_HALT_MSK : std_logic;`
93			`signal CLK_HALT_VAL : std_logic;`
94
95			`begin`
96
97			`tempr: temperature`
98			`PORT MAP( CLK_I => CLK_I,`
99	9	jsauermann	`RST_I => LCLR,`
100	2	jsauermann	`DATA_OUT => TEMP_DO,`
101			`TEMP_SPI => TEMP_SPI,`
102			`TEMP_SPO => TEMP_SPO,`
103			`TEMP_CE => TEMP_CE,`
104			`TEMP_SCLK => TEMP_SCLK`
105			`);`
106
107			`uart: uart_baudgen`
108			`PORT MAP( CLK_I => CLK_I,`
109	9	jsauermann	`RST_I => LCLR,`
110	2	jsauermann	`RD => IO_RD_SERIAL,`
111			`WR => IO_WR_SERIAL,`
112			`TX_DATA => IO_WDAT,`
113			`TX_SEROUT => SER_OUT,`
114			`RX_SERIN => SER_IN,`
115			`RX_DATA => RX_DATA,`
116			`RX_READY => RX_READY,`
117			`TX_BUSY => TX_BUSY`
118			`);`
119
120	9	jsauermann	`RST_O <= LCLR;`
121	2	jsauermann	`INT <= (RX_INT_ENABLED and RX_READY)`
122			`or (TX_INT_ENABLED and not TX_BUSY)`
123			`or (TIM_INT_ENABLED and TIMER_INT);`
124
125	9	jsauermann	`SERDAT <= (IO and CYC_I) when (ADR_I = X"00") else '0';`
126			`IO_RD_SERIAL <= SERDAT and not WE_I;`
127			`IO_WR_SERIAL <= SERDAT and WE_I;`
128			`ACK_O <= STB_I;`
129
130	2	jsauermann	`-- IO read process`
131			`--`
132	9	jsauermann	`process(ADR_I, RX_DATA, TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,`
133			`RX_INT_ENABLED, RX_READY, TEMP_DO, SWITCH, CLK_COUNT)`
134	2	jsauermann	`begin`
135	9	jsauermann	`case ADR_I is`
136			`when X"00" => IO_RDAT <= RX_DATA;`
137	2	jsauermann	`when X"01" => IO_RDAT <= '0'`
138			`& (TIM_INT_ENABLED and TIMER_INT)`
139			`& (TX_INT_ENABLED and not TX_BUSY)`
140			`& (RX_INT_ENABLED and RX_READY)`
141			`& '0'`
142			`& TIMER_INT`
143			`& TX_BUSY`
144			`& RX_READY;`
145			`when X"02" => IO_RDAT <= TEMP_DO;`
146			`when X"03" => IO_RDAT <= SWITCH(7 downto 0);`
147	9	jsauermann	`when X"05" => IO_RDAT <= CLK_COUNT(8 downto 1);`
148			`when others => IO_RDAT <= CLK_COUNT(16 downto 9);`
149	2	jsauermann	`end case;`
150			`end process;`
151
152			`-- IO write and timer process`
153			`--`
154			`process(CLK_I)`
155			`begin`
156			`if (rising_edge(CLK_I)) then`
157	9	jsauermann	`if (LCLR = '1') then`
158			`LED <= X"00";`
159			`RX_INT_ENABLED <= '0';`
160			`TX_INT_ENABLED <= '0';`
161			`TIM_INT_ENABLED <= '0';`
162			`TIMER_INT <= '0';`
163			`TIMER <= X"0000";`
164			`else`
165			`if (IO = '1' and CYC_I = '1' and WE_I = '1') then`
166			`case ADR_I is`
167			`when X"00" => -- handled by uart`
168			`when X"01" => -- handled by uart`
169			`when X"02" => LED <= IO_WDAT;`
170			`when X"03" => RX_INT_ENABLED <= IO_WDAT(0);`
171			`TX_INT_ENABLED <= IO_WDAT(1);`
172			`TIM_INT_ENABLED <= IO_WDAT(2);`
173			`when X"04" => TIMER_INT <= '0';`
174			`when X"05" => CLK_COUNT_EN <= '1';`
175			`CLK_COUNT <= '0' & X"0000";`
176			`CLK_HALT_VAL <= IO_WDAT(0);`
177			`CLK_HALT_MSK <= IO_WDAT(1);`
178			`when X"06" => CLK_COUNT_EN <= '0';`
179			`when others =>`
180			`end case;`
181			`end if;`
182
183			`if (TIMER = 39999) then -- 1 ms at 40 MHz`
184			`TIMER_INT <= '1';`
185			`TIMER <= X"0000";`
186	2	jsauermann	`else`
187			`TIMER <= TIMER + 1;`
188	9	jsauermann	`end if;`
189	2	jsauermann
190	9	jsauermann	`if (CLK_COUNT_EN = '1' and`
191			`(HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then`
192			`CLK_COUNT <= CLK_COUNT + 1;`
193	2	jsauermann	`end if;`
194			`end if;`
195			`end if;`
196			`end process;`
197
198			`-- reset debounce process`
199			`--`
200			`process(CLK_I)`
201			`begin`
202			`if (rising_edge(CLK_I)) then`
203	9	jsauermann	`-- switch debounce`
204			`if (SWITCH(8) = '1' or SWITCH(9) = '1') then`
205			`LCLR <= '1';`
206			`C2_N <= '0';`
207			`C1_N <= '0';`
208			`else`
209			`LCLR <= not C2_N;`
210			`C2_N <= C1_N;`
211			`C1_N <= '1';`
212	2	jsauermann	`end if;`
213			`end if;`
214			`end process;`
215
216			`end Behavioral;`

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[/] [c16/] [trunk/] [vhdl/] [input_output.vhd] - Blame information for rev 31