URL https://opencores.org/ocsvn/c16/c16/trunk

Subversion Repositories c16

[/] [c16/] [trunk/] [vhdl/] [memory.vhd] - Blame information for rev 33

Go to most recent revision | Details | Compare with Previous | View Log


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
use work.mem_content.All;
 
entity memory is
        Port (  CLK_I   : in  std_logic;
                        T2              : in  std_logic;
                        CE              : in  std_logic;
                        PC              : in  std_logic_vector(15 downto 0);
                        ADR             : in  std_logic_vector(15 downto 0);
                        WR              : in  std_logic;
                        WDAT    : in  std_logic_vector( 7 downto 0);
 
                        OPC             : out std_logic_vector( 7 downto 0);
                        RDAT    : out std_logic_vector( 7 downto 0)
                );
end memory;
 
architecture Behavioral of memory is
 
        signal ENA     : std_logic;
        signal ENB     : std_logic;
 
        signal WR_0    : std_logic;
        signal WR_1    : std_logic;
 
        signal LADR    : std_logic_vector( 3 downto 0);
        signal OUT_0   : std_logic_vector( 7 downto 0);
        signal OUT_1   : std_logic_vector( 7 downto 0);
 
        signal LPC     : std_logic_vector( 3 downto 0);
        signal OPC_0   : std_logic_vector( 7 downto 0);
        signal OPC_1   : std_logic_vector( 7 downto 0);
 
begin
 
        ENA   <= CE and not T2;
        ENB   <= CE and     T2;
 
        WR_0  <= '1' when (WR = '1' and ADR(15 downto 12) = "0000"  ) else '0';
        WR_1  <= '1' when (WR = '1' and ADR(15 downto 12) = "0001"  ) else '0';
 
        -- Bank 0 ------------------------------------------------------------------------
        --
        m_0_0 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_0_0_0, INIT_01 => m_0_0_1, INIT_02 => m_0_0_2, INIT_03 => m_0_0_3,
        INIT_04 => m_0_0_4, INIT_05 => m_0_0_5, INIT_06 => m_0_0_6, INIT_07 => m_0_0_7,
        INIT_08 => m_0_0_8, INIT_09 => m_0_0_9, INIT_0A => m_0_0_A, INIT_0B => m_0_0_B,
        INIT_0C => m_0_0_C, INIT_0D => m_0_0_D, INIT_0E => m_0_0_E, INIT_0F => m_0_0_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(0 downto 0),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_0,
                                DOA   => OPC_0(0 downto 0),               DOB   => OUT_0(0 downto 0)
                        );
 
        m_0_1 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_0_1_0, INIT_01 => m_0_1_1, INIT_02 => m_0_1_2, INIT_03 => m_0_1_3,
        INIT_04 => m_0_1_4, INIT_05 => m_0_1_5, INIT_06 => m_0_1_6, INIT_07 => m_0_1_7,
        INIT_08 => m_0_1_8, INIT_09 => m_0_1_9, INIT_0A => m_0_1_A, INIT_0B => m_0_1_B,
        INIT_0C => m_0_1_C, INIT_0D => m_0_1_D, INIT_0E => m_0_1_E, INIT_0F => m_0_1_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(1 downto 1),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_0,
                                DOA   => OPC_0(1 downto 1),             DOB   => OUT_0(1 downto 1)
                        );
 
        m_0_2 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_0_2_0, INIT_01 => m_0_2_1, INIT_02 => m_0_2_2, INIT_03 => m_0_2_3,
        INIT_04 => m_0_2_4, INIT_05 => m_0_2_5, INIT_06 => m_0_2_6, INIT_07 => m_0_2_7,
        INIT_08 => m_0_2_8, INIT_09 => m_0_2_9, INIT_0A => m_0_2_A, INIT_0B => m_0_2_B,
        INIT_0C => m_0_2_C, INIT_0D => m_0_2_D, INIT_0E => m_0_2_E, INIT_0F => m_0_2_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(2 downto 2),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_0,
                                DOA   => OPC_0(2 downto 2),             DOB   => OUT_0(2 downto 2)
                        );
 
        m_0_3 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_0_3_0, INIT_01 => m_0_3_1, INIT_02 => m_0_3_2, INIT_03 => m_0_3_3,
        INIT_04 => m_0_3_4, INIT_05 => m_0_3_5, INIT_06 => m_0_3_6, INIT_07 => m_0_3_7,
        INIT_08 => m_0_3_8, INIT_09 => m_0_3_9, INIT_0A => m_0_3_A, INIT_0B => m_0_3_B,
        INIT_0C => m_0_3_C, INIT_0D => m_0_3_D, INIT_0E => m_0_3_E, INIT_0F => m_0_3_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(3 downto 3),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_0,
                                DOA   => OPC_0(3 downto 3),             DOB   => OUT_0(3 downto 3)
                        );
 
        m_0_4 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_0_4_0, INIT_01 => m_0_4_1, INIT_02 => m_0_4_2, INIT_03 => m_0_4_3,
        INIT_04 => m_0_4_4, INIT_05 => m_0_4_5, INIT_06 => m_0_4_6, INIT_07 => m_0_4_7,
        INIT_08 => m_0_4_8, INIT_09 => m_0_4_9, INIT_0A => m_0_4_A, INIT_0B => m_0_4_B,
        INIT_0C => m_0_4_C, INIT_0D => m_0_4_D, INIT_0E => m_0_4_E, INIT_0F => m_0_4_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(4 downto 4),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_0,
                                DOA   => OPC_0(4 downto 4),             DOB   => OUT_0(4 downto 4)
                        );
 
        m_0_5 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_0_5_0, INIT_01 => m_0_5_1, INIT_02 => m_0_5_2, INIT_03 => m_0_5_3,
        INIT_04 => m_0_5_4, INIT_05 => m_0_5_5, INIT_06 => m_0_5_6, INIT_07 => m_0_5_7,
        INIT_08 => m_0_5_8, INIT_09 => m_0_5_9, INIT_0A => m_0_5_A, INIT_0B => m_0_5_B,
        INIT_0C => m_0_5_C, INIT_0D => m_0_5_D, INIT_0E => m_0_5_E, INIT_0F => m_0_5_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(5 downto 5),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_0,
                                DOA   => OPC_0(5 downto 5),             DOB   => OUT_0(5 downto 5)
                        );
 
        m_0_6 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_0_6_0, INIT_01 => m_0_6_1, INIT_02 => m_0_6_2, INIT_03 => m_0_6_3,
        INIT_04 => m_0_6_4, INIT_05 => m_0_6_5, INIT_06 => m_0_6_6, INIT_07 => m_0_6_7,
        INIT_08 => m_0_6_8, INIT_09 => m_0_6_9, INIT_0A => m_0_6_A, INIT_0B => m_0_6_B,
        INIT_0C => m_0_6_C, INIT_0D => m_0_6_D, INIT_0E => m_0_6_E, INIT_0F => m_0_6_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(6 downto 6),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_0,
                                DOA   => OPC_0(6 downto 6),             DOB   => OUT_0(6 downto 6)
                        );
 
        m_0_7 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_0_7_0, INIT_01 => m_0_7_1, INIT_02 => m_0_7_2, INIT_03 => m_0_7_3,
        INIT_04 => m_0_7_4, INIT_05 => m_0_7_5, INIT_06 => m_0_7_6, INIT_07 => m_0_7_7,
        INIT_08 => m_0_7_8, INIT_09 => m_0_7_9, INIT_0A => m_0_7_A, INIT_0B => m_0_7_B,
        INIT_0C => m_0_7_C, INIT_0D => m_0_7_D, INIT_0E => m_0_7_E, INIT_0F => m_0_7_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(7 downto 7),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_0,
                                DOA   => OPC_0(7 downto 7),             DOB   => OUT_0(7 downto 7)
                        );
 
        -- Bank 1 ------------------------------------------------------------------------
        --
        m_1_0 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_1_0_0, INIT_01 => m_1_0_1, INIT_02 => m_1_0_2, INIT_03 => m_1_0_3,
        INIT_04 => m_1_0_4, INIT_05 => m_1_0_5, INIT_06 => m_1_0_6, INIT_07 => m_1_0_7,
        INIT_08 => m_1_0_8, INIT_09 => m_1_0_9, INIT_0A => m_1_0_A, INIT_0B => m_1_0_B,
        INIT_0C => m_1_0_C, INIT_0D => m_1_0_D, INIT_0E => m_1_0_E, INIT_0F => m_1_0_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(0 downto 0),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_1,
                                DOA   => OPC_1(0 downto 0),               DOB   => OUT_1(0 downto 0)
                        );
 
        m_1_1 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_1_1_0, INIT_01 => m_1_1_1, INIT_02 => m_1_1_2, INIT_03 => m_1_1_3,
        INIT_04 => m_1_1_4, INIT_05 => m_1_1_5, INIT_06 => m_1_1_6, INIT_07 => m_1_1_7,
        INIT_08 => m_1_1_8, INIT_09 => m_1_1_9, INIT_0A => m_1_1_A, INIT_0B => m_1_1_B,
        INIT_0C => m_1_1_C, INIT_0D => m_1_1_D, INIT_0E => m_1_1_E, INIT_0F => m_1_1_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(1 downto 1),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_1,
                                DOA   => OPC_1(1 downto 1),             DOB   => OUT_1(1 downto 1)
                        );
 
        m_1_2 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_1_2_0, INIT_01 => m_1_2_1, INIT_02 => m_1_2_2, INIT_03 => m_1_2_3,
        INIT_04 => m_1_2_4, INIT_05 => m_1_2_5, INIT_06 => m_1_2_6, INIT_07 => m_1_2_7,
        INIT_08 => m_1_2_8, INIT_09 => m_1_2_9, INIT_0A => m_1_2_A, INIT_0B => m_1_2_B,
        INIT_0C => m_1_2_C, INIT_0D => m_1_2_D, INIT_0E => m_1_2_E, INIT_0F => m_1_2_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(2 downto 2),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_1,
                                DOA   => OPC_1(2 downto 2),             DOB   => OUT_1(2 downto 2)
                        );
 
        m_1_3 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_1_3_0, INIT_01 => m_1_3_1, INIT_02 => m_1_3_2, INIT_03 => m_1_3_3,
        INIT_04 => m_1_3_4, INIT_05 => m_1_3_5, INIT_06 => m_1_3_6, INIT_07 => m_1_3_7,
        INIT_08 => m_1_3_8, INIT_09 => m_1_3_9, INIT_0A => m_1_3_A, INIT_0B => m_1_3_B,
        INIT_0C => m_1_3_C, INIT_0D => m_1_3_D, INIT_0E => m_1_3_E, INIT_0F => m_1_3_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(3 downto 3),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_1,
                                DOA   => OPC_1(3 downto 3),             DOB   => OUT_1(3 downto 3)
                        );
 
        m_1_4 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_1_4_0, INIT_01 => m_1_4_1, INIT_02 => m_1_4_2, INIT_03 => m_1_4_3,
        INIT_04 => m_1_4_4, INIT_05 => m_1_4_5, INIT_06 => m_1_4_6, INIT_07 => m_1_4_7,
        INIT_08 => m_1_4_8, INIT_09 => m_1_4_9, INIT_0A => m_1_4_A, INIT_0B => m_1_4_B,
        INIT_0C => m_1_4_C, INIT_0D => m_1_4_D, INIT_0E => m_1_4_E, INIT_0F => m_1_4_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(4 downto 4),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_1,
                                DOA   => OPC_1(4 downto 4),             DOB   => OUT_1(4 downto 4)
                        );
 
        m_1_5 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_1_5_0, INIT_01 => m_1_5_1, INIT_02 => m_1_5_2, INIT_03 => m_1_5_3,
        INIT_04 => m_1_5_4, INIT_05 => m_1_5_5, INIT_06 => m_1_5_6, INIT_07 => m_1_5_7,
        INIT_08 => m_1_5_8, INIT_09 => m_1_5_9, INIT_0A => m_1_5_A, INIT_0B => m_1_5_B,
        INIT_0C => m_1_5_C, INIT_0D => m_1_5_D, INIT_0E => m_1_5_E, INIT_0F => m_1_5_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(5 downto 5),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_1,
                                DOA   => OPC_1(5 downto 5),             DOB   => OUT_1(5 downto 5)
                        );
        -- synopsys translate_on
 
        m_1_6 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_1_6_0, INIT_01 => m_1_6_1, INIT_02 => m_1_6_2, INIT_03 => m_1_6_3,
        INIT_04 => m_1_6_4, INIT_05 => m_1_6_5, INIT_06 => m_1_6_6, INIT_07 => m_1_6_7,
        INIT_08 => m_1_6_8, INIT_09 => m_1_6_9, INIT_0A => m_1_6_A, INIT_0B => m_1_6_B,
        INIT_0C => m_1_6_C, INIT_0D => m_1_6_D, INIT_0E => m_1_6_E, INIT_0F => m_1_6_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(6 downto 6),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_1,
                                DOA   => OPC_1(6 downto 6),             DOB   => OUT_1(6 downto 6)
                        );
 
 
        m_1_7 : RAMB4_S1_S1
        -- synopsys translate_off
        GENERIC MAP(
        INIT_00 => m_1_7_0, INIT_01 => m_1_7_1, INIT_02 => m_1_7_2, INIT_03 => m_1_7_3,
        INIT_04 => m_1_7_4, INIT_05 => m_1_7_5, INIT_06 => m_1_7_6, INIT_07 => m_1_7_7,
        INIT_08 => m_1_7_8, INIT_09 => m_1_7_9, INIT_0A => m_1_7_A, INIT_0B => m_1_7_B,
        INIT_0C => m_1_7_C, INIT_0D => m_1_7_D, INIT_0E => m_1_7_E, INIT_0F => m_1_7_F)
        -- synopsys translate_on
        PORT MAP(       ADDRA => PC(11 downto 0),                ADDRB => ADR(11 downto 0),
                                CLKA  => CLK_I,                                 CLKB  => CLK_I,
                                DIA   => "0",                                    DIB   => WDAT(7 downto 7),
                                ENA   => ENA,                                   ENB   => ENB,
                                RSTA  => '0',                                    RSTB  => '0',
                                WEA   => '0',                                    WEB   => WR_1,
                                DOA   => OPC_1(7 downto 7),             DOB   => OUT_1(7 downto 7)
                        );
 
        process(CLK_I)    -- new
        begin
                if (rising_edge(CLK_I) and T2 = '1') then
                        if (CE = '1') then
                                LADR <= ADR(15 downto 12);
                        end if;
                end if;
        end process;
 
 
        process(LADR, OUT_0, OUT_1)
        begin
 
                case LADR is
                        when "0001" =>  RDAT <= OUT_1;
                        when others =>  RDAT <= OUT_0;
                end case;
 
        end process;
 
        process(CLK_I)
        begin
                if (rising_edge(CLK_I) and T2 = '0') then
                        if (CE = '1') then
                                LPC <= PC(15 downto 12);
                        end if;
                end if;
        end process;
 
        process(LPC, OPC_0, OPC_1)
        begin
                case LPC is
                        when "0001" =>  OPC <= OPC_1;
                        when others =>  OPC <= OPC_0;
                end case;
        end process;
 
end Behavioral;

Browse

Tools

Subversion Repositories c16

[/] [c16/] [trunk/] [vhdl/] [memory.vhd] - Blame information for rev 33

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`-- Uncomment the following lines to use the declarations that are`
7			`-- provided for instantiating Xilinx primitive components.`
8			`library UNISIM;`
9			`use UNISIM.VComponents.all;`
10
11			`use work.cpu_pack.ALL;`
12			`use work.mem_content.All;`
13
14			`entity memory is`
15			`Port ( CLK_I : in std_logic;`
16			`T2 : in std_logic;`
17			`CE : in std_logic;`
18			`PC : in std_logic_vector(15 downto 0);`
19			`ADR : in std_logic_vector(15 downto 0);`
20			`WR : in std_logic;`
21			`WDAT : in std_logic_vector( 7 downto 0);`
22
23			`OPC : out std_logic_vector( 7 downto 0);`
24			`RDAT : out std_logic_vector( 7 downto 0)`
25			`);`
26			`end memory;`
27
28			`architecture Behavioral of memory is`
29
30			`signal ENA : std_logic;`
31			`signal ENB : std_logic;`
32
33			`signal WR_0 : std_logic;`
34			`signal WR_1 : std_logic;`
35
36			`signal LADR : std_logic_vector( 3 downto 0);`
37			`signal OUT_0 : std_logic_vector( 7 downto 0);`
38			`signal OUT_1 : std_logic_vector( 7 downto 0);`
39
40			`signal LPC : std_logic_vector( 3 downto 0);`
41			`signal OPC_0 : std_logic_vector( 7 downto 0);`
42			`signal OPC_1 : std_logic_vector( 7 downto 0);`
43
44			`begin`
45
46			`ENA <= CE and not T2;`
47			`ENB <= CE and T2;`
48
49			`WR_0 <= '1' when (WR = '1' and ADR(15 downto 12) = "0000" ) else '0';`
50			`WR_1 <= '1' when (WR = '1' and ADR(15 downto 12) = "0001" ) else '0';`
51
52			`-- Bank 0 ------------------------------------------------------------------------`
53			`--`
54			`m_0_0 : RAMB4_S1_S1`
55			`-- synopsys translate_off`
56			`GENERIC MAP(`
57			`INIT_00 => m_0_0_0, INIT_01 => m_0_0_1, INIT_02 => m_0_0_2, INIT_03 => m_0_0_3,`
58			`INIT_04 => m_0_0_4, INIT_05 => m_0_0_5, INIT_06 => m_0_0_6, INIT_07 => m_0_0_7,`
59			`INIT_08 => m_0_0_8, INIT_09 => m_0_0_9, INIT_0A => m_0_0_A, INIT_0B => m_0_0_B,`
60			`INIT_0C => m_0_0_C, INIT_0D => m_0_0_D, INIT_0E => m_0_0_E, INIT_0F => m_0_0_F)`
61			`-- synopsys translate_on`
62			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
63			`CLKA => CLK_I, CLKB => CLK_I,`
64			`DIA => "0", DIB => WDAT(0 downto 0),`
65			`ENA => ENA, ENB => ENB,`
66			`RSTA => '0', RSTB => '0',`
67			`WEA => '0', WEB => WR_0,`
68			`DOA => OPC_0(0 downto 0), DOB => OUT_0(0 downto 0)`
69			`);`
70
71			`m_0_1 : RAMB4_S1_S1`
72			`-- synopsys translate_off`
73			`GENERIC MAP(`
74			`INIT_00 => m_0_1_0, INIT_01 => m_0_1_1, INIT_02 => m_0_1_2, INIT_03 => m_0_1_3,`
75			`INIT_04 => m_0_1_4, INIT_05 => m_0_1_5, INIT_06 => m_0_1_6, INIT_07 => m_0_1_7,`
76			`INIT_08 => m_0_1_8, INIT_09 => m_0_1_9, INIT_0A => m_0_1_A, INIT_0B => m_0_1_B,`
77			`INIT_0C => m_0_1_C, INIT_0D => m_0_1_D, INIT_0E => m_0_1_E, INIT_0F => m_0_1_F)`
78			`-- synopsys translate_on`
79			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
80			`CLKA => CLK_I, CLKB => CLK_I,`
81			`DIA => "0", DIB => WDAT(1 downto 1),`
82			`ENA => ENA, ENB => ENB,`
83			`RSTA => '0', RSTB => '0',`
84			`WEA => '0', WEB => WR_0,`
85			`DOA => OPC_0(1 downto 1), DOB => OUT_0(1 downto 1)`
86			`);`
87
88			`m_0_2 : RAMB4_S1_S1`
89			`-- synopsys translate_off`
90			`GENERIC MAP(`
91			`INIT_00 => m_0_2_0, INIT_01 => m_0_2_1, INIT_02 => m_0_2_2, INIT_03 => m_0_2_3,`
92			`INIT_04 => m_0_2_4, INIT_05 => m_0_2_5, INIT_06 => m_0_2_6, INIT_07 => m_0_2_7,`
93			`INIT_08 => m_0_2_8, INIT_09 => m_0_2_9, INIT_0A => m_0_2_A, INIT_0B => m_0_2_B,`
94			`INIT_0C => m_0_2_C, INIT_0D => m_0_2_D, INIT_0E => m_0_2_E, INIT_0F => m_0_2_F)`
95			`-- synopsys translate_on`
96			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
97			`CLKA => CLK_I, CLKB => CLK_I,`
98			`DIA => "0", DIB => WDAT(2 downto 2),`
99			`ENA => ENA, ENB => ENB,`
100			`RSTA => '0', RSTB => '0',`
101			`WEA => '0', WEB => WR_0,`
102			`DOA => OPC_0(2 downto 2), DOB => OUT_0(2 downto 2)`
103			`);`
104
105			`m_0_3 : RAMB4_S1_S1`
106			`-- synopsys translate_off`
107			`GENERIC MAP(`
108			`INIT_00 => m_0_3_0, INIT_01 => m_0_3_1, INIT_02 => m_0_3_2, INIT_03 => m_0_3_3,`
109			`INIT_04 => m_0_3_4, INIT_05 => m_0_3_5, INIT_06 => m_0_3_6, INIT_07 => m_0_3_7,`
110			`INIT_08 => m_0_3_8, INIT_09 => m_0_3_9, INIT_0A => m_0_3_A, INIT_0B => m_0_3_B,`
111			`INIT_0C => m_0_3_C, INIT_0D => m_0_3_D, INIT_0E => m_0_3_E, INIT_0F => m_0_3_F)`
112			`-- synopsys translate_on`
113			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
114			`CLKA => CLK_I, CLKB => CLK_I,`
115			`DIA => "0", DIB => WDAT(3 downto 3),`
116			`ENA => ENA, ENB => ENB,`
117			`RSTA => '0', RSTB => '0',`
118			`WEA => '0', WEB => WR_0,`
119			`DOA => OPC_0(3 downto 3), DOB => OUT_0(3 downto 3)`
120			`);`
121
122			`m_0_4 : RAMB4_S1_S1`
123			`-- synopsys translate_off`
124			`GENERIC MAP(`
125			`INIT_00 => m_0_4_0, INIT_01 => m_0_4_1, INIT_02 => m_0_4_2, INIT_03 => m_0_4_3,`
126			`INIT_04 => m_0_4_4, INIT_05 => m_0_4_5, INIT_06 => m_0_4_6, INIT_07 => m_0_4_7,`
127			`INIT_08 => m_0_4_8, INIT_09 => m_0_4_9, INIT_0A => m_0_4_A, INIT_0B => m_0_4_B,`
128			`INIT_0C => m_0_4_C, INIT_0D => m_0_4_D, INIT_0E => m_0_4_E, INIT_0F => m_0_4_F)`
129			`-- synopsys translate_on`
130			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
131			`CLKA => CLK_I, CLKB => CLK_I,`
132			`DIA => "0", DIB => WDAT(4 downto 4),`
133			`ENA => ENA, ENB => ENB,`
134			`RSTA => '0', RSTB => '0',`
135			`WEA => '0', WEB => WR_0,`
136			`DOA => OPC_0(4 downto 4), DOB => OUT_0(4 downto 4)`
137			`);`
138
139			`m_0_5 : RAMB4_S1_S1`
140			`-- synopsys translate_off`
141			`GENERIC MAP(`
142			`INIT_00 => m_0_5_0, INIT_01 => m_0_5_1, INIT_02 => m_0_5_2, INIT_03 => m_0_5_3,`
143			`INIT_04 => m_0_5_4, INIT_05 => m_0_5_5, INIT_06 => m_0_5_6, INIT_07 => m_0_5_7,`
144			`INIT_08 => m_0_5_8, INIT_09 => m_0_5_9, INIT_0A => m_0_5_A, INIT_0B => m_0_5_B,`
145			`INIT_0C => m_0_5_C, INIT_0D => m_0_5_D, INIT_0E => m_0_5_E, INIT_0F => m_0_5_F)`
146			`-- synopsys translate_on`
147			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
148			`CLKA => CLK_I, CLKB => CLK_I,`
149			`DIA => "0", DIB => WDAT(5 downto 5),`
150			`ENA => ENA, ENB => ENB,`
151			`RSTA => '0', RSTB => '0',`
152			`WEA => '0', WEB => WR_0,`
153			`DOA => OPC_0(5 downto 5), DOB => OUT_0(5 downto 5)`
154			`);`
155
156			`m_0_6 : RAMB4_S1_S1`
157			`-- synopsys translate_off`
158			`GENERIC MAP(`
159			`INIT_00 => m_0_6_0, INIT_01 => m_0_6_1, INIT_02 => m_0_6_2, INIT_03 => m_0_6_3,`
160			`INIT_04 => m_0_6_4, INIT_05 => m_0_6_5, INIT_06 => m_0_6_6, INIT_07 => m_0_6_7,`
161			`INIT_08 => m_0_6_8, INIT_09 => m_0_6_9, INIT_0A => m_0_6_A, INIT_0B => m_0_6_B,`
162			`INIT_0C => m_0_6_C, INIT_0D => m_0_6_D, INIT_0E => m_0_6_E, INIT_0F => m_0_6_F)`
163			`-- synopsys translate_on`
164			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
165			`CLKA => CLK_I, CLKB => CLK_I,`
166			`DIA => "0", DIB => WDAT(6 downto 6),`
167			`ENA => ENA, ENB => ENB,`
168			`RSTA => '0', RSTB => '0',`
169			`WEA => '0', WEB => WR_0,`
170			`DOA => OPC_0(6 downto 6), DOB => OUT_0(6 downto 6)`
171			`);`
172
173			`m_0_7 : RAMB4_S1_S1`
174			`-- synopsys translate_off`
175			`GENERIC MAP(`
176			`INIT_00 => m_0_7_0, INIT_01 => m_0_7_1, INIT_02 => m_0_7_2, INIT_03 => m_0_7_3,`
177			`INIT_04 => m_0_7_4, INIT_05 => m_0_7_5, INIT_06 => m_0_7_6, INIT_07 => m_0_7_7,`
178			`INIT_08 => m_0_7_8, INIT_09 => m_0_7_9, INIT_0A => m_0_7_A, INIT_0B => m_0_7_B,`
179			`INIT_0C => m_0_7_C, INIT_0D => m_0_7_D, INIT_0E => m_0_7_E, INIT_0F => m_0_7_F)`
180			`-- synopsys translate_on`
181			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
182			`CLKA => CLK_I, CLKB => CLK_I,`
183			`DIA => "0", DIB => WDAT(7 downto 7),`
184			`ENA => ENA, ENB => ENB,`
185			`RSTA => '0', RSTB => '0',`
186			`WEA => '0', WEB => WR_0,`
187			`DOA => OPC_0(7 downto 7), DOB => OUT_0(7 downto 7)`
188			`);`
189
190			`-- Bank 1 ------------------------------------------------------------------------`
191			`--`
192			`m_1_0 : RAMB4_S1_S1`
193			`-- synopsys translate_off`
194			`GENERIC MAP(`
195			`INIT_00 => m_1_0_0, INIT_01 => m_1_0_1, INIT_02 => m_1_0_2, INIT_03 => m_1_0_3,`
196			`INIT_04 => m_1_0_4, INIT_05 => m_1_0_5, INIT_06 => m_1_0_6, INIT_07 => m_1_0_7,`
197			`INIT_08 => m_1_0_8, INIT_09 => m_1_0_9, INIT_0A => m_1_0_A, INIT_0B => m_1_0_B,`
198			`INIT_0C => m_1_0_C, INIT_0D => m_1_0_D, INIT_0E => m_1_0_E, INIT_0F => m_1_0_F)`
199			`-- synopsys translate_on`
200			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
201			`CLKA => CLK_I, CLKB => CLK_I,`
202			`DIA => "0", DIB => WDAT(0 downto 0),`
203			`ENA => ENA, ENB => ENB,`
204			`RSTA => '0', RSTB => '0',`
205			`WEA => '0', WEB => WR_1,`
206			`DOA => OPC_1(0 downto 0), DOB => OUT_1(0 downto 0)`
207			`);`
208
209			`m_1_1 : RAMB4_S1_S1`
210			`-- synopsys translate_off`
211			`GENERIC MAP(`
212			`INIT_00 => m_1_1_0, INIT_01 => m_1_1_1, INIT_02 => m_1_1_2, INIT_03 => m_1_1_3,`
213			`INIT_04 => m_1_1_4, INIT_05 => m_1_1_5, INIT_06 => m_1_1_6, INIT_07 => m_1_1_7,`
214			`INIT_08 => m_1_1_8, INIT_09 => m_1_1_9, INIT_0A => m_1_1_A, INIT_0B => m_1_1_B,`
215			`INIT_0C => m_1_1_C, INIT_0D => m_1_1_D, INIT_0E => m_1_1_E, INIT_0F => m_1_1_F)`
216			`-- synopsys translate_on`
217			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
218			`CLKA => CLK_I, CLKB => CLK_I,`
219			`DIA => "0", DIB => WDAT(1 downto 1),`
220			`ENA => ENA, ENB => ENB,`
221			`RSTA => '0', RSTB => '0',`
222			`WEA => '0', WEB => WR_1,`
223			`DOA => OPC_1(1 downto 1), DOB => OUT_1(1 downto 1)`
224			`);`
225
226			`m_1_2 : RAMB4_S1_S1`
227			`-- synopsys translate_off`
228			`GENERIC MAP(`
229			`INIT_00 => m_1_2_0, INIT_01 => m_1_2_1, INIT_02 => m_1_2_2, INIT_03 => m_1_2_3,`
230			`INIT_04 => m_1_2_4, INIT_05 => m_1_2_5, INIT_06 => m_1_2_6, INIT_07 => m_1_2_7,`
231			`INIT_08 => m_1_2_8, INIT_09 => m_1_2_9, INIT_0A => m_1_2_A, INIT_0B => m_1_2_B,`
232			`INIT_0C => m_1_2_C, INIT_0D => m_1_2_D, INIT_0E => m_1_2_E, INIT_0F => m_1_2_F)`
233			`-- synopsys translate_on`
234			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
235			`CLKA => CLK_I, CLKB => CLK_I,`
236			`DIA => "0", DIB => WDAT(2 downto 2),`
237			`ENA => ENA, ENB => ENB,`
238			`RSTA => '0', RSTB => '0',`
239			`WEA => '0', WEB => WR_1,`
240			`DOA => OPC_1(2 downto 2), DOB => OUT_1(2 downto 2)`
241			`);`
242
243			`m_1_3 : RAMB4_S1_S1`
244			`-- synopsys translate_off`
245			`GENERIC MAP(`
246			`INIT_00 => m_1_3_0, INIT_01 => m_1_3_1, INIT_02 => m_1_3_2, INIT_03 => m_1_3_3,`
247			`INIT_04 => m_1_3_4, INIT_05 => m_1_3_5, INIT_06 => m_1_3_6, INIT_07 => m_1_3_7,`
248			`INIT_08 => m_1_3_8, INIT_09 => m_1_3_9, INIT_0A => m_1_3_A, INIT_0B => m_1_3_B,`
249			`INIT_0C => m_1_3_C, INIT_0D => m_1_3_D, INIT_0E => m_1_3_E, INIT_0F => m_1_3_F)`
250			`-- synopsys translate_on`
251			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
252			`CLKA => CLK_I, CLKB => CLK_I,`
253			`DIA => "0", DIB => WDAT(3 downto 3),`
254			`ENA => ENA, ENB => ENB,`
255			`RSTA => '0', RSTB => '0',`
256			`WEA => '0', WEB => WR_1,`
257			`DOA => OPC_1(3 downto 3), DOB => OUT_1(3 downto 3)`
258			`);`
259
260			`m_1_4 : RAMB4_S1_S1`
261			`-- synopsys translate_off`
262			`GENERIC MAP(`
263			`INIT_00 => m_1_4_0, INIT_01 => m_1_4_1, INIT_02 => m_1_4_2, INIT_03 => m_1_4_3,`
264			`INIT_04 => m_1_4_4, INIT_05 => m_1_4_5, INIT_06 => m_1_4_6, INIT_07 => m_1_4_7,`
265			`INIT_08 => m_1_4_8, INIT_09 => m_1_4_9, INIT_0A => m_1_4_A, INIT_0B => m_1_4_B,`
266			`INIT_0C => m_1_4_C, INIT_0D => m_1_4_D, INIT_0E => m_1_4_E, INIT_0F => m_1_4_F)`
267			`-- synopsys translate_on`
268			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
269			`CLKA => CLK_I, CLKB => CLK_I,`
270			`DIA => "0", DIB => WDAT(4 downto 4),`
271			`ENA => ENA, ENB => ENB,`
272			`RSTA => '0', RSTB => '0',`
273			`WEA => '0', WEB => WR_1,`
274			`DOA => OPC_1(4 downto 4), DOB => OUT_1(4 downto 4)`
275			`);`
276
277			`m_1_5 : RAMB4_S1_S1`
278			`-- synopsys translate_off`
279			`GENERIC MAP(`
280			`INIT_00 => m_1_5_0, INIT_01 => m_1_5_1, INIT_02 => m_1_5_2, INIT_03 => m_1_5_3,`
281			`INIT_04 => m_1_5_4, INIT_05 => m_1_5_5, INIT_06 => m_1_5_6, INIT_07 => m_1_5_7,`
282			`INIT_08 => m_1_5_8, INIT_09 => m_1_5_9, INIT_0A => m_1_5_A, INIT_0B => m_1_5_B,`
283			`INIT_0C => m_1_5_C, INIT_0D => m_1_5_D, INIT_0E => m_1_5_E, INIT_0F => m_1_5_F)`
284			`-- synopsys translate_on`
285			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
286			`CLKA => CLK_I, CLKB => CLK_I,`
287			`DIA => "0", DIB => WDAT(5 downto 5),`
288			`ENA => ENA, ENB => ENB,`
289			`RSTA => '0', RSTB => '0',`
290			`WEA => '0', WEB => WR_1,`
291			`DOA => OPC_1(5 downto 5), DOB => OUT_1(5 downto 5)`
292			`);`
293			`-- synopsys translate_on`
294
295			`m_1_6 : RAMB4_S1_S1`
296			`-- synopsys translate_off`
297			`GENERIC MAP(`
298			`INIT_00 => m_1_6_0, INIT_01 => m_1_6_1, INIT_02 => m_1_6_2, INIT_03 => m_1_6_3,`
299			`INIT_04 => m_1_6_4, INIT_05 => m_1_6_5, INIT_06 => m_1_6_6, INIT_07 => m_1_6_7,`
300			`INIT_08 => m_1_6_8, INIT_09 => m_1_6_9, INIT_0A => m_1_6_A, INIT_0B => m_1_6_B,`
301			`INIT_0C => m_1_6_C, INIT_0D => m_1_6_D, INIT_0E => m_1_6_E, INIT_0F => m_1_6_F)`
302			`-- synopsys translate_on`
303			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
304			`CLKA => CLK_I, CLKB => CLK_I,`
305			`DIA => "0", DIB => WDAT(6 downto 6),`
306			`ENA => ENA, ENB => ENB,`
307			`RSTA => '0', RSTB => '0',`
308			`WEA => '0', WEB => WR_1,`
309			`DOA => OPC_1(6 downto 6), DOB => OUT_1(6 downto 6)`
310			`);`
311
312
313			`m_1_7 : RAMB4_S1_S1`
314			`-- synopsys translate_off`
315			`GENERIC MAP(`
316			`INIT_00 => m_1_7_0, INIT_01 => m_1_7_1, INIT_02 => m_1_7_2, INIT_03 => m_1_7_3,`
317			`INIT_04 => m_1_7_4, INIT_05 => m_1_7_5, INIT_06 => m_1_7_6, INIT_07 => m_1_7_7,`
318			`INIT_08 => m_1_7_8, INIT_09 => m_1_7_9, INIT_0A => m_1_7_A, INIT_0B => m_1_7_B,`
319			`INIT_0C => m_1_7_C, INIT_0D => m_1_7_D, INIT_0E => m_1_7_E, INIT_0F => m_1_7_F)`
320			`-- synopsys translate_on`
321			`PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),`
322			`CLKA => CLK_I, CLKB => CLK_I,`
323			`DIA => "0", DIB => WDAT(7 downto 7),`
324			`ENA => ENA, ENB => ENB,`
325			`RSTA => '0', RSTB => '0',`
326			`WEA => '0', WEB => WR_1,`
327			`DOA => OPC_1(7 downto 7), DOB => OUT_1(7 downto 7)`
328			`);`
329
330	21	jsauermann	`process(CLK_I) -- new`
331	2	jsauermann	`begin`
332	21	jsauermann	`if (rising_edge(CLK_I) and T2 = '1') then`
333			`if (CE = '1') then`
334			`LADR <= ADR(15 downto 12);`
335	2	jsauermann	`end if;`
336			`end if;`
337			`end process;`
338	21	jsauermann
339	2	jsauermann
340			`process(LADR, OUT_0, OUT_1)`
341			`begin`
342
343			`case LADR is`
344			`when "0001" => RDAT <= OUT_1;`
345			`when others => RDAT <= OUT_0;`
346			`end case;`
347
348			`end process;`
349
350			`process(CLK_I)`
351			`begin`
352	21	jsauermann	`if (rising_edge(CLK_I) and T2 = '0') then`
353			`if (CE = '1') then`
354			`LPC <= PC(15 downto 12);`
355	2	jsauermann	`end if;`
356			`end if;`
357			`end process;`
358
359			`process(LPC, OPC_0, OPC_1)`
360			`begin`
361			`case LPC is`
362			`when "0001" => OPC <= OPC_1;`
363			`when others => OPC <= OPC_0;`
364			`end case;`
365			`end process;`
366
367			`end Behavioral;`