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jsauermann |
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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use work.cpu_pack.ALL;
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entity select_yy is
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Port( SY : in std_logic_vector( 3 downto 0);
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IMM : in std_logic_vector(15 downto 0);
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QUICK : in std_logic_vector( 3 downto 0);
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M_RDAT : in std_logic_vector( 7 downto 0);
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IO_RDAT : in std_logic_vector( 7 downto 0);
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RR : in std_logic_vector(15 downto 0);
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YY : out std_logic_vector(15 downto 0)
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);
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end select_yy;
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architecture Behavioral of select_yy is
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function b4(A : std_logic) return std_logic_vector is
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begin
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return A & A & A & A;
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end;
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function b8(A : std_logic) return std_logic_vector is
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begin
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return b4(A) & b4(A);
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end;
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begin
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-- bits 1..0
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--
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s_1_0: process(SY, IMM(1 downto 0), QUICK(1 downto 0), M_RDAT(1 downto 0),
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IO_RDAT(1 downto 0), RR(1 downto 0))
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begin
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case SY is
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when SY_I16 | SY_SI8
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| SY_UI8 => YY(1 downto 0) <= IMM (1 downto 0);
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when SY_RR => YY(1 downto 0) <= RR (1 downto 0);
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when SY_SQ | SY_UQ => YY(1 downto 0) <= QUICK (1 downto 0);
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when SY_SM | SY_UM => YY(1 downto 0) <= M_RDAT (1 downto 0);
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when SY_IO => YY(1 downto 0) <= IO_RDAT(1 downto 0);
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when others => YY(1 downto 0) <= SY (1 downto 0);
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end case;
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end process;
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-- bits 3..2
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--
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s_3_2: process(SY, IMM(3 downto 2), QUICK(3 downto 2), M_RDAT(3 downto 2),
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IO_RDAT(3 downto 2), RR(3 downto 2))
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begin
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case SY is
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when SY_I16 | SY_SI8
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| SY_UI8 => YY(3 downto 2) <= IMM (3 downto 2);
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when SY_RR => YY(3 downto 2) <= RR (3 downto 2);
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when SY_SQ | SY_UQ => YY(3 downto 2) <= QUICK (3 downto 2);
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when SY_SM | SY_UM => YY(3 downto 2) <= M_RDAT (3 downto 2);
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when SY_IO => YY(3 downto 2) <= IO_RDAT(3 downto 2);
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when others => YY(3 downto 2) <= "00";
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end case;
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end process;
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-- bits 7..4
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--
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s_7_4: process(SY, IMM(7 downto 4), QUICK(3), M_RDAT(7 downto 4),
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IO_RDAT(7 downto 4), RR(7 downto 4))
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begin
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case SY is
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when SY_I16 | SY_SI8
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| SY_UI8 => YY(7 downto 4) <= IMM (7 downto 4);
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when SY_RR => YY(7 downto 4) <= RR (7 downto 4);
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when SY_SQ => YY(7 downto 4) <= b4(QUICK(3));
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when SY_SM | SY_UM => YY(7 downto 4) <= M_RDAT (7 downto 4);
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when SY_IO => YY(7 downto 4) <= IO_RDAT(7 downto 4);
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when others => YY(7 downto 4) <= "0000";
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end case;
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end process;
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-- bits 15..8
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--
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s_15_8: process(SY, IMM(15 downto 7), QUICK(3), M_RDAT(7), RR(15 downto 8))
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begin
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case SY is
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when SY_I16 => YY(15 downto 8) <= IMM (15 downto 8);
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when SY_SI8 => YY(15 downto 8) <= b8(IMM(7));
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when SY_RR => YY(15 downto 8) <= RR(15 downto 8);
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when SY_SQ => YY(15 downto 8) <= b8(QUICK(3));
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when SY_SM => YY(15 downto 8) <= b8(M_RDAT(7));
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when others => YY(15 downto 8) <= "00000000";
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end case;
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end process;
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end Behavioral;
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