URL https://opencores.org/ocsvn/c16/c16/trunk

Subversion Repositories c16

[/] [c16/] [trunk/] [vhdl/] [select_yy.vhd] - Blame information for rev 33

Go to most recent revision | Details | Compare with Previous | View Log


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity select_yy is
    Port(       SY    : in  std_logic_vector( 3 downto 0);
                        IMM   : in  std_logic_vector(15 downto 0);
                        QUICK : in  std_logic_vector( 3 downto 0);
                        RDAT  : in  std_logic_vector( 7 downto 0);
                        RR    : in  std_logic_vector(15 downto 0);
                        YY    : out std_logic_vector(15 downto 0)
                );
end select_yy;
 
architecture Behavioral of select_yy is
 
        function b4(A : std_logic) return std_logic_vector is
        begin
                return A & A & A & A;
        end;
 
        function b8(A : std_logic) return std_logic_vector is
        begin
                return b4(A) & b4(A);
        end;
 
begin
 
        -- bits 1..0
        --
        s_1_0: process(SY, IMM(1 downto 0), QUICK(1 downto 0), RDAT(1 downto 0),
                       RR(1 downto 0))
        begin
                case SY is
                        when SY_I16 | SY_SI8
                           | SY_UI8                     => YY(1 downto 0) <= IMM  (1 downto 0);
                        when SY_RR                      => YY(1 downto 0) <= RR   (1 downto 0);
                        when SY_SQ | SY_UQ      => YY(1 downto 0) <= QUICK(1 downto 0);
                        when SY_SM | SY_UM      => YY(1 downto 0) <= RDAT (1 downto 0);
                        when others                     => YY(1 downto 0) <= SY   (1 downto 0);
                end case;
        end process;
 
        -- bits 3..2
        --
        s_3_2: process(SY, IMM(3 downto 2), QUICK(3 downto 2), RDAT(3 downto 2),
                       RR(3 downto 2))
        begin
                case SY is
                        when SY_I16 | SY_SI8
                           | SY_UI8                     => YY(3 downto 2) <= IMM  (3 downto 2);
                        when SY_RR                      => YY(3 downto 2) <= RR   (3 downto 2);
                        when SY_SQ | SY_UQ      => YY(3 downto 2) <= QUICK(3 downto 2);
                        when SY_SM | SY_UM      => YY(3 downto 2) <= RDAT (3 downto 2);
                        when others                     => YY(3 downto 2) <= "00";
                end case;
        end process;
 
        -- bits 7..4
        --
        s_7_4: process(SY, IMM(7 downto 4), QUICK(3), RDAT(7 downto 4),
                       RR(7 downto 4))
        begin
                case SY is
                        when SY_I16 | SY_SI8
                           | SY_UI8                     => YY(7 downto 4) <= IMM  (7 downto 4);
                        when SY_RR                      => YY(7 downto 4) <= RR   (7 downto 4);
                        when SY_SQ                      => YY(7 downto 4) <= b4(QUICK(3));
                        when SY_SM | SY_UM      => YY(7 downto 4) <= RDAT (7 downto 4);
                        when others                     => YY(7 downto 4) <= "0000";
                end case;
        end process;
 
        -- bits 15..8
        --
        s_15_8: process(SY, IMM(15 downto 7), QUICK(3), RDAT(7), RR(15 downto 8))
        begin
                case SY is
                        when SY_I16                     => YY(15 downto 8) <= IMM  (15 downto 8);
                        when SY_SI8                     => YY(15 downto 8) <= b8(IMM(7));
                        when SY_RR                      => YY(15 downto 8) <= RR(15 downto 8);
                        when SY_SQ                      => YY(15 downto 8) <= b8(QUICK(3));
                        when SY_SM                      => YY(15 downto 8) <= b8(RDAT(7));
                        when others                     => YY(15 downto 8) <= "00000000";
                end case;
        end process;
 
end Behavioral;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`-- Uncomment the following lines to use the declarations that are`
7			`-- provided for instantiating Xilinx primitive components.`
8			`--library UNISIM;`
9			`--use UNISIM.VComponents.all;`
10
11			`use work.cpu_pack.ALL;`
12
13			`entity select_yy is`
14	9	jsauermann	`Port( SY : in std_logic_vector( 3 downto 0);`
15			`IMM : in std_logic_vector(15 downto 0);`
16			`QUICK : in std_logic_vector( 3 downto 0);`
17			`RDAT : in std_logic_vector( 7 downto 0);`
18			`RR : in std_logic_vector(15 downto 0);`
19			`YY : out std_logic_vector(15 downto 0)`
20	2	jsauermann	`);`
21			`end select_yy;`
22
23			`architecture Behavioral of select_yy is`
24
25			`function b4(A : std_logic) return std_logic_vector is`
26			`begin`
27			`return A & A & A & A;`
28			`end;`
29
30			`function b8(A : std_logic) return std_logic_vector is`
31			`begin`
32			`return b4(A) & b4(A);`
33			`end;`
34
35			`begin`
36
37			`-- bits 1..0`
38			`--`
39	9	jsauermann	`s_1_0: process(SY, IMM(1 downto 0), QUICK(1 downto 0), RDAT(1 downto 0),`
40			`RR(1 downto 0))`
41	2	jsauermann	`begin`
42			`case SY is`
43			`when SY_I16 \| SY_SI8`
44	9	jsauermann	`\| SY_UI8 => YY(1 downto 0) <= IMM (1 downto 0);`
45			`when SY_RR => YY(1 downto 0) <= RR (1 downto 0);`
46			`when SY_SQ \| SY_UQ => YY(1 downto 0) <= QUICK(1 downto 0);`
47			`when SY_SM \| SY_UM => YY(1 downto 0) <= RDAT (1 downto 0);`
48			`when others => YY(1 downto 0) <= SY (1 downto 0);`
49	2	jsauermann	`end case;`
50			`end process;`
51
52			`-- bits 3..2`
53			`--`
54	9	jsauermann	`s_3_2: process(SY, IMM(3 downto 2), QUICK(3 downto 2), RDAT(3 downto 2),`
55			`RR(3 downto 2))`
56	2	jsauermann	`begin`
57			`case SY is`
58			`when SY_I16 \| SY_SI8`
59	9	jsauermann	`\| SY_UI8 => YY(3 downto 2) <= IMM (3 downto 2);`
60			`when SY_RR => YY(3 downto 2) <= RR (3 downto 2);`
61			`when SY_SQ \| SY_UQ => YY(3 downto 2) <= QUICK(3 downto 2);`
62			`when SY_SM \| SY_UM => YY(3 downto 2) <= RDAT (3 downto 2);`
63	2	jsauermann	`when others => YY(3 downto 2) <= "00";`
64			`end case;`
65			`end process;`
66
67			`-- bits 7..4`
68			`--`
69	9	jsauermann	`s_7_4: process(SY, IMM(7 downto 4), QUICK(3), RDAT(7 downto 4),`
70			`RR(7 downto 4))`
71	2	jsauermann	`begin`
72			`case SY is`
73			`when SY_I16 \| SY_SI8`
74	9	jsauermann	`\| SY_UI8 => YY(7 downto 4) <= IMM (7 downto 4);`
75			`when SY_RR => YY(7 downto 4) <= RR (7 downto 4);`
76	2	jsauermann	`when SY_SQ => YY(7 downto 4) <= b4(QUICK(3));`
77	9	jsauermann	`when SY_SM \| SY_UM => YY(7 downto 4) <= RDAT (7 downto 4);`
78	2	jsauermann	`when others => YY(7 downto 4) <= "0000";`
79			`end case;`
80			`end process;`
81
82			`-- bits 15..8`
83			`--`
84	9	jsauermann	`s_15_8: process(SY, IMM(15 downto 7), QUICK(3), RDAT(7), RR(15 downto 8))`
85	2	jsauermann	`begin`
86			`case SY is`
87			`when SY_I16 => YY(15 downto 8) <= IMM (15 downto 8);`
88			`when SY_SI8 => YY(15 downto 8) <= b8(IMM(7));`
89			`when SY_RR => YY(15 downto 8) <= RR(15 downto 8);`
90			`when SY_SQ => YY(15 downto 8) <= b8(QUICK(3));`
91	9	jsauermann	`when SY_SM => YY(15 downto 8) <= b8(RDAT(7));`
92	2	jsauermann	`when others => YY(15 downto 8) <= "00000000";`
93			`end case;`
94			`end process;`
95
96			`end Behavioral;`

Browse

Tools

Subversion Repositories c16

[/] [c16/] [trunk/] [vhdl/] [select_yy.vhd] - Blame information for rev 33