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[/] [c16/] [trunk/] [vhdl/] [temperature.vhd] - Blame information for rev 2

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
entity temperature is
        PORT(   CLK_I                   : in STD_LOGIC;
                        T2                              : in STD_LOGIC;
                        CLR                             : in STD_LOGIC;
                        DATA_OUT                : out STD_LOGIC_VECTOR(7 downto 0);
                        TEMP_SPI                : out STD_LOGIC;
                        TEMP_SPO                : in STD_LOGIC;
                        TEMP_CE                 : out STD_LOGIC;
                        TEMP_SCLK               : out STD_LOGIC
    );
end temperature;
 
architecture behavioral of temperature is
 
        component DS1722
        PORT(   RESET                   : in std_logic;
                        CLK_I                   : in std_logic;
                        T2                              : in std_logic;
 
                        DATA_IN                 : in std_logic_vector(7 downto 0);
                        DATA_OUT                : out std_logic_vector(7 downto 0);
                        ADDRESS                 : in std_logic_vector(7 downto 0);
 
                        START                   : in std_logic;
                        DONE                    : out std_logic;
 
                        TEMP_SPI                : out STD_LOGIC;
                        TEMP_SPO                : in STD_LOGIC;
                        TEMP_CE                 : out STD_LOGIC;
                        TEMP_SCLK               : out STD_LOGIC
                );
end component;
 
        signal TEMP_DATA_IN             : STD_LOGIC_VECTOR (7 downto 0);
        signal TEMP_DATA_OUT    : STD_LOGIC_VECTOR (7 downto 0);
        signal TEMP_ADDRESS             : STD_LOGIC_VECTOR (7 downto 0);
        signal TEMP_START               : std_logic;
        signal TEMP_DONE                : std_logic;
 
        type TEMPERATURE_STATES is (TEMP_IDLE, TEMP_SETUP, TEMP_SETUP_COMPLETE,
                                                                TEMP_GET_DATA, TEMP_GET_DATA_COMPLETE);
        signal TEMP_state       : TEMPERATURE_STATES;
 
begin
 
        tsensor: DS1722
        PORT MAP(       CLK_I           => CLK_I,
                                T2                      => T2,
                                RESET           => CLR,
 
                                DATA_IN         => TEMP_DATA_IN,
                                DATA_OUT        => TEMP_DATA_OUT,
                                ADDRESS         => TEMP_ADDRESS,
 
                                START           => TEMP_START,
                                DONE            => TEMP_DONE,
 
                                TEMP_SPI        => TEMP_SPI,
                                TEMP_SPO        => TEMP_SPO,
                                TEMP_CE         => TEMP_CE,
                                TEMP_SCLK       => TEMP_SCLK
                        );
 
-- State machine to step though the process of getting data from the Digital Thermometer.
        process (CLR, CLK_I)
        begin
                if (CLR = '1') then
                        TEMP_state   <= TEMP_IDLE;
                        TEMP_START   <= '0';
                        TEMP_ADDRESS <= "00000000";
                        TEMP_DATA_IN <= "00000000";
                elsif (rising_edge(CLK_I)) then
                        if (T2 = '1') then
                                case TEMP_state is
                                        when TEMP_IDLE =>
                                                TEMP_START   <= '0';
                                                TEMP_ADDRESS <= "00000000";
                                                TEMP_DATA_IN <= "00000000";
                                                TEMP_state   <= TEMP_SETUP;
 
                                        when TEMP_SETUP =>
                                                TEMP_ADDRESS <= "10000000";
                                                TEMP_DATA_IN <= "11101000";
                                                if (TEMP_DONE = '1') then
                                                        TEMP_state <= TEMP_SETUP_COMPLETE;
                                                        TEMP_START <= '0';
                                                else
                                                        TEMP_state <= TEMP_SETUP;
                                                        TEMP_START <= '1';
                                                end if;
 
                                        when TEMP_SETUP_COMPLETE =>
                                                TEMP_START <= '0';
                                     if (TEMP_DONE = '1') then
                                                        TEMP_state <= TEMP_SETUP_COMPLETE;
                                                else
                                                        TEMP_state <= TEMP_GET_DATA;
                                                end if;
 
                                        when TEMP_GET_DATA =>
                                                TEMP_ADDRESS <= "00000010";
                                                if (TEMP_DONE = '1') then
                                                        TEMP_state <= TEMP_GET_DATA_COMPLETE;
                                                        DATA_OUT   <= TEMP_DATA_OUT;
                                                        TEMP_START <= '0';
                                                else
                                                        TEMP_state <= TEMP_GET_DATA;
                                                        TEMP_START <= '1';
                                                end if;
 
                                        when TEMP_GET_DATA_COMPLETE =>
                                                TEMP_START <= '0';
                                 if (TEMP_DONE = '1') then
                                                        TEMP_state <= TEMP_GET_DATA_COMPLETE;
                                                else
                                                        TEMP_state <= TEMP_GET_DATA;
                                                end if;
                                end case;
                        end if;
                end if;
        end process;
 
end behavioral;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3			`use IEEE.std_logic_unsigned.all;`
4
5			`entity temperature is`
6			`PORT( CLK_I : in STD_LOGIC;`
7			`T2 : in STD_LOGIC;`
8			`CLR : in STD_LOGIC;`
9			`DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0);`
10			`TEMP_SPI : out STD_LOGIC;`
11			`TEMP_SPO : in STD_LOGIC;`
12			`TEMP_CE : out STD_LOGIC;`
13			`TEMP_SCLK : out STD_LOGIC`
14			`);`
15			`end temperature;`
16
17			`architecture behavioral of temperature is`
18
19			`component DS1722`
20			`PORT( RESET : in std_logic;`
21			`CLK_I : in std_logic;`
22			`T2 : in std_logic;`
23
24			`DATA_IN : in std_logic_vector(7 downto 0);`
25			`DATA_OUT : out std_logic_vector(7 downto 0);`
26			`ADDRESS : in std_logic_vector(7 downto 0);`
27
28			`START : in std_logic;`
29			`DONE : out std_logic;`
30
31			`TEMP_SPI : out STD_LOGIC;`
32			`TEMP_SPO : in STD_LOGIC;`
33			`TEMP_CE : out STD_LOGIC;`
34			`TEMP_SCLK : out STD_LOGIC`
35			`);`
36			`end component;`
37
38			`signal TEMP_DATA_IN : STD_LOGIC_VECTOR (7 downto 0);`
39			`signal TEMP_DATA_OUT : STD_LOGIC_VECTOR (7 downto 0);`
40			`signal TEMP_ADDRESS : STD_LOGIC_VECTOR (7 downto 0);`
41			`signal TEMP_START : std_logic;`
42			`signal TEMP_DONE : std_logic;`
43
44			`type TEMPERATURE_STATES is (TEMP_IDLE, TEMP_SETUP, TEMP_SETUP_COMPLETE,`
45			`TEMP_GET_DATA, TEMP_GET_DATA_COMPLETE);`
46			`signal TEMP_state : TEMPERATURE_STATES;`
47
48			`begin`
49
50			`tsensor: DS1722`
51			`PORT MAP( CLK_I => CLK_I,`
52			`T2 => T2,`
53			`RESET => CLR,`
54
55			`DATA_IN => TEMP_DATA_IN,`
56			`DATA_OUT => TEMP_DATA_OUT,`
57			`ADDRESS => TEMP_ADDRESS,`
58
59			`START => TEMP_START,`
60			`DONE => TEMP_DONE,`
61
62			`TEMP_SPI => TEMP_SPI,`
63			`TEMP_SPO => TEMP_SPO,`
64			`TEMP_CE => TEMP_CE,`
65			`TEMP_SCLK => TEMP_SCLK`
66			`);`
67
68			`-- State machine to step though the process of getting data from the Digital Thermometer.`
69			`process (CLR, CLK_I)`
70			`begin`
71			`if (CLR = '1') then`
72			`TEMP_state <= TEMP_IDLE;`
73			`TEMP_START <= '0';`
74			`TEMP_ADDRESS <= "00000000";`
75			`TEMP_DATA_IN <= "00000000";`
76			`elsif (rising_edge(CLK_I)) then`
77			`if (T2 = '1') then`
78			`case TEMP_state is`
79			`when TEMP_IDLE =>`
80			`TEMP_START <= '0';`
81			`TEMP_ADDRESS <= "00000000";`
82			`TEMP_DATA_IN <= "00000000";`
83			`TEMP_state <= TEMP_SETUP;`
84
85			`when TEMP_SETUP =>`
86			`TEMP_ADDRESS <= "10000000";`
87			`TEMP_DATA_IN <= "11101000";`
88			`if (TEMP_DONE = '1') then`
89			`TEMP_state <= TEMP_SETUP_COMPLETE;`
90			`TEMP_START <= '0';`
91			`else`
92			`TEMP_state <= TEMP_SETUP;`
93			`TEMP_START <= '1';`
94			`end if;`
95
96			`when TEMP_SETUP_COMPLETE =>`
97			`TEMP_START <= '0';`
98			`if (TEMP_DONE = '1') then`
99			`TEMP_state <= TEMP_SETUP_COMPLETE;`
100			`else`
101			`TEMP_state <= TEMP_GET_DATA;`
102			`end if;`
103
104			`when TEMP_GET_DATA =>`
105			`TEMP_ADDRESS <= "00000010";`
106			`if (TEMP_DONE = '1') then`
107			`TEMP_state <= TEMP_GET_DATA_COMPLETE;`
108			`DATA_OUT <= TEMP_DATA_OUT;`
109			`TEMP_START <= '0';`
110			`else`
111			`TEMP_state <= TEMP_GET_DATA;`
112			`TEMP_START <= '1';`
113			`end if;`
114
115			`when TEMP_GET_DATA_COMPLETE =>`
116			`TEMP_START <= '0';`
117			`if (TEMP_DONE = '1') then`
118			`TEMP_state <= TEMP_GET_DATA_COMPLETE;`
119			`else`
120			`TEMP_state <= TEMP_GET_DATA;`
121			`end if;`
122			`end case;`
123			`end if;`
124			`end if;`
125			`end process;`
126
127			`end behavioral;`

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[/] [c16/] [trunk/] [vhdl/] [temperature.vhd] - Blame information for rev 2