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[/] [c16/] [trunk/] [vhdl/] [temperature.vhd] - Blame information for rev 31

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
entity temperature is
        PORT(   CLK_I                   : in STD_LOGIC;
                        RST_I                   : in STD_LOGIC;
                        DATA_OUT                : out STD_LOGIC_VECTOR(7 downto 0);
                        TEMP_SPI                : out STD_LOGIC;
                        TEMP_SPO                : in STD_LOGIC;
                        TEMP_CE                 : out STD_LOGIC;
                        TEMP_SCLK               : out STD_LOGIC
    );
end temperature;
 
architecture behavioral of temperature is
 
        component DS1722
        PORT(   CLK_I                   : in std_logic;
                        RST_I                   : in std_logic;
 
                        DATA_IN                 : in std_logic_vector(7 downto 0);
                        DATA_OUT                : out std_logic_vector(7 downto 0);
                        ADDRESS                 : in std_logic_vector(7 downto 0);
 
                        START                   : in std_logic;
                        DONE                    : out std_logic;
 
                        TEMP_SPI                : out STD_LOGIC;
                        TEMP_SPO                : in STD_LOGIC;
                        TEMP_CE                 : out STD_LOGIC;
                        TEMP_SCLK               : out STD_LOGIC
                );
end component;
 
        signal TEMP_DATA_IN             : STD_LOGIC_VECTOR (7 downto 0);
        signal TEMP_DATA_OUT    : STD_LOGIC_VECTOR (7 downto 0);
        signal TEMP_ADDRESS             : STD_LOGIC_VECTOR (7 downto 0);
        signal TEMP_START               : std_logic;
        signal TEMP_DONE                : std_logic;
 
        type TEMPERATURE_STATES is (TEMP_IDLE, TEMP_SETUP, TEMP_SETUP_COMPLETE,
                                                                TEMP_GET_DATA, TEMP_GET_DATA_COMPLETE);
        signal TEMP_state       : TEMPERATURE_STATES;
 
begin
 
        tsensor: DS1722
        PORT MAP(       CLK_I           => CLK_I,
                                RST_I           => RST_I,
 
                                DATA_IN         => TEMP_DATA_IN,
                                DATA_OUT        => TEMP_DATA_OUT,
                                ADDRESS         => TEMP_ADDRESS,
 
                                START           => TEMP_START,
                                DONE            => TEMP_DONE,
 
                                TEMP_SPI        => TEMP_SPI,
                                TEMP_SPO        => TEMP_SPO,
                                TEMP_CE         => TEMP_CE,
                                TEMP_SCLK       => TEMP_SCLK
                        );
 
        -- State machine to step though the process of getting data
        -- from the Digital Thermometer.
        --
        process (CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (RST_I = '1') then
                                TEMP_state   <= TEMP_IDLE;
                                TEMP_START   <= '0';
                                TEMP_ADDRESS <= "00000000";
                                TEMP_DATA_IN <= "00000000";
                        else
                                case TEMP_state is
                                        when TEMP_IDLE =>
                                                TEMP_START   <= '0';
                                                TEMP_ADDRESS <= "00000000";
                                                TEMP_DATA_IN <= "00000000";
                                                TEMP_state   <= TEMP_SETUP;
 
                                        when TEMP_SETUP =>
                                                TEMP_ADDRESS <= "10000000";
                                                TEMP_DATA_IN <= "11101000";
                                                if (TEMP_DONE = '1') then
                                                        TEMP_state <= TEMP_SETUP_COMPLETE;
                                                        TEMP_START <= '0';
                                                else
                                                        TEMP_state <= TEMP_SETUP;
                                                        TEMP_START <= '1';
                                                end if;
 
                                        when TEMP_SETUP_COMPLETE =>
                                                TEMP_START <= '0';
                                     if (TEMP_DONE = '1') then
                                                        TEMP_state <= TEMP_SETUP_COMPLETE;
                                                else
                                                        TEMP_state <= TEMP_GET_DATA;
                                                end if;
 
                                        when TEMP_GET_DATA =>
                                                TEMP_ADDRESS <= "00000010";
                                                if (TEMP_DONE = '1') then
                                                        TEMP_state <= TEMP_GET_DATA_COMPLETE;
                                                        DATA_OUT   <= TEMP_DATA_OUT;
                                                        TEMP_START <= '0';
                                                else
                                                        TEMP_state <= TEMP_GET_DATA;
                                                        TEMP_START <= '1';
                                                end if;
 
                                        when TEMP_GET_DATA_COMPLETE =>
                                                TEMP_START <= '0';
                                 if (TEMP_DONE = '1') then
                                                        TEMP_state <= TEMP_GET_DATA_COMPLETE;
                                                else
                                                        TEMP_state <= TEMP_GET_DATA;
                                                end if;
                                end case;
                        end if;
                end if;
        end process;
 
end behavioral;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3			`use IEEE.std_logic_unsigned.all;`
4
5			`entity temperature is`
6			`PORT( CLK_I : in STD_LOGIC;`
7	9	jsauermann	`RST_I : in STD_LOGIC;`
8	2	jsauermann	`DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0);`
9			`TEMP_SPI : out STD_LOGIC;`
10			`TEMP_SPO : in STD_LOGIC;`
11			`TEMP_CE : out STD_LOGIC;`
12			`TEMP_SCLK : out STD_LOGIC`
13			`);`
14			`end temperature;`
15
16			`architecture behavioral of temperature is`
17
18			`component DS1722`
19	9	jsauermann	`PORT( CLK_I : in std_logic;`
20			`RST_I : in std_logic;`
21	2	jsauermann
22			`DATA_IN : in std_logic_vector(7 downto 0);`
23			`DATA_OUT : out std_logic_vector(7 downto 0);`
24			`ADDRESS : in std_logic_vector(7 downto 0);`
25
26			`START : in std_logic;`
27			`DONE : out std_logic;`
28
29			`TEMP_SPI : out STD_LOGIC;`
30			`TEMP_SPO : in STD_LOGIC;`
31			`TEMP_CE : out STD_LOGIC;`
32			`TEMP_SCLK : out STD_LOGIC`
33			`);`
34			`end component;`
35
36			`signal TEMP_DATA_IN : STD_LOGIC_VECTOR (7 downto 0);`
37			`signal TEMP_DATA_OUT : STD_LOGIC_VECTOR (7 downto 0);`
38			`signal TEMP_ADDRESS : STD_LOGIC_VECTOR (7 downto 0);`
39			`signal TEMP_START : std_logic;`
40			`signal TEMP_DONE : std_logic;`
41
42			`type TEMPERATURE_STATES is (TEMP_IDLE, TEMP_SETUP, TEMP_SETUP_COMPLETE,`
43			`TEMP_GET_DATA, TEMP_GET_DATA_COMPLETE);`
44			`signal TEMP_state : TEMPERATURE_STATES;`
45
46			`begin`
47
48			`tsensor: DS1722`
49			`PORT MAP( CLK_I => CLK_I,`
50	9	jsauermann	`RST_I => RST_I,`
51	2	jsauermann
52			`DATA_IN => TEMP_DATA_IN,`
53			`DATA_OUT => TEMP_DATA_OUT,`
54			`ADDRESS => TEMP_ADDRESS,`
55
56			`START => TEMP_START,`
57			`DONE => TEMP_DONE,`
58
59			`TEMP_SPI => TEMP_SPI,`
60			`TEMP_SPO => TEMP_SPO,`
61			`TEMP_CE => TEMP_CE,`
62			`TEMP_SCLK => TEMP_SCLK`
63			`);`
64
65	9	jsauermann	`-- State machine to step though the process of getting data`
66			`-- from the Digital Thermometer.`
67			`--`
68			`process (CLK_I)`
69	2	jsauermann	`begin`
70	9	jsauermann	`if (rising_edge(CLK_I)) then`
71			`if (RST_I = '1') then`
72			`TEMP_state <= TEMP_IDLE;`
73			`TEMP_START <= '0';`
74			`TEMP_ADDRESS <= "00000000";`
75			`TEMP_DATA_IN <= "00000000";`
76			`else`
77	2	jsauermann	`case TEMP_state is`
78			`when TEMP_IDLE =>`
79			`TEMP_START <= '0';`
80			`TEMP_ADDRESS <= "00000000";`
81			`TEMP_DATA_IN <= "00000000";`
82			`TEMP_state <= TEMP_SETUP;`
83
84			`when TEMP_SETUP =>`
85			`TEMP_ADDRESS <= "10000000";`
86			`TEMP_DATA_IN <= "11101000";`
87			`if (TEMP_DONE = '1') then`
88			`TEMP_state <= TEMP_SETUP_COMPLETE;`
89			`TEMP_START <= '0';`
90			`else`
91			`TEMP_state <= TEMP_SETUP;`
92			`TEMP_START <= '1';`
93			`end if;`
94
95			`when TEMP_SETUP_COMPLETE =>`
96			`TEMP_START <= '0';`
97			`if (TEMP_DONE = '1') then`
98			`TEMP_state <= TEMP_SETUP_COMPLETE;`
99			`else`
100			`TEMP_state <= TEMP_GET_DATA;`
101			`end if;`
102
103			`when TEMP_GET_DATA =>`
104			`TEMP_ADDRESS <= "00000010";`
105			`if (TEMP_DONE = '1') then`
106			`TEMP_state <= TEMP_GET_DATA_COMPLETE;`
107			`DATA_OUT <= TEMP_DATA_OUT;`
108			`TEMP_START <= '0';`
109			`else`
110			`TEMP_state <= TEMP_GET_DATA;`
111			`TEMP_START <= '1';`
112			`end if;`
113
114			`when TEMP_GET_DATA_COMPLETE =>`
115			`TEMP_START <= '0';`
116			`if (TEMP_DONE = '1') then`
117			`TEMP_state <= TEMP_GET_DATA_COMPLETE;`
118			`else`
119			`TEMP_state <= TEMP_GET_DATA;`
120			`end if;`
121			`end case;`
122			`end if;`
123			`end if;`
124			`end process;`
125
126			`end behavioral;`

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[/] [c16/] [trunk/] [vhdl/] [temperature.vhd] - Blame information for rev 31