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-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
use work.cpu_pack.ALL;
 
ENTITY testbench IS
END testbench;
 
ARCHITECTURE behavior OF testbench IS
 
        COMPONENT cpu_engine
        PORT(   CLK      : in  std_logic;
                        CCK      : in  std_logic;
                        CLR      : in  std_logic;
                        Q_PC   : out std_logic_vector(15 downto 0);
                        Q_OPC  : out std_logic_vector( 7 downto 0);
                        Q_CAT  : out op_category;
                        Q_IMM  : out std_logic_vector(15 downto 0);
                        Q_CYC  : out cycle;
 
                        -- input/output
                        INT      : in  std_logic;
                        IO_ADR   : out std_logic_vector(7 downto 0);
                        IO_RD    : out std_logic;
                        IO_WR    : out std_logic;
                        IO_RDAT  : in  std_logic_vector( 7 downto 0);
 
                        -- memory
                        XM_ADR  : out std_logic_vector(15 downto 0);
                        XM_RDAT : in  std_logic_vector( 7 downto 0);
                        XM_WDAT : out std_logic_vector( 7 downto 0);
                        XM_WE   : out std_logic;
                        XM_CE   : out std_logic;
 
                        -- select signals
                        Q_SX    : out std_logic_vector(1 downto 0);
                        Q_SY    : out std_logic_vector(3 downto 0);
                        Q_OP    : out std_logic_vector(4 downto 0);
                        Q_SA    : out std_logic_vector(4 downto 0);
                        Q_SMQ   : out std_logic;
 
                        -- write enable/select signal
                        Q_WE_RR  : out std_logic;
                        Q_WE_LL  : out std_logic;
                        Q_WE_SP  : out SP_OP;
 
                        Q_RR     : out std_logic_vector(15 downto 0);
                        Q_LL     : out std_logic_vector(15 downto 0);
                        Q_SP     : out std_logic_vector(15 downto 0);
                        HALT       : out std_logic
                );
        END COMPONENT;
 
        signal  CLK      : std_logic;
        signal  CLR      : std_logic;
        signal  Q_PC   : std_logic_vector(15 downto 0);
        signal  Q_OPC  : std_logic_vector( 7 downto 0);
        signal  Q_CAT  : op_category;
        signal  Q_CYC  : cycle;
        signal  Q_IMM  : std_logic_vector(15 downto 0);
 
        signal  Q_SP     : std_logic_vector(15 downto 0);
        signal  Q_LL     : std_logic_vector(15 downto 0);
        signal  Q_RR     : std_logic_vector(15 downto 0);
 
        -- input/output
        signal  INT      : std_logic;
        signal  IO_RD    : std_logic;
        signal  IO_ADR   : std_logic_vector( 7 downto 0);
        signal  IO_WR    : std_logic;
        signal  IO_RDAT  : std_logic_vector( 7 downto 0);
        signal  HALT     : std_logic;
 
                        -- memory
        signal  XM_ADR  : std_logic_vector(15 downto 0);
        signal  XM_RDAT : std_logic_vector( 7 downto 0);
        signal  XM_WDAT : std_logic_vector( 7 downto 0);
        signal  XM_WE   : std_logic;
        signal  XM_CE   : std_logic;
 
                        -- select signals
        signal  Q_SX    : std_logic_vector(1 downto 0);
        signal  Q_SY    : std_logic_vector(3 downto 0);
        signal  Q_OP    : std_logic_vector(4 downto 0);
        signal  Q_SA    : std_logic_vector(4 downto 0);
        signal  Q_SMQ   : std_logic;
 
                        -- write enable/select signal
        signal  Q_WE_RR  : std_logic;
        signal  Q_WE_LL  : std_logic;
        signal  Q_WE_SP  : SP_OP;
 
        signal clk_counter : INTEGER := 0;
 
BEGIN
 
        uut: cpu_engine PORT MAP(
                CLK        => CLK,
                CCK        => CLK,
                CLR        => CLR,
                Q_PC     => Q_PC,
                Q_OPC    => Q_OPC,
                Q_CAT    => Q_CAT,
                Q_IMM    => Q_IMM,
                Q_CYC    => Q_CYC,
 
                INT        => INT,
                IO_ADR     => IO_ADR,
                IO_RD      => IO_RD,
                IO_WR      => IO_WR,
                IO_RDAT    => IO_RDAT,
 
                XM_ADR     => XM_ADR,
                XM_RDAT    => XM_RDAT,
                XM_WDAT    => XM_WDAT,
                XM_WE      => XM_WE,
                XM_CE      => XM_CE,
 
                Q_SX     => Q_SX,
                Q_SY     => Q_SY,
                Q_OP     => Q_OP,
                Q_SA     => Q_SA,
                Q_SMQ    => Q_SMQ,
 
                Q_WE_RR  => Q_WE_RR,
                Q_WE_LL  => Q_WE_LL,
                Q_WE_SP  => Q_WE_SP,
 
                Q_RR     => Q_RR,
                Q_LL     => Q_LL,
                Q_SP     => Q_SP,
                HALT     => HALT
        );
 
-- *** Test Bench - User Defined Section ***
        PROCESS -- clock process for CLK,
        BEGIN
                CLOCK_LOOP : LOOP
                        CLK <= transport '0';
                        WAIT FOR 1 ns;
                        CLK <= transport '1';
                        WAIT FOR 1 ns;
                        WAIT FOR 11 ns;
                        CLK <= transport '0';
                        WAIT FOR 12 ns;
                END LOOP CLOCK_LOOP;
        END PROCESS;
 
        PROCESS(CLK)
        BEGIN
                if (rising_edge(CLK)) then
                        if (Q_CYC = M1) then
                                CLK_COUNTER <= CLK_COUNTER + 1;
                        end if;
 
                        if (XM_ADR(0) = '0') then         IO_RDAT <= X"44";       -- data
                        else                                                    IO_RDAT <= X"01";       -- control
                        end if;
 
                        case CLK_COUNTER is
                                when 0           =>      CLR <= '1';   INT <= '0';
                                when 1          =>      CLR <= '0';
--                              when 20         =>      INT <= '1';
 
 
                                when 1000       =>      CLK_COUNTER <= 0;
                                                                ASSERT (FALSE) REPORT
                                                                        "simulation done (no error)"
                                                                        SEVERITY FAILURE;
                                when others     =>
                        end case;
                end if;
        END PROCESS;
 
END;

Line No.	Rev	Author	Line
1	2	jsauermann
2			`-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003`
3			`--`
4			`-- Notes:`
5			`-- This testbench has been automatically generated using types std_logic and`
6			`-- std_logic_vector for the ports of the unit under test. Xilinx recommends`
7			`-- that these types always be used for the top-level I/O of a design in order`
8			`-- to guarantee that the testbench will bind correctly to the post-implementation`
9			`-- simulation model.`
10			`--`
11			`LIBRARY ieee;`
12			`USE ieee.std_logic_1164.ALL;`
13			`USE ieee.numeric_std.ALL;`
14
15			`use work.cpu_pack.ALL;`
16
17			`ENTITY testbench IS`
18			`END testbench;`
19
20			`ARCHITECTURE behavior OF testbench IS`
21
22			`COMPONENT cpu_engine`
23			`PORT( CLK : in std_logic;`
24			`CCK : in std_logic;`
25			`CLR : in std_logic;`
26			`Q_PC : out std_logic_vector(15 downto 0);`
27			`Q_OPC : out std_logic_vector( 7 downto 0);`
28			`Q_CAT : out op_category;`
29			`Q_IMM : out std_logic_vector(15 downto 0);`
30			`Q_CYC : out cycle;`
31
32			`-- input/output`
33			`INT : in std_logic;`
34			`IO_ADR : out std_logic_vector(7 downto 0);`
35			`IO_RD : out std_logic;`
36			`IO_WR : out std_logic;`
37			`IO_RDAT : in std_logic_vector( 7 downto 0);`
38
39			`-- memory`
40			`XM_ADR : out std_logic_vector(15 downto 0);`
41			`XM_RDAT : in std_logic_vector( 7 downto 0);`
42			`XM_WDAT : out std_logic_vector( 7 downto 0);`
43			`XM_WE : out std_logic;`
44			`XM_CE : out std_logic;`
45
46			`-- select signals`
47			`Q_SX : out std_logic_vector(1 downto 0);`
48			`Q_SY : out std_logic_vector(3 downto 0);`
49			`Q_OP : out std_logic_vector(4 downto 0);`
50			`Q_SA : out std_logic_vector(4 downto 0);`
51			`Q_SMQ : out std_logic;`
52
53			`-- write enable/select signal`
54			`Q_WE_RR : out std_logic;`
55			`Q_WE_LL : out std_logic;`
56			`Q_WE_SP : out SP_OP;`
57
58			`Q_RR : out std_logic_vector(15 downto 0);`
59			`Q_LL : out std_logic_vector(15 downto 0);`
60			`Q_SP : out std_logic_vector(15 downto 0);`
61			`HALT : out std_logic`
62			`);`
63			`END COMPONENT;`
64
65			`signal CLK : std_logic;`
66			`signal CLR : std_logic;`
67			`signal Q_PC : std_logic_vector(15 downto 0);`
68			`signal Q_OPC : std_logic_vector( 7 downto 0);`
69			`signal Q_CAT : op_category;`
70			`signal Q_CYC : cycle;`
71			`signal Q_IMM : std_logic_vector(15 downto 0);`
72
73			`signal Q_SP : std_logic_vector(15 downto 0);`
74			`signal Q_LL : std_logic_vector(15 downto 0);`
75			`signal Q_RR : std_logic_vector(15 downto 0);`
76
77			`-- input/output`
78			`signal INT : std_logic;`
79			`signal IO_RD : std_logic;`
80			`signal IO_ADR : std_logic_vector( 7 downto 0);`
81			`signal IO_WR : std_logic;`
82			`signal IO_RDAT : std_logic_vector( 7 downto 0);`
83			`signal HALT : std_logic;`
84
85			`-- memory`
86			`signal XM_ADR : std_logic_vector(15 downto 0);`
87			`signal XM_RDAT : std_logic_vector( 7 downto 0);`
88			`signal XM_WDAT : std_logic_vector( 7 downto 0);`
89			`signal XM_WE : std_logic;`
90			`signal XM_CE : std_logic;`
91
92			`-- select signals`
93			`signal Q_SX : std_logic_vector(1 downto 0);`
94			`signal Q_SY : std_logic_vector(3 downto 0);`
95			`signal Q_OP : std_logic_vector(4 downto 0);`
96			`signal Q_SA : std_logic_vector(4 downto 0);`
97			`signal Q_SMQ : std_logic;`
98
99			`-- write enable/select signal`
100			`signal Q_WE_RR : std_logic;`
101			`signal Q_WE_LL : std_logic;`
102			`signal Q_WE_SP : SP_OP;`
103
104			`signal clk_counter : INTEGER := 0;`
105
106			`BEGIN`
107
108			`uut: cpu_engine PORT MAP(`
109			`CLK => CLK,`
110			`CCK => CLK,`
111			`CLR => CLR,`
112			`Q_PC => Q_PC,`
113			`Q_OPC => Q_OPC,`
114			`Q_CAT => Q_CAT,`
115			`Q_IMM => Q_IMM,`
116			`Q_CYC => Q_CYC,`
117
118			`INT => INT,`
119			`IO_ADR => IO_ADR,`
120			`IO_RD => IO_RD,`
121			`IO_WR => IO_WR,`
122			`IO_RDAT => IO_RDAT,`
123
124			`XM_ADR => XM_ADR,`
125			`XM_RDAT => XM_RDAT,`
126			`XM_WDAT => XM_WDAT,`
127			`XM_WE => XM_WE,`
128			`XM_CE => XM_CE,`
129
130			`Q_SX => Q_SX,`
131			`Q_SY => Q_SY,`
132			`Q_OP => Q_OP,`
133			`Q_SA => Q_SA,`
134			`Q_SMQ => Q_SMQ,`
135
136			`Q_WE_RR => Q_WE_RR,`
137			`Q_WE_LL => Q_WE_LL,`
138			`Q_WE_SP => Q_WE_SP,`
139
140			`Q_RR => Q_RR,`
141			`Q_LL => Q_LL,`
142			`Q_SP => Q_SP,`
143			`HALT => HALT`
144			`);`
145
146			`-- * Test Bench - User Defined Section *`
147			`PROCESS -- clock process for CLK,`
148			`BEGIN`
149			`CLOCK_LOOP : LOOP`
150			`CLK <= transport '0';`
151			`WAIT FOR 1 ns;`
152			`CLK <= transport '1';`
153			`WAIT FOR 1 ns;`
154			`WAIT FOR 11 ns;`
155			`CLK <= transport '0';`
156			`WAIT FOR 12 ns;`
157			`END LOOP CLOCK_LOOP;`
158			`END PROCESS;`
159
160			`PROCESS(CLK)`
161			`BEGIN`
162			`if (rising_edge(CLK)) then`
163			`if (Q_CYC = M1) then`
164			`CLK_COUNTER <= CLK_COUNTER + 1;`
165			`end if;`
166
167			`if (XM_ADR(0) = '0') then IO_RDAT <= X"44"; -- data`
168			`else IO_RDAT <= X"01"; -- control`
169			`end if;`
170
171			`case CLK_COUNTER is`
172			`when 0 => CLR <= '1'; INT <= '0';`
173			`when 1 => CLR <= '0';`
174			`-- when 20 => INT <= '1';`
175
176
177			`when 1000 => CLK_COUNTER <= 0;`
178			`ASSERT (FALSE) REPORT`
179			`"simulation done (no error)"`
180			`SEVERITY FAILURE;`
181			`when others =>`
182			`end case;`
183			`end if;`
184			`END PROCESS;`
185
186			`END;`

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