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[/] [c16/] [trunk/] [vhdl/] [uart._baudgen.vhd] - Blame information for rev 2

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity uart_baudgen is
        PORT(   CLK_I     : in  std_logic;
                        T2        : in  std_logic;
                        CLR       : in  std_logic;
 
                        RD        : in  std_logic;
                        WR        : in  std_logic;
 
                        TX_DATA   : in  std_logic_vector(7 downto 0);
                        TX_SEROUT : out std_logic;
                        RX_SERIN  : in  std_logic;
                        RX_DATA   : out std_logic_vector(7 downto 0);
                        RX_READY  : out std_logic;
                        TX_BUSY   : out std_logic
                );
end uart_baudgen;
 
architecture Behavioral of uart_baudgen is
 
        COMPONENT baudgen
        Generic(bg_clock_freq : integer; bg_baud_rate : integer);
        PORT(
                CLK_I : IN std_logic;
                CLR   : IN std_logic;
                CE_16 : OUT std_logic
                );
        END COMPONENT;
 
        COMPONENT uart
        PORT(   CLK_I     : in std_logic;
                        CLR       : in std_logic;
                        CE_16     : in std_logic;
 
                        TX_DATA   : in std_logic_vector(7 downto 0);
                        TX_FLAG   : in  std_logic;
                        TX_SEROUT : out std_logic;
                        TX_FLAGQ  : out std_logic;
 
                        RX_SERIN  : in  std_logic;
                        RX_DATA   : out std_logic_vector(7 downto 0);
                        RX_FLAG   : out std_logic
                );
        END COMPONENT;
 
        signal CE_16       : std_logic;
        signal RX_FLAG     : std_logic;
        signal RX_OLD_FLAG : std_logic;
        signal TX_FLAG     : std_logic;
        signal TX_FLAGQ    : std_logic;
        signal LTX_DATA    : std_logic_vector(7 downto 0);
        signal LRX_READY   : std_logic;
 
begin
 
        RX_READY <= LRX_READY;
        TX_BUSY  <= TX_FLAG xor TX_FLAGQ;
 
        baud: baudgen
        GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)
        PORT MAP(
                CLK_I => CLK_I,
                CLR   => CLR,
                CE_16 => CE_16
        );
 
        urt: uart
        PORT MAP(       CLK_I     => CLK_I,
                                CLR       => CLR,
                                CE_16     => CE_16,
                                TX_DATA   => LTX_DATA,
                                TX_FLAG   => TX_FLAG,
                                TX_SEROUT => TX_SEROUT,
                                TX_FLAGQ  => TX_FLAGQ,
                                RX_SERIN  => RX_SERIN,
                                RX_DATA   => RX_DATA,
                                RX_FLAG   => RX_FLAG
                        );
 
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (T2 = '1') then
                                if (CLR = '1') then
                                                TX_FLAG <= '0';
                                                LTX_DATA <= X"33";
                                else
                                        if (RD = '1') then                      -- read Rx data
                                                LRX_READY    <= '0';
                                        end if;
 
                                        if (WR = '1') then                      -- write Tx data
                                                TX_FLAG  <= not TX_FLAG;
                                                LTX_DATA <= TX_DATA;
                                        end if;
 
                                        if (RX_FLAG /= RX_OLD_FLAG) then
                                                LRX_READY <= '1';
                                        end if;
 
                                        RX_OLD_FLAG <= RX_FLAG;
                                end if;
                        end if;
                end if;
        end process;
 
end Behavioral;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`-- Uncomment the following lines to use the declarations that are`
7			`-- provided for instantiating Xilinx primitive components.`
8			`--library UNISIM;`
9			`--use UNISIM.VComponents.all;`
10
11			`entity uart_baudgen is`
12			`PORT( CLK_I : in std_logic;`
13			`T2 : in std_logic;`
14			`CLR : in std_logic;`
15
16			`RD : in std_logic;`
17			`WR : in std_logic;`
18
19			`TX_DATA : in std_logic_vector(7 downto 0);`
20			`TX_SEROUT : out std_logic;`
21			`RX_SERIN : in std_logic;`
22			`RX_DATA : out std_logic_vector(7 downto 0);`
23			`RX_READY : out std_logic;`
24			`TX_BUSY : out std_logic`
25			`);`
26			`end uart_baudgen;`
27
28			`architecture Behavioral of uart_baudgen is`
29
30			`COMPONENT baudgen`
31			`Generic(bg_clock_freq : integer; bg_baud_rate : integer);`
32			`PORT(`
33			`CLK_I : IN std_logic;`
34			`CLR : IN std_logic;`
35			`CE_16 : OUT std_logic`
36			`);`
37			`END COMPONENT;`
38
39			`COMPONENT uart`
40			`PORT( CLK_I : in std_logic;`
41			`CLR : in std_logic;`
42			`CE_16 : in std_logic;`
43
44			`TX_DATA : in std_logic_vector(7 downto 0);`
45			`TX_FLAG : in std_logic;`
46			`TX_SEROUT : out std_logic;`
47			`TX_FLAGQ : out std_logic;`
48
49			`RX_SERIN : in std_logic;`
50			`RX_DATA : out std_logic_vector(7 downto 0);`
51			`RX_FLAG : out std_logic`
52			`);`
53			`END COMPONENT;`
54
55			`signal CE_16 : std_logic;`
56			`signal RX_FLAG : std_logic;`
57			`signal RX_OLD_FLAG : std_logic;`
58			`signal TX_FLAG : std_logic;`
59			`signal TX_FLAGQ : std_logic;`
60			`signal LTX_DATA : std_logic_vector(7 downto 0);`
61			`signal LRX_READY : std_logic;`
62
63			`begin`
64
65			`RX_READY <= LRX_READY;`
66			`TX_BUSY <= TX_FLAG xor TX_FLAGQ;`
67
68			`baud: baudgen`
69			`GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)`
70			`PORT MAP(`
71			`CLK_I => CLK_I,`
72			`CLR => CLR,`
73			`CE_16 => CE_16`
74			`);`
75
76			`urt: uart`
77			`PORT MAP( CLK_I => CLK_I,`
78			`CLR => CLR,`
79			`CE_16 => CE_16,`
80			`TX_DATA => LTX_DATA,`
81			`TX_FLAG => TX_FLAG,`
82			`TX_SEROUT => TX_SEROUT,`
83			`TX_FLAGQ => TX_FLAGQ,`
84			`RX_SERIN => RX_SERIN,`
85			`RX_DATA => RX_DATA,`
86			`RX_FLAG => RX_FLAG`
87			`);`
88
89			`process(CLK_I)`
90			`begin`
91			`if (rising_edge(CLK_I)) then`
92			`if (T2 = '1') then`
93			`if (CLR = '1') then`
94			`TX_FLAG <= '0';`
95			`LTX_DATA <= X"33";`
96			`else`
97			`if (RD = '1') then -- read Rx data`
98			`LRX_READY <= '0';`
99			`end if;`
100
101			`if (WR = '1') then -- write Tx data`
102			`TX_FLAG <= not TX_FLAG;`
103			`LTX_DATA <= TX_DATA;`
104			`end if;`
105
106			`if (RX_FLAG /= RX_OLD_FLAG) then`
107			`LRX_READY <= '1';`
108			`end if;`
109
110			`RX_OLD_FLAG <= RX_FLAG;`
111			`end if;`
112			`end if;`
113			`end if;`
114			`end process;`
115
116			`end Behavioral;`

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[/] [c16/] [trunk/] [vhdl/] [uart._baudgen.vhd] - Blame information for rev 2