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[/] [c16/] [trunk/] [vhdl/] [uart._baudgen.vhd] - Blame information for rev 31

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity uart_baudgen is
        PORT(   CLK_I     : in  std_logic;
                        RST_I     : in  std_logic;
 
                        RD        : in  std_logic;
                        WR        : in  std_logic;
 
                        TX_DATA   : in  std_logic_vector(7 downto 0);
                        TX_SEROUT : out std_logic;
                        RX_SERIN  : in  std_logic;
                        RX_DATA   : out std_logic_vector(7 downto 0);
                        RX_READY  : out std_logic;
                        TX_BUSY   : out std_logic
                );
end uart_baudgen;
 
architecture Behavioral of uart_baudgen is
 
        COMPONENT baudgen
        Generic(bg_clock_freq : integer; bg_baud_rate : integer);
        PORT(   CLK_I : IN std_logic;
                        RST_I : IN std_logic;
                        CE_16 : OUT std_logic
                        );
        END COMPONENT;
 
        COMPONENT uart
        PORT(   CLK_I     : in std_logic;
                        RST_I     : in std_logic;
                        CE_16     : in std_logic;
 
                        TX_DATA   : in std_logic_vector(7 downto 0);
                        TX_FLAG   : in  std_logic;
                        TX_SEROUT : out std_logic;
                        TX_FLAGQ  : out std_logic;
 
                        RX_SERIN  : in  std_logic;
                        RX_DATA   : out std_logic_vector(7 downto 0);
                        RX_FLAG   : out std_logic
                );
        END COMPONENT;
 
        signal CE_16       : std_logic;
        signal RX_FLAG     : std_logic;
        signal RX_OLD_FLAG : std_logic;
        signal TX_FLAG     : std_logic;
        signal TX_FLAGQ    : std_logic;
        signal LTX_DATA    : std_logic_vector(7 downto 0);
        signal LRX_READY   : std_logic;
 
begin
 
        RX_READY <= LRX_READY;
        TX_BUSY  <= TX_FLAG xor TX_FLAGQ;
 
        baud: baudgen
        GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)
        PORT MAP(
                CLK_I => CLK_I,
                RST_I => RST_I,
                CE_16 => CE_16
        );
 
        urt: uart
        PORT MAP(       CLK_I     => CLK_I,
                                RST_I     => RST_I,
                                CE_16     => CE_16,
                                TX_DATA   => LTX_DATA,
                                TX_FLAG   => TX_FLAG,
                                TX_SEROUT => TX_SEROUT,
                                TX_FLAGQ  => TX_FLAGQ,
                                RX_SERIN  => RX_SERIN,
                                RX_DATA   => RX_DATA,
                                RX_FLAG   => RX_FLAG
                        );
 
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (RST_I = '1') then
                                TX_FLAG <= '0';
                                LTX_DATA <= X"33";
                        else
                                if (RD = '1') then                      -- read Rx data
                                        LRX_READY    <= '0';
                                end if;
 
                                if (WR = '1') then                      -- write Tx data
                                        TX_FLAG  <= not TX_FLAG;
                                        LTX_DATA <= TX_DATA;
                                end if;
 
                                if (RX_FLAG /= RX_OLD_FLAG) then
                                        LRX_READY <= '1';
                                end if;
 
                                RX_OLD_FLAG <= RX_FLAG;
                        end if;
                end if;
        end process;
 
end Behavioral;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`-- Uncomment the following lines to use the declarations that are`
7			`-- provided for instantiating Xilinx primitive components.`
8			`--library UNISIM;`
9			`--use UNISIM.VComponents.all;`
10
11			`entity uart_baudgen is`
12			`PORT( CLK_I : in std_logic;`
13	9	jsauermann	`RST_I : in std_logic;`
14	2	jsauermann
15			`RD : in std_logic;`
16			`WR : in std_logic;`
17
18			`TX_DATA : in std_logic_vector(7 downto 0);`
19			`TX_SEROUT : out std_logic;`
20			`RX_SERIN : in std_logic;`
21			`RX_DATA : out std_logic_vector(7 downto 0);`
22			`RX_READY : out std_logic;`
23			`TX_BUSY : out std_logic`
24			`);`
25			`end uart_baudgen;`
26
27			`architecture Behavioral of uart_baudgen is`
28
29			`COMPONENT baudgen`
30			`Generic(bg_clock_freq : integer; bg_baud_rate : integer);`
31	9	jsauermann	`PORT( CLK_I : IN std_logic;`
32			`RST_I : IN std_logic;`
33			`CE_16 : OUT std_logic`
34			`);`
35	2	jsauermann	`END COMPONENT;`
36
37			`COMPONENT uart`
38			`PORT( CLK_I : in std_logic;`
39	9	jsauermann	`RST_I : in std_logic;`
40	2	jsauermann	`CE_16 : in std_logic;`
41
42			`TX_DATA : in std_logic_vector(7 downto 0);`
43			`TX_FLAG : in std_logic;`
44			`TX_SEROUT : out std_logic;`
45			`TX_FLAGQ : out std_logic;`
46
47			`RX_SERIN : in std_logic;`
48			`RX_DATA : out std_logic_vector(7 downto 0);`
49			`RX_FLAG : out std_logic`
50			`);`
51			`END COMPONENT;`
52
53			`signal CE_16 : std_logic;`
54			`signal RX_FLAG : std_logic;`
55			`signal RX_OLD_FLAG : std_logic;`
56			`signal TX_FLAG : std_logic;`
57			`signal TX_FLAGQ : std_logic;`
58			`signal LTX_DATA : std_logic_vector(7 downto 0);`
59			`signal LRX_READY : std_logic;`
60
61			`begin`
62
63			`RX_READY <= LRX_READY;`
64			`TX_BUSY <= TX_FLAG xor TX_FLAGQ;`
65
66			`baud: baudgen`
67			`GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)`
68			`PORT MAP(`
69			`CLK_I => CLK_I,`
70	9	jsauermann	`RST_I => RST_I,`
71	2	jsauermann	`CE_16 => CE_16`
72			`);`
73
74			`urt: uart`
75			`PORT MAP( CLK_I => CLK_I,`
76	9	jsauermann	`RST_I => RST_I,`
77	2	jsauermann	`CE_16 => CE_16,`
78			`TX_DATA => LTX_DATA,`
79			`TX_FLAG => TX_FLAG,`
80			`TX_SEROUT => TX_SEROUT,`
81			`TX_FLAGQ => TX_FLAGQ,`
82			`RX_SERIN => RX_SERIN,`
83			`RX_DATA => RX_DATA,`
84			`RX_FLAG => RX_FLAG`
85			`);`
86
87			`process(CLK_I)`
88			`begin`
89			`if (rising_edge(CLK_I)) then`
90	9	jsauermann	`if (RST_I = '1') then`
91			`TX_FLAG <= '0';`
92			`LTX_DATA <= X"33";`
93			`else`
94			`if (RD = '1') then -- read Rx data`
95			`LRX_READY <= '0';`
96			`end if;`
97	2	jsauermann
98	9	jsauermann	`if (WR = '1') then -- write Tx data`
99			`TX_FLAG <= not TX_FLAG;`
100			`LTX_DATA <= TX_DATA;`
101			`end if;`
102	2	jsauermann
103	9	jsauermann	`if (RX_FLAG /= RX_OLD_FLAG) then`
104			`LRX_READY <= '1';`
105			`end if;`
106	2	jsauermann
107	9	jsauermann	`RX_OLD_FLAG <= RX_FLAG;`
108	2	jsauermann	`end if;`
109			`end if;`
110			`end process;`
111
112			`end Behavioral;`

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[/] [c16/] [trunk/] [vhdl/] [uart._baudgen.vhd] - Blame information for rev 31