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[/] [c16/] [trunk/] [vhdl/] [uart.vhd] - Blame information for rev 26

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1 2 jsauermann
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--  Uncomment the following lines to use the declarations that are
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--  provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity uart is
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        PORT(   CLK_I     : in std_logic;
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                        RST_I     : in std_logic;
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                        CE_16     : in std_logic;
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                        TX_DATA   : in std_logic_vector(7 downto 0);
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                        TX_FLAG   : in std_logic;
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                        TX_SEROUT : out std_logic;
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                        TX_FLAGQ  : out std_logic;
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                        RX_SERIN  : in  std_logic;
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                        RX_DATA   : out std_logic_vector(7 downto 0);
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                        RX_FLAG   : out std_logic
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                );
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end uart;
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architecture Behavioral of uart is
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        COMPONENT uart_tx
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        PORT(   CLK_I      : IN  std_logic;
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                        RST_I      : IN  std_logic;
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                        CE_16      : IN  std_logic;
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                        DATA       : IN  std_logic_vector(7 downto 0);
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                        DATA_FLAG  : IN  std_logic;
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                        SER_OUT    : OUT std_logic;
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                        DATA_FLAGQ : OUT std_logic
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                );
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        END COMPONENT;
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        COMPONENT uart_rx
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        PORT(   CLK_I     : IN std_logic;
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                        RST_I     : IN std_logic;
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                        CE_16     : IN std_logic;
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                        SER_IN    : IN std_logic;
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                        DATA      : OUT std_logic_vector(7 downto 0);
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                        DATA_FLAG : OUT std_logic
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                );
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        END COMPONENT;
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begin
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        tx: uart_tx
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        PORT MAP(       CLK_I      => CLK_I,
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                                RST_I      => RST_I,
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                                CE_16      => CE_16,
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                                DATA       => TX_DATA,
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                                DATA_FLAG  => TX_FLAG,
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                                SER_OUT    => TX_SEROUT,
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                                DATA_FLAGQ => TX_FLAGQ
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                        );
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        rx: uart_rx
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        PORT MAP(       CLK_I     => CLK_I,
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                                RST_I     => RST_I,
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                                CE_16     => CE_16,
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                                DATA      => RX_DATA,
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                                SER_IN    => RX_SERIN,
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                                DATA_FLAG => RX_FLAG
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                        );
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end Behavioral;

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