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[/] [c16/] [trunk/] [vhdl/] [uart_rx.vhd] - Blame information for rev 31

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity UART_RX is
        PORT(   CLK_I     : in  std_logic;
                        RST_I     : in  std_logic;
                        CE_16     : in  std_logic;                      -- 16 times baud rate 
                        SER_IN    : in  std_logic;                      -- Serial input line
 
                        DATA      : out std_logic_vector(7 downto 0);
                        DATA_FLAG : out std_logic                       -- toggle on every byte received
   );
end UART_RX;
 
architecture RX_UART_arch of UART_RX is
 
        signal POSITION   : std_logic_vector(7 downto 0);                --  sample position
        signal BUF        : std_logic_vector(9 downto 0);
        signal LDATA_FLAG : std_logic;
        signal SER_IN1    : std_logic;                                                  -- double clock the input
        signal SER_HOT    : std_logic;                                                  -- double clock the input
 
begin
 
        -- double clock the input data...
        --
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (RST_I = '1') then
                                SER_IN1 <= '1';
                                SER_HOT <= '1';
                        else
                                SER_IN1 <= SER_IN;
                                SER_HOT <= SER_IN1;
                        end if;
                end if;
        end process;
 
        DATA_FLAG <= LDATA_FLAG;
 
        process(CLK_I, POSITION)
 
                variable START_BIT : boolean;
                variable STOP_BIT  : boolean;
                variable STOP_POS  : boolean;
 
        begin
                START_BIT := POSITION(7 downto 4) = X"0";
                STOP_BIT  := POSITION(7 downto 4) = X"9";
                STOP_POS  := STOP_BIT and POSITION(3 downto 2) = "11";          -- 3/4 of stop bit
 
                if (rising_edge(CLK_I)) then
                        if (RST_I = '1') then
                                LDATA_FLAG <= '0';
                                POSITION   <= X"00";    -- idle
                                BUF        <= "1111111111";
                                DATA       <= "00000000";
                        elsif (CE_16 = '1') then
                                if (POSITION = X"00") then                      -- uart idle
                                        BUF    <= "1111111111";
                                        if (SER_HOT = '0')  then         -- start bit received
                                                POSITION <= X"01";
                                        end if;
                                else
                                        POSITION <= POSITION + X"01";
                                        if (POSITION(3 downto 0) = "0111") then          -- 1/2 of the bit
                                                BUF <= SER_HOT & BUF(9 downto 1);               -- sample data
                                                -- validate start bit
                                                --
                                                if (START_BIT and SER_HOT = '1') then   -- inside start bit
                                                        POSITION <= X"00";
                                                end if;
 
                                                if (STOP_BIT) then                                      -- inside stop bit
                                                        DATA <= BUF(9 downto 2);
                                                end if;
                                        elsif (STOP_POS) then   -- 3/4 of stop bit
                                                LDATA_FLAG <= LDATA_FLAG xor (BUF(9) and not BUF(0));
                                                POSITION <= X"00";
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
end RX_UART_arch;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3			`use IEEE.STD_LOGIC_UNSIGNED.all;`
4
5			`entity UART_RX is`
6			`PORT( CLK_I : in std_logic;`
7	9	jsauermann	`RST_I : in std_logic;`
8	2	jsauermann	`CE_16 : in std_logic; -- 16 times baud rate`
9			`SER_IN : in std_logic; -- Serial input line`
10
11			`DATA : out std_logic_vector(7 downto 0);`
12			`DATA_FLAG : out std_logic -- toggle on every byte received`
13			`);`
14			`end UART_RX;`
15
16			`architecture RX_UART_arch of UART_RX is`
17
18			`signal POSITION : std_logic_vector(7 downto 0); -- sample position`
19			`signal BUF : std_logic_vector(9 downto 0);`
20			`signal LDATA_FLAG : std_logic;`
21			`signal SER_IN1 : std_logic; -- double clock the input`
22			`signal SER_HOT : std_logic; -- double clock the input`
23
24			`begin`
25
26			`-- double clock the input data...`
27			`--`
28			`process(CLK_I)`
29			`begin`
30			`if (rising_edge(CLK_I)) then`
31	9	jsauermann	`if (RST_I = '1') then`
32	2	jsauermann	`SER_IN1 <= '1';`
33			`SER_HOT <= '1';`
34			`else`
35			`SER_IN1 <= SER_IN;`
36			`SER_HOT <= SER_IN1;`
37			`end if;`
38			`end if;`
39			`end process;`
40
41			`DATA_FLAG <= LDATA_FLAG;`
42
43			`process(CLK_I, POSITION)`
44
45			`variable START_BIT : boolean;`
46			`variable STOP_BIT : boolean;`
47			`variable STOP_POS : boolean;`
48
49			`begin`
50			`START_BIT := POSITION(7 downto 4) = X"0";`
51			`STOP_BIT := POSITION(7 downto 4) = X"9";`
52			`STOP_POS := STOP_BIT and POSITION(3 downto 2) = "11"; -- 3/4 of stop bit`
53
54			`if (rising_edge(CLK_I)) then`
55	9	jsauermann	`if (RST_I = '1') then`
56	2	jsauermann	`LDATA_FLAG <= '0';`
57			`POSITION <= X"00"; -- idle`
58			`BUF <= "1111111111";`
59			`DATA <= "00000000";`
60			`elsif (CE_16 = '1') then`
61			`if (POSITION = X"00") then -- uart idle`
62			`BUF <= "1111111111";`
63			`if (SER_HOT = '0') then -- start bit received`
64			`POSITION <= X"01";`
65			`end if;`
66			`else`
67			`POSITION <= POSITION + X"01";`
68			`if (POSITION(3 downto 0) = "0111") then -- 1/2 of the bit`
69			`BUF <= SER_HOT & BUF(9 downto 1); -- sample data`
70			`-- validate start bit`
71			`--`
72			`if (START_BIT and SER_HOT = '1') then -- inside start bit`
73			`POSITION <= X"00";`
74			`end if;`
75
76			`if (STOP_BIT) then -- inside stop bit`
77			`DATA <= BUF(9 downto 2);`
78			`end if;`
79			`elsif (STOP_POS) then -- 3/4 of stop bit`
80			`LDATA_FLAG <= LDATA_FLAG xor (BUF(9) and not BUF(0));`
81			`POSITION <= X"00";`
82			`end if;`
83			`end if;`
84			`end if;`
85			`end if;`
86			`end process;`
87
88			`end RX_UART_arch;`

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[/] [c16/] [trunk/] [vhdl/] [uart_rx.vhd] - Blame information for rev 31