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[/] [c16/] [trunk/] [vhdl/] [uart_tx.vhd] - Blame information for rev 29

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity UART_TX is
        PORT(   CLK_I      : in  std_logic;
                        RST_I      : in  std_logic;                                                     -- RESET
                        CE_16      : in  std_logic;                                                     -- BUAD rate clock
                        DATA       : in  std_logic_vector(7 downto 0);           -- DATA to be sent
                        DATA_FLAG  : in  std_logic;                                                     -- toggle to send data
                        SER_OUT    : out std_logic;                                                     -- Serial output line
                        DATA_FLAGQ : out std_logic                                                      -- Transmitting Flag
                );
end UART_TX;
 
 
architecture TX_UART_arch of UART_TX is
 
        signal BUF      : std_logic_vector(7 downto 0);
        signal TODO     : integer range 0 to 9;                  -- bits to send
        signal FLAGQ    : std_logic;
        signal CE_1     : std_logic;
        signal C16      : std_logic_vector(3 downto 0);
 
begin
 
        DATA_FLAGQ <= FLAGQ;
 
        -- generate a CE_1 every 16 CE_16...
        --
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        CE_1 <= '0';
                        if (RST_I = '1') then
                                C16 <= "0000";
                        elsif (CE_16 = '1') then
                                if (C16 = "1111") then
                                        CE_1 <= '1';
                                end if;
                                C16 <= C16 + "0001";
                        end if;
                end if;
        end process;
 
        process(CLK_I)
        begin
                if (rising_edge(CLK_I)) then
                        if (RST_I = '1') then
                                SER_OUT     <= '1';
                                BUF         <= "11111111";
                                TODO        <= 0;
                                FLAGQ       <= DATA_FLAG;                                       -- idle
                        elsif (CE_1 = '1') then
                                if (TODO > 0) then                                                       -- transmitting
                                        SER_OUT <= BUF(0);               -- next bit
                                        BUF     <= '1' & BUF(7 downto 1);
                                        if (TODO = 1) then
                                                FLAGQ   <= DATA_FLAG;
                                        end if;
                                        TODO    <= TODO - 1;
                                elsif (FLAGQ /= DATA_FLAG) then                         -- new byte
                                        SER_OUT <= '0';                  -- start bit
                                        TODO    <= 9;
                                        BUF     <= DATA;
                                end if;
                        end if;
                end if;
        end process;
 
end TX_UART_arch;

Line No.	Rev	Author	Line
1	2	jsauermann	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3			`use IEEE.STD_LOGIC_UNSIGNED.all;`
4
5			`entity UART_TX is`
6			`PORT( CLK_I : in std_logic;`
7	9	jsauermann	`RST_I : in std_logic; -- RESET`
8	2	jsauermann	`CE_16 : in std_logic; -- BUAD rate clock`
9			`DATA : in std_logic_vector(7 downto 0); -- DATA to be sent`
10			`DATA_FLAG : in std_logic; -- toggle to send data`
11			`SER_OUT : out std_logic; -- Serial output line`
12			`DATA_FLAGQ : out std_logic -- Transmitting Flag`
13			`);`
14			`end UART_TX;`
15
16
17			`architecture TX_UART_arch of UART_TX is`
18
19			`signal BUF : std_logic_vector(7 downto 0);`
20			`signal TODO : integer range 0 to 9; -- bits to send`
21			`signal FLAGQ : std_logic;`
22			`signal CE_1 : std_logic;`
23			`signal C16 : std_logic_vector(3 downto 0);`
24
25			`begin`
26
27			`DATA_FLAGQ <= FLAGQ;`
28
29			`-- generate a CE_1 every 16 CE_16...`
30			`--`
31			`process(CLK_I)`
32			`begin`
33			`if (rising_edge(CLK_I)) then`
34			`CE_1 <= '0';`
35	9	jsauermann	`if (RST_I = '1') then`
36	2	jsauermann	`C16 <= "0000";`
37			`elsif (CE_16 = '1') then`
38			`if (C16 = "1111") then`
39			`CE_1 <= '1';`
40			`end if;`
41			`C16 <= C16 + "0001";`
42			`end if;`
43			`end if;`
44			`end process;`
45
46			`process(CLK_I)`
47			`begin`
48			`if (rising_edge(CLK_I)) then`
49	9	jsauermann	`if (RST_I = '1') then`
50	2	jsauermann	`SER_OUT <= '1';`
51			`BUF <= "11111111";`
52			`TODO <= 0;`
53			`FLAGQ <= DATA_FLAG; -- idle`
54			`elsif (CE_1 = '1') then`
55			`if (TODO > 0) then -- transmitting`
56			`SER_OUT <= BUF(0); -- next bit`
57			`BUF <= '1' & BUF(7 downto 1);`
58			`if (TODO = 1) then`
59			`FLAGQ <= DATA_FLAG;`
60			`end if;`
61			`TODO <= TODO - 1;`
62			`elsif (FLAGQ /= DATA_FLAG) then -- new byte`
63			`SER_OUT <= '0'; -- start bit`
64			`TODO <= 9;`
65			`BUF <= DATA;`
66			`end if;`
67			`end if;`
68			`end if;`
69			`end process;`
70
71			`end TX_UART_arch;`

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[/] [c16/] [trunk/] [vhdl/] [uart_tx.vhd] - Blame information for rev 29