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--------------------------------------------------------------------------------
-- Designer:      Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date:   01/31/2008
-- Last Update:   03/28/2008
-- Project Name:  camellia-vhdl
-- Description:   Control unit and key handling
--
-- Copyright (C) 2008  Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity control is
    port    (
            clk        : in  STD_LOGIC;
            reset      : in  STD_LOGIC;
 
            data_in    : in  STD_LOGIC_VECTOR (0 to 127);
            enc_dec    : in  STD_LOGIC;
            data_rdy   : in  STD_LOGIC;
            data_acq   : out STD_LOGIC;
 
            key_in     : in  STD_LOGIC_VECTOR (0 to 255);
            k_len      : in  STD_LOGIC_VECTOR (0 to 1);
            key_rdy    : in  STD_LOGIC;
            key_acq    : out STD_LOGIC;
 
            data_to    : out STD_LOGIC_VECTOR (0 to 127); -- data to datapath
            output_rdy : out STD_LOGIC;
            k1         : out STD_LOGIC_VECTOR (0 to 63);
            k2         : out STD_LOGIC_VECTOR (0 to 63);
            newdata    : out STD_LOGIC;
            sel        : out STD_LOGIC;
            pre_xor    : out STD_LOGIC_VECTOR (0 to 127);
            post_xor   : out STD_LOGIC_VECTOR (0 to 127);
            data_from  : in  STD_LOGIC_VECTOR (0 to 127)  -- data from datapath
            );
end control;
 
architecture RTL of control is
 
    type STATUS is (KEYa, KEYb, KEYc, KEYd, KEYe, KEYf,
                    SIX1a, SIX1b, SIX1c, SIX1d, SIX1e, SIX1f,
                    FL1,
                    SIX2a, SIX2b, SIX2c, SIX2d, SIX2e, SIX2f,
                    FL2,
                    SIX3a, SIX3b, SIX3c, SIX3d, SIX3e, SIX3f,
                    FL3,
                    SIX4a, SIX4b, SIX4c, SIX4d, SIX4e, SIX4f,
                    WT
                    );
    signal PS, NS    : STATUS;
 
    type K1_TYPE is (SIG1, SIG2, SIG3, SIG4, SIG5, SIG6,
                     KL_L, KL_R, KR_L, KR_R, KA_L, KA_R, KB_L, KB_R);
    signal k1_sel    : K1_TYPE;
    type K2_TYPE is (KL_L, KL_R, KR_L, KR_R, KA_L, KA_R, KB_L, KB_R);
    signal k2_sel    : K2_TYPE;
    type POSTXOR_TYPE is (KL, KA, KB, ZERO);
    signal postxor_sel    : POSTXOR_TYPE;
    type PREXOR_TYPE is (KL, KR, KA, KB, ZERO);
    signal prexor_sel    : PREXOR_TYPE;
 
    -- keys
    signal reg_kl    : STD_LOGIC_VECTOR (0 to 127);
    signal reg_kr    : STD_LOGIC_VECTOR (0 to 127);
    signal reg_ka    : STD_LOGIC_VECTOR (0 to 127);
    signal reg_kb    : STD_LOGIC_VECTOR (0 to 127);
    --keys shifted each step
    signal reg_kl_s  : STD_LOGIC_VECTOR (0 to 127);
    signal reg_kr_s  : STD_LOGIC_VECTOR (0 to 127);
    signal reg_ka_s  : STD_LOGIC_VECTOR (0 to 127);
    signal reg_kb_s  : STD_LOGIC_VECTOR (0 to 127);
 
    signal reg_k_len   : STD_LOGIC_VECTOR (0 to 1);
    signal reg_enc_dec : STD_LOGIC;
 
    -- input constant
    constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";
    constant KLEN_192 : STD_LOGIC_VECTOR (0 to 1) := "01";
    constant KLEN_256 : STD_LOGIC_VECTOR (0 to 1) := "10";
    constant ENC      : STD_LOGIC := '0';
    constant DEC      : STD_LOGIC := '1';
    constant SEL_F    : STD_LOGIC := '0';
    constant SEL_FL   : STD_LOGIC := '1';
 
    -- constant keys
    constant sigma1 : STD_LOGIC_VECTOR (0 to 63) := X"A09E667F3BCC908B";
    constant sigma2 : STD_LOGIC_VECTOR (0 to 63) := X"B67AE8584CAA73B2";
    constant sigma3 : STD_LOGIC_VECTOR (0 to 63) := X"C6EF372FE94F82BE";
    constant sigma4 : STD_LOGIC_VECTOR (0 to 63) := X"54FF53A5F1D36F1C";
    constant sigma5 : STD_LOGIC_VECTOR (0 to 63) := X"10E527FADE682D1D";
    constant sigma6 : STD_LOGIC_VECTOR (0 to 63) := X"B05688C2B3E6C1FD";
 
begin
 
    with k1_sel select
        k1 <=   sigma1                 when SIG1,
                sigma2                 when SIG2,
                sigma3                 when SIG3,
                sigma4                 when SIG4,
                sigma5                 when SIG5,
                sigma6                 when SIG6,
                reg_kl_s(0 to 63)      when KL_L,
                reg_kl_s(64 to 127)    when KL_R,
                reg_kr_s(0 to 63)      when KR_L,
                reg_kr_s(64 to 127)    when KR_R,
                reg_ka_s(0 to 63)      when KA_L,
                reg_ka_s(64 to 127)    when KA_R,
                reg_kb_s(0 to 63)      when KB_L,
                reg_kb_s(64 to 127)    when others;
    with k2_sel select
        k2 <=   reg_kl_s(0 to 63)      when KL_L,
                reg_kl_s(64 to 127)    when KL_R,
                reg_kr_s(0 to 63)      when KR_L,
                reg_kr_s(64 to 127)    when KR_R,
                reg_ka_s(0 to 63)      when KA_L,
                reg_ka_s(64 to 127)    when KA_R,
                reg_kb_s(0 to 63)      when KB_L,
                reg_kb_s(64 to 127)    when others;
 
    with postxor_sel select
        post_xor <= reg_kl_s(64 to 127) & reg_kl_s(0 to 63)   when KL,
                    reg_ka_s(64 to 127) & reg_ka_s(0 to 63)   when KA,
                    reg_kb_s(64 to 127) & reg_kb_s(0 to 63)   when KB,
                    (others=>'0')                             when others;
 
    with prexor_sel select
        pre_xor  <=   reg_kl_s           when KL,
                      reg_kr_s           when KR,
                      reg_ka_s           when KA,
                      reg_kb_s           when KB,
                      (others=>'0')      when others;
 
 
    REGISTERS_UPDATE : process(reset, clk)
        variable coming_from_key : STD_LOGIC;
    begin
    if (reset = '1') then
        reg_kl           <= (others=>'0');
        reg_kr           <= (others=>'0');
        reg_ka           <= (others=>'0');
        reg_kb           <= (others=>'0');
        reg_kl_s         <= (others=>'0');
        reg_kr_s         <= (others=>'0');
        reg_ka_s         <= (others=>'0');
        reg_kb_s         <= (others=>'0');
        reg_enc_dec      <= '0';
        reg_k_len        <= (others=>'0');
        output_rdy       <= '0';
        coming_from_key  := '0';
    else
        if (clk'event and clk = '1') then
            case PS is
                when KEYa =>
                    coming_from_key  := '1';
                    reg_kl           <= key_in(0 to 127);
                    reg_kl_s         <= key_in(0 to 127);
                    reg_k_len        <= k_len;
                    case k_len is
                        when KLEN_192 =>
                            reg_kr    <= key_in(128 to 191) & not (key_in(128 to 191));
                            reg_kr_s  <= key_in(128 to 191) & not (key_in(128 to 191));
                        when KLEN_256 =>
                            reg_kr    <= key_in(128 to 255);
                            reg_kr_s  <= key_in(128 to 255);
                        when others =>
                            reg_kr    <= (others=>'0');
                            reg_kr_s  <= (others=>'0');
                    end case;
                    k1_sel    <= SIG1;
                when KEYb =>
                    k1_sel    <= SIG2;
                when KEYc =>
                    k1_sel    <= SIG3;
                when KEYd =>
                    k1_sel    <= SIG4;
                when KEYe =>
                    reg_ka    <= data_from;
                    reg_ka_s  <= data_from;
                    k1_sel    <= SIG5;
                when KEYf =>
                    k1_sel    <= SIG6;
                when SIX1a =>
                    if (enc_dec = ENC) then
                        if (coming_from_key = '1') then
                            if (reg_k_len = KLEN_128) then
                                reg_ka   <= data_from;
                                reg_ka_s <= data_from;
                            else
                                reg_kb   <= data_from;
                                reg_kb_s <= data_from;
                            end if;
                        else
                            reg_ka_s <= reg_ka;
                            reg_kb_s <= reg_kb;
                            reg_kl_s <= reg_kl;
                            reg_kr_s <= reg_kr;
                        end if;
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_L;
                        else
                            k1_sel <= KB_L;
                        end if;
                    else -- DEC
                        if (coming_from_key = '1') then
                            if (reg_k_len = KLEN_128) then
                                reg_ka   <= data_from;
                                reg_ka_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
                            else
                                reg_kb   <= data_from;
                                reg_kb_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
                                reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
                                reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
                            end if;
                            reg_kl_s  <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
                        else
                            reg_ka_s <= reg_ka(111 to 127) & reg_ka(0 to 110); -- >>> 17
                            reg_kb_s <= reg_kb(111 to 127) & reg_kb(0 to 110); -- >>> 17
                            reg_kl_s <= key_in(111 to 127) & key_in(0 to 110); --kl >>> 17
                            reg_kr_s <= reg_kr(111 to 127) & reg_kr(0 to 110); -- >>> 17
                        end if;
                        k1_sel <= KL_R;
                    end if;
                    reg_enc_dec <= enc_dec;
                when SIX1b =>
                    coming_from_key  := '0';
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_R;
                        else
                            k1_sel <= KB_R;
                        end if;
                    else -- DEC
                        k1_sel <= KL_L; -- for each value of reg_k_len
                    end if;
                when SIX1c =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_L;
                            reg_kl_s  <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
                        else
                            k1_sel <= KR_L;
                            reg_kr_s  <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
                        end if;
                    else -- DEC
                        reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
                        k1_sel <= KA_R; -- for each value of reg_k_len
                    end if;
                when SIX1d =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_R;
                        else
                            k1_sel <= KR_R;
                        end if;
                    else -- DEC
                        k1_sel <= KA_L; -- for each value of reg_k_len
                    end if;
                when SIX1e =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            reg_ka_s  <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
                        else
                            reg_ka_s  <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
                        end if;
                        k1_sel <= KA_L;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
                            k1_sel <= KL_R;
                        else
                            reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
                            k1_sel <= KR_R;
                        end if;
                    end if;
                when SIX1f =>
                    if (reg_enc_dec = ENC) then
                        k1_sel <= KA_R;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_L;
                        else
                            k1_sel <= KR_L;
                        end if;
                    end if;
                when FL1 =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_L;
                            k2_sel <= KA_R;
                            reg_kl_s  <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
                            reg_ka_s  <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
                        else
                            k1_sel <= KR_L;
                            k2_sel <= KR_R;
                            reg_kb_s  <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
                            reg_kr_s  <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
                        end if;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_R;
                            k2_sel <= KL_L;
                        else
                            k1_sel <= KA_R;
                            k2_sel <= KA_L;
                        end if;
                        reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
                        reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
                    end if;
                when SIX2a =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_L;
                            reg_kl_s  <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
                        else
                            k1_sel <= KB_L;
                            reg_kb_s  <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
                            reg_kl_s  <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
                        end if;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_R;
                            reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
                        else
                            k1_sel <= KL_R;
                            reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
                            reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
                        end if;
                    end if;
                when SIX2b =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_R;
                        else
                            k1_sel <= KB_R;
                            reg_kl_s  <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
                        end if;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_L;
                        else
                            k1_sel <= KL_L;
                            reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
                        end if;
                    end if;
                when SIX2c =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_L;
                            reg_ka_s  <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
                        else
                            k1_sel <= KL_L;
                            reg_kl_s  <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
                        end if;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_R;
                            reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
                        else
                            k1_sel <= KB_R;
                            reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
                        end if;
                    end if;
                when SIX2d =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            reg_kl_s  <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
                        else
                            reg_ka_s  <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
                        end if;
                        k1_sel <= KL_R;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_L;
                            reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
                        else
                            k1_sel <= KB_L;
                            reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
                        end if;
                    end if;
                when SIX2e =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            reg_ka_s  <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
                        else
                            reg_ka_s  <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
                        end if;
                        k1_sel <= KA_L;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_R;
                            reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
                        else
                            k1_sel <= KR_R;
                            reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
                        end if;
                    end if;
                when SIX2f =>
                    if (reg_enc_dec = ENC) then
                        k1_sel <= KA_R;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_L;
                        else
                            k1_sel <= KR_L;
                        end if;
                    end if;
                when FL2 =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            reg_kl_s  <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
                        else
                            reg_kr_s  <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
                            reg_kl_s  <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
                        end if;
                        k1_sel <= KL_L;
                        k2_sel <= KL_R;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_R;
                            k2_sel <= KA_L;
                            reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
                        else
                            k1_sel <= KL_R;
                            k2_sel <= KL_L;
                            reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
                            reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
                        end if;
                    end if;
                when SIX3a =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_L;
                            reg_kl_s  <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
                        else
                            k1_sel <= KR_L;
                            reg_kr_s  <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
                        end if;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_R;
                        else
                            k1_sel <= KA_R;
                        end if;
                        reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
                    end if;
                when SIX3b =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_R;
                            reg_ka_s  <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
                        else
                            k1_sel <= KR_R;
                            reg_kb_s  <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
                        end if;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_L;
                            reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
                        else
                            k1_sel <= KA_L;
                        end if;
                    end if;
                when SIX3c =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_L;
                            reg_ka_s  <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
                        else
                            k1_sel <= KB_L;
                            reg_kb_s  <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
                        end if;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_R;
                        else
                            k1_sel <= KL_R;
                        end if;
                        reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
                    end if;
                when SIX3d =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_R;
                        else
                            k1_sel <= KB_R;
                        end if;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KL_L;
                        else
                            k1_sel <= KL_L;
                            reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
                        end if;
                    end if;
                when SIX3e =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            reg_kl_s  <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
                        else
                            reg_kl_s  <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
                        end if;
                        k1_sel <= KL_L;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_R;
                            reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
                        else
                            k1_sel <= KB_R;
                            reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
                        end if;
                    end if;
                when SIX3f =>
                    if (reg_enc_dec = ENC) then
                        if (reg_k_len = KLEN_128) then
                            reg_ka_s  <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
                        else
                            reg_ka_s  <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
                        end if;
                        k1_sel <= KL_R;
                    else -- DEC
                        if (reg_k_len = KLEN_128) then
                            k1_sel <= KA_L;
                            reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
                        else
                            k1_sel <= KB_L;
                            reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
                        end if;
                    end if;
                when FL3 =>
                    if (reg_enc_dec = ENC) then
                        k1_sel  <= KA_L;
                        k2_sel  <= KA_R;
                        reg_kr_s  <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
                        reg_ka_s  <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
                    else -- DEC
                        k1_sel  <= KR_R;
                        k2_sel  <= KR_L;
                        reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
                        reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
                    end if;
                when SIX4a =>
                    if (reg_enc_dec = ENC) then
                        k1_sel <= KR_L;
                        reg_kr_s  <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
                    else -- DEC
                        k1_sel <= KA_R;
                        reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
                    end if;
                when SIX4b =>
                    if (reg_enc_dec = ENC) then
                        k1_sel <= KR_R;
                    else -- DEC
                        k1_sel <= KA_L;
                    end if;
                when SIX4c =>
                    if (reg_enc_dec = ENC) then
                        k1_sel <= KA_L;
                        reg_ka_s  <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
                    else -- DEC
                        k1_sel <= KR_R;
                        reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
                    end if;
                when SIX4d =>
                    if (reg_enc_dec = ENC) then
                        k1_sel <= KA_R;
                        reg_kl_s  <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
                        reg_kb_s  <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
                    else -- DEC
                        k1_sel <= KR_L;
                        reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
                        reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
                    end if;
                when SIX4e =>
                    if (reg_enc_dec = ENC) then
                        k1_sel <= KL_L;
                        reg_kl_s  <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
                        reg_kb_s  <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
                    else -- DEC
                        k1_sel <= KB_R;
                        reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
                        reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
                    end if;
                when SIX4f =>
                    if (reg_enc_dec = ENC) then
                        k1_sel <= KL_R;
                        reg_kb_s  <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
                    else -- DEC
                        k1_sel <= KB_L;
                        reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
                    end if;
                when WT =>
                    -- do nothing
            end case;
 
            if (PS = KEYa) then
                data_to <= key_in(0 to 127); --kl
            else
                data_to <= data_in;
            end if;
 
            case PS is
                when KEYc =>
                    prexor_sel <= KL;
                when KEYa | KEYe =>
                    prexor_sel <= KR;
                when SIX1a =>
                    if (enc_dec = ENC) then
                        prexor_sel <= KL;
                    else
                        if (reg_k_len = KLEN_128) then
                            prexor_sel <= KA;
                        else
                            prexor_sel <= KB;
                        end if;
                    end if;
                when others =>
                    prexor_sel <= ZERO;
            end case;
 
            case PS is
                when SIX3f =>
                    if (reg_k_len = KLEN_128) then
                        if (reg_enc_dec = ENC) then
                            postxor_sel <= KA;
                        else
                            postxor_sel <= KL;
                        end if;
                    else
                        postxor_sel <= ZERO;
                    end if;
                when SIX4f =>
                    if (reg_enc_dec = ENC) then
                        postxor_sel <= KB;
                    else
                        postxor_sel <= KL;
                    end if;
                when others =>
                    postxor_sel <= ZERO;
            end case;
 
            if (PS = SIX1a or PS = KEYa) then
                newdata <= '1';
            else
                newdata <= '0';
            end if;
 
            if ((PS = SIX3f and reg_k_len = KLEN_128) or PS = SIX4f) then
                output_rdy <= '1';
            else
                output_rdy <= '0';
            end if;
 
            if (PS = FL1 or PS = FL2 or PS = FL3) then
                sel <= SEL_FL;
            else
                sel <= SEL_F;
            end if;
 
            if (PS = KEYb) then
                key_acq   <=  '1';
            else
                key_acq   <=  '0';
            end if;
 
            if (PS = SIX1b) then
                data_acq   <=  '1';
            else
                data_acq   <=  '0';
            end if;
 
        end if;
    end if;
 
    end process;
 
    STATE_UPDATE: process (reset, clk)
    begin
 
        if (reset = '1') then
            PS <= KEYa;
        else
            if (clk'event and clk = '1') then
                PS <= NS;
            end if;
        end if;
    end process;
 
    NEXT_STATE: process (PS, data_rdy, key_rdy)
    begin
               case PS is
                when KEYa =>
                    if(key_rdy = '1') then
                        NS <= KEYb;
                    else
                        NS <= KEYa;
                    end if;
                when KEYb =>
                    NS <= KEYc;
                when KEYc =>
                    NS <= KEYd;
                when KEYd =>
                    if (reg_k_len = KLEN_128) then
                        NS <= SIX1a;
                    else
                        NS <= KEYe;
                    end if;
                when KEYe =>
                    NS <= KEYf;
                when KEYf =>
                    NS <= SIX1a;
                when SIX1a =>
                    if(data_rdy = '1') then
                        NS <= SIX1b;
                    else
                        NS <= SIX1a;
                    end if;
                when SIX1b =>
                    NS <= SIX1c;
                when SIX1c =>
                    NS <= SIX1d;
                when SIX1d =>
                    NS <= SIX1e;
                when SIX1e =>
                    NS <= SIX1f;
                when SIX1f =>
                    NS <= FL1;
                when FL1 =>
                    NS <= SIX2a;
                when SIX2a =>
                    NS <= SIX2b;
                when SIX2b =>
                    NS <= SIX2c;
                when SIX2c =>
                    NS <= SIX2d;
                when SIX2d =>
                    NS <= SIX2e;
                when SIX2e =>
                    NS <= SIX2f;
                when SIX2f =>
                    NS <= FL2;
                when FL2 =>
                    NS <= SIX3a;
                when SIX3a =>
                    NS <= SIX3b;
                when SIX3b =>
                    NS <= SIX3c;
                when SIX3c =>
                    NS <= SIX3d;
                when SIX3d =>
                    NS <= SIX3e;
                when SIX3e =>
                    NS <= SIX3f;
                when SIX3f =>
                    if (reg_k_len = KLEN_128) then
                        if (key_rdy = '1') then
                            NS <= KEYa;
                        else
                            if (data_rdy = '1') then
                                NS <= SIX1a;
                            else
                                NS <= WT;
                            end if;
                        end if;
                    else
                        NS <= FL3;
                    end if;
                when FL3 =>
                    NS <= SIX4a;
                when SIX4a =>
                    NS <= SIX4b;
                when SIX4b =>
                    NS <= SIX4c;
                when SIX4c =>
                    NS <= SIX4d;
                when SIX4d =>
                    NS <= SIX4e;
                when SIX4e =>
                    NS <= SIX4f;
                when SIX4f =>
                    if (key_rdy = '1') then
                        NS <= KEYa;
                    else
                        if (data_rdy = '1') then
                            NS <= SIX1a;
                        else
                            NS <= WT;
                        end if;
                    end if;
                when WT =>
                    if (key_rdy = '1') then
                        NS <= KEYa;
                    else
                        if (data_rdy = '1') then
                            NS <= SIX1a;
                        else
                            NS <= WT;
                        end if;
                    end if;
            end case;
    end process;
 
end RTL;

Line No.	Rev	Author	Line
1	3	pfulgoni
2			`--------------------------------------------------------------------------------`
3			`-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>`
4			`--`
5			`-- Create Date: 01/31/2008`
6	4	pfulgoni	`-- Last Update: 03/28/2008`
7	3	pfulgoni	`-- Project Name: camellia-vhdl`
8			`-- Description: Control unit and key handling`
9			`--`
10			`-- Copyright (C) 2008 Paolo Fulgoni`
11			`-- This file is part of camellia-vhdl.`
12			`-- camellia-vhdl is free software; you can redistribute it and/or modify`
13			`-- it under the terms of the GNU General Public License as published by`
14			`-- the Free Software Foundation; either version 3 of the License, or`
15			`-- (at your option) any later version.`
16			`-- camellia-vhdl is distributed in the hope that it will be useful,`
17			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`-- GNU General Public License for more details.`
20			`-- You should have received a copy of the GNU General Public License`
21			`-- along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`--`
23			`-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and`
24			`-- Mitsubishi Electric researchers.`
25			`-- http://info.isl.ntt.co.jp/crypt/eng/camellia/`
26			`--------------------------------------------------------------------------------`
27			`library IEEE;`
28			`use IEEE.std_logic_1164.all;`
29
30			`entity control is`
31			`port (`
32			`clk : in STD_LOGIC;`
33			`reset : in STD_LOGIC;`
34	4	pfulgoni
35	3	pfulgoni	`data_in : in STD_LOGIC_VECTOR (0 to 127);`
36	4	pfulgoni	`enc_dec : in STD_LOGIC;`
37			`data_rdy : in STD_LOGIC;`
38			`data_acq : out STD_LOGIC;`
39
40	3	pfulgoni	`key_in : in STD_LOGIC_VECTOR (0 to 255);`
41			`k_len : in STD_LOGIC_VECTOR (0 to 1);`
42	4	pfulgoni	`key_rdy : in STD_LOGIC;`
43			`key_acq : out STD_LOGIC;`
44
45	3	pfulgoni	`data_to : out STD_LOGIC_VECTOR (0 to 127); -- data to datapath`
46	4	pfulgoni	`output_rdy : out STD_LOGIC;`
47	3	pfulgoni	`k1 : out STD_LOGIC_VECTOR (0 to 63);`
48			`k2 : out STD_LOGIC_VECTOR (0 to 63);`
49			`newdata : out STD_LOGIC;`
50			`sel : out STD_LOGIC;`
51			`pre_xor : out STD_LOGIC_VECTOR (0 to 127);`
52			`post_xor : out STD_LOGIC_VECTOR (0 to 127);`
53			`data_from : in STD_LOGIC_VECTOR (0 to 127) -- data from datapath`
54			`);`
55			`end control;`
56
57			`architecture RTL of control is`
58
59	6	pfulgoni	`type STATUS is (KEYa, KEYb, KEYc, KEYd, KEYe, KEYf,`
60	3	pfulgoni	`SIX1a, SIX1b, SIX1c, SIX1d, SIX1e, SIX1f,`
61			`FL1,`
62			`SIX2a, SIX2b, SIX2c, SIX2d, SIX2e, SIX2f,`
63			`FL2,`
64			`SIX3a, SIX3b, SIX3c, SIX3d, SIX3e, SIX3f,`
65			`FL3,`
66	4	pfulgoni	`SIX4a, SIX4b, SIX4c, SIX4d, SIX4e, SIX4f,`
67			`WT`
68			`);`
69	3	pfulgoni	`signal PS, NS : STATUS;`
70
71			`type K1_TYPE is (SIG1, SIG2, SIG3, SIG4, SIG5, SIG6,`
72			`KL_L, KL_R, KR_L, KR_R, KA_L, KA_R, KB_L, KB_R);`
73			`signal k1_sel : K1_TYPE;`
74			`type K2_TYPE is (KL_L, KL_R, KR_L, KR_R, KA_L, KA_R, KB_L, KB_R);`
75			`signal k2_sel : K2_TYPE;`
76			`type POSTXOR_TYPE is (KL, KA, KB, ZERO);`
77			`signal postxor_sel : POSTXOR_TYPE;`
78			`type PREXOR_TYPE is (KL, KR, KA, KB, ZERO);`
79			`signal prexor_sel : PREXOR_TYPE;`
80
81			`-- keys`
82	4	pfulgoni	`signal reg_kl : STD_LOGIC_VECTOR (0 to 127);`
83	3	pfulgoni	`signal reg_kr : STD_LOGIC_VECTOR (0 to 127);`
84			`signal reg_ka : STD_LOGIC_VECTOR (0 to 127);`
85			`signal reg_kb : STD_LOGIC_VECTOR (0 to 127);`
86			`--keys shifted each step`
87			`signal reg_kl_s : STD_LOGIC_VECTOR (0 to 127);`
88			`signal reg_kr_s : STD_LOGIC_VECTOR (0 to 127);`
89			`signal reg_ka_s : STD_LOGIC_VECTOR (0 to 127);`
90			`signal reg_kb_s : STD_LOGIC_VECTOR (0 to 127);`
91	4	pfulgoni
92			`signal reg_k_len : STD_LOGIC_VECTOR (0 to 1);`
93			`signal reg_enc_dec : STD_LOGIC;`
94	3	pfulgoni
95			`-- input constant`
96			`constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";`
97			`constant KLEN_192 : STD_LOGIC_VECTOR (0 to 1) := "01";`
98			`constant KLEN_256 : STD_LOGIC_VECTOR (0 to 1) := "10";`
99			`constant ENC : STD_LOGIC := '0';`
100			`constant DEC : STD_LOGIC := '1';`
101			`constant SEL_F : STD_LOGIC := '0';`
102			`constant SEL_FL : STD_LOGIC := '1';`
103
104			`-- constant keys`
105			`constant sigma1 : STD_LOGIC_VECTOR (0 to 63) := X"A09E667F3BCC908B";`
106			`constant sigma2 : STD_LOGIC_VECTOR (0 to 63) := X"B67AE8584CAA73B2";`
107			`constant sigma3 : STD_LOGIC_VECTOR (0 to 63) := X"C6EF372FE94F82BE";`
108			`constant sigma4 : STD_LOGIC_VECTOR (0 to 63) := X"54FF53A5F1D36F1C";`
109			`constant sigma5 : STD_LOGIC_VECTOR (0 to 63) := X"10E527FADE682D1D";`
110			`constant sigma6 : STD_LOGIC_VECTOR (0 to 63) := X"B05688C2B3E6C1FD";`
111
112			`begin`
113
114			`with k1_sel select`
115			`k1 <= sigma1 when SIG1,`
116			`sigma2 when SIG2,`
117			`sigma3 when SIG3,`
118			`sigma4 when SIG4,`
119			`sigma5 when SIG5,`
120			`sigma6 when SIG6,`
121			`reg_kl_s(0 to 63) when KL_L,`
122			`reg_kl_s(64 to 127) when KL_R,`
123			`reg_kr_s(0 to 63) when KR_L,`
124			`reg_kr_s(64 to 127) when KR_R,`
125			`reg_ka_s(0 to 63) when KA_L,`
126			`reg_ka_s(64 to 127) when KA_R,`
127			`reg_kb_s(0 to 63) when KB_L,`
128			`reg_kb_s(64 to 127) when others;`
129			`with k2_sel select`
130			`k2 <= reg_kl_s(0 to 63) when KL_L,`
131			`reg_kl_s(64 to 127) when KL_R,`
132			`reg_kr_s(0 to 63) when KR_L,`
133			`reg_kr_s(64 to 127) when KR_R,`
134			`reg_ka_s(0 to 63) when KA_L,`
135			`reg_ka_s(64 to 127) when KA_R,`
136			`reg_kb_s(0 to 63) when KB_L,`
137			`reg_kb_s(64 to 127) when others;`
138
139			`with postxor_sel select`
140	4	pfulgoni	`post_xor <= reg_kl_s(64 to 127) & reg_kl_s(0 to 63) when KL,`
141	3	pfulgoni	`reg_ka_s(64 to 127) & reg_ka_s(0 to 63) when KA,`
142			`reg_kb_s(64 to 127) & reg_kb_s(0 to 63) when KB,`
143			`(others=>'0') when others;`
144
145			`with prexor_sel select`
146	4	pfulgoni	`pre_xor <= reg_kl_s when KL,`
147	3	pfulgoni	`reg_kr_s when KR,`
148			`reg_ka_s when KA,`
149			`reg_kb_s when KB,`
150			`(others=>'0') when others;`
151	6	pfulgoni
152	3	pfulgoni
153	6	pfulgoni	`REGISTERS_UPDATE : process(reset, clk)`
154	3	pfulgoni	`variable coming_from_key : STD_LOGIC;`
155			`begin`
156	6	pfulgoni	`if (reset = '1') then`
157			`reg_kl <= (others=>'0');`
158			`reg_kr <= (others=>'0');`
159			`reg_ka <= (others=>'0');`
160			`reg_kb <= (others=>'0');`
161			`reg_kl_s <= (others=>'0');`
162			`reg_kr_s <= (others=>'0');`
163			`reg_ka_s <= (others=>'0');`
164			`reg_kb_s <= (others=>'0');`
165			`reg_enc_dec <= '0';`
166			`reg_k_len <= (others=>'0');`
167			`output_rdy <= '0';`
168			`coming_from_key := '0';`
169			`else`
170			`if (clk'event and clk = '1') then`
171			`case PS is`
172			`when KEYa =>`
173			`coming_from_key := '1';`
174			`reg_kl <= key_in(0 to 127);`
175			`reg_kl_s <= key_in(0 to 127);`
176			`reg_k_len <= k_len;`
177			`case k_len is`
178			`when KLEN_192 =>`
179			`reg_kr <= key_in(128 to 191) & not (key_in(128 to 191));`
180			`reg_kr_s <= key_in(128 to 191) & not (key_in(128 to 191));`
181			`when KLEN_256 =>`
182			`reg_kr <= key_in(128 to 255);`
183			`reg_kr_s <= key_in(128 to 255);`
184			`when others =>`
185			`reg_kr <= (others=>'0');`
186			`reg_kr_s <= (others=>'0');`
187			`end case;`
188			`k1_sel <= SIG1;`
189			`when KEYb =>`
190			`k1_sel <= SIG2;`
191			`when KEYc =>`
192			`k1_sel <= SIG3;`
193			`when KEYd =>`
194			`k1_sel <= SIG4;`
195			`when KEYe =>`
196			`reg_ka <= data_from;`
197			`reg_ka_s <= data_from;`
198			`k1_sel <= SIG5;`
199			`when KEYf =>`
200			`k1_sel <= SIG6;`
201			`when SIX1a =>`
202			`if (enc_dec = ENC) then`
203			`if (coming_from_key = '1') then`
204			`if (reg_k_len = KLEN_128) then`
205			`reg_ka <= data_from;`
206			`reg_ka_s <= data_from;`
207			`else`
208			`reg_kb <= data_from;`
209			`reg_kb_s <= data_from;`
210			`end if;`
211			`else`
212			`reg_ka_s <= reg_ka;`
213			`reg_kb_s <= reg_kb;`
214			`reg_kl_s <= reg_kl;`
215			`reg_kr_s <= reg_kr;`
216			`end if;`
217	4	pfulgoni	`if (reg_k_len = KLEN_128) then`
218	6	pfulgoni	`k1_sel <= KA_L;`
219	3	pfulgoni	`else`
220	6	pfulgoni	`k1_sel <= KB_L;`
221	3	pfulgoni	`end if;`
222	6	pfulgoni	`else -- DEC`
223			`if (coming_from_key = '1') then`
224			`if (reg_k_len = KLEN_128) then`
225			`reg_ka <= data_from;`
226			`reg_ka_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17`
227			`else`
228			`reg_kb <= data_from;`
229			`reg_kb_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17`
230			`reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17`
231			`reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17`
232			`end if;`
233			`reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17`
234			`else`
235			`reg_ka_s <= reg_ka(111 to 127) & reg_ka(0 to 110); -- >>> 17`
236			`reg_kb_s <= reg_kb(111 to 127) & reg_kb(0 to 110); -- >>> 17`
237			`reg_kl_s <= key_in(111 to 127) & key_in(0 to 110); --kl >>> 17`
238			`reg_kr_s <= reg_kr(111 to 127) & reg_kr(0 to 110); -- >>> 17`
239			`end if;`
240			`k1_sel <= KL_R;`
241	3	pfulgoni	`end if;`
242	6	pfulgoni	`reg_enc_dec <= enc_dec;`
243			`when SIX1b =>`
244			`coming_from_key := '0';`
245			`if (reg_enc_dec = ENC) then`
246			`if (reg_k_len = KLEN_128) then`
247			`k1_sel <= KA_R;`
248			`else`
249			`k1_sel <= KB_R;`
250			`end if;`
251			`else -- DEC`
252			`k1_sel <= KL_L; -- for each value of reg_k_len`
253	3	pfulgoni	`end if;`
254	6	pfulgoni	`when SIX1c =>`
255			`if (reg_enc_dec = ENC) then`
256	4	pfulgoni	`if (reg_k_len = KLEN_128) then`
257	6	pfulgoni	`k1_sel <= KL_L;`
258			`reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15`
259	3	pfulgoni	`else`
260	6	pfulgoni	`k1_sel <= KR_L;`
261			`reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15`
262			`end if;`
263			`else -- DEC`
264			`reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17`
265			`k1_sel <= KA_R; -- for each value of reg_k_len`
266			`end if;`
267			`when SIX1d =>`
268			`if (reg_enc_dec = ENC) then`
269			`if (reg_k_len = KLEN_128) then`
270			`k1_sel <= KL_R;`
271			`else`
272			`k1_sel <= KR_R;`
273			`end if;`
274			`else -- DEC`
275			`k1_sel <= KA_L; -- for each value of reg_k_len`
276			`end if;`
277			`when SIX1e =>`
278			`if (reg_enc_dec = ENC) then`
279			`if (reg_k_len = KLEN_128) then`
280			`reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15`
281			`else`
282			`reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15`
283			`end if;`
284			`k1_sel <= KA_L;`
285			`else -- DEC`
286			`if (reg_k_len = KLEN_128) then`
287			`reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17`
288			`k1_sel <= KL_R;`
289			`else`
290	3	pfulgoni	`reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17`
291	6	pfulgoni	`k1_sel <= KR_R;`
292	3	pfulgoni	`end if;`
293			`end if;`
294	6	pfulgoni	`when SIX1f =>`
295			`if (reg_enc_dec = ENC) then`
296	3	pfulgoni	`k1_sel <= KA_R;`
297	6	pfulgoni	`else -- DEC`
298			`if (reg_k_len = KLEN_128) then`
299			`k1_sel <= KL_L;`
300			`else`
301			`k1_sel <= KR_L;`
302			`end if;`
303	3	pfulgoni	`end if;`
304	6	pfulgoni	`when FL1 =>`
305			`if (reg_enc_dec = ENC) then`
306			`if (reg_k_len = KLEN_128) then`
307			`k1_sel <= KA_L;`
308			`k2_sel <= KA_R;`
309			`reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15`
310			`reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15`
311			`else`
312			`k1_sel <= KR_L;`
313			`k2_sel <= KR_R;`
314			`reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15`
315			`reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15`
316			`end if;`
317			`else -- DEC`
318			`if (reg_k_len = KLEN_128) then`
319			`k1_sel <= KL_R;`
320			`k2_sel <= KL_L;`
321			`else`
322			`k1_sel <= KA_R;`
323			`k2_sel <= KA_L;`
324			`end if;`
325			`reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17`
326			`reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17`
327	3	pfulgoni	`end if;`
328	6	pfulgoni	`when SIX2a =>`
329			`if (reg_enc_dec = ENC) then`
330			`if (reg_k_len = KLEN_128) then`
331			`k1_sel <= KL_L;`
332			`reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15`
333			`else`
334			`k1_sel <= KB_L;`
335			`reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15`
336			`reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15`
337			`end if;`
338			`else -- DEC`
339			`if (reg_k_len = KLEN_128) then`
340			`k1_sel <= KA_R;`
341			`reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17`
342			`else`
343			`k1_sel <= KL_R;`
344			`reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17`
345			`reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17`
346			`end if;`
347	3	pfulgoni	`end if;`
348	6	pfulgoni	`when SIX2b =>`
349			`if (reg_enc_dec = ENC) then`
350			`if (reg_k_len = KLEN_128) then`
351			`k1_sel <= KL_R;`
352			`else`
353			`k1_sel <= KB_R;`
354			`reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15`
355			`end if;`
356			`else -- DEC`
357			`if (reg_k_len = KLEN_128) then`
358			`k1_sel <= KA_L;`
359			`else`
360			`k1_sel <= KL_L;`
361			`reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17`
362			`end if;`
363	3	pfulgoni	`end if;`
364	6	pfulgoni	`when SIX2c =>`
365			`if (reg_enc_dec = ENC) then`
366			`if (reg_k_len = KLEN_128) then`
367			`k1_sel <= KA_L;`
368			`reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15`
369			`else`
370			`k1_sel <= KL_L;`
371			`reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15`
372			`end if;`
373			`else -- DEC`
374			`if (reg_k_len = KLEN_128) then`
375			`k1_sel <= KL_R;`
376			`reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17`
377			`else`
378			`k1_sel <= KB_R;`
379			`reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17`
380			`end if;`
381			`end if;`
382			`when SIX2d =>`
383			`if (reg_enc_dec = ENC) then`
384			`if (reg_k_len = KLEN_128) then`
385			`reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15`
386			`else`
387			`reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15`
388			`end if;`
389	3	pfulgoni	`k1_sel <= KL_R;`
390	6	pfulgoni	`else -- DEC`
391			`if (reg_k_len = KLEN_128) then`
392			`k1_sel <= KA_L;`
393			`reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15`
394			`else`
395			`k1_sel <= KB_L;`
396			`reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17`
397			`end if;`
398	3	pfulgoni	`end if;`
399	6	pfulgoni	`when SIX2e =>`
400			`if (reg_enc_dec = ENC) then`
401			`if (reg_k_len = KLEN_128) then`
402			`reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15`
403			`else`
404			`reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15`
405			`end if;`
406	3	pfulgoni	`k1_sel <= KA_L;`
407	6	pfulgoni	`else -- DEC`
408			`if (reg_k_len = KLEN_128) then`
409			`k1_sel <= KL_R;`
410			`reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15`
411			`else`
412			`k1_sel <= KR_R;`
413			`reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17`
414			`end if;`
415	3	pfulgoni	`end if;`
416	6	pfulgoni	`when SIX2f =>`
417			`if (reg_enc_dec = ENC) then`
418	3	pfulgoni	`k1_sel <= KA_R;`
419	6	pfulgoni	`else -- DEC`
420			`if (reg_k_len = KLEN_128) then`
421			`k1_sel <= KL_L;`
422			`else`
423			`k1_sel <= KR_L;`
424			`end if;`
425	3	pfulgoni	`end if;`
426	6	pfulgoni	`when FL2 =>`
427			`if (reg_enc_dec = ENC) then`
428			`if (reg_k_len = KLEN_128) then`
429			`reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17`
430			`else`
431			`reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15`
432			`reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15`
433			`end if;`
434	3	pfulgoni	`k1_sel <= KL_L;`
435	6	pfulgoni	`k2_sel <= KL_R;`
436			`else -- DEC`
437			`if (reg_k_len = KLEN_128) then`
438			`k1_sel <= KA_R;`
439			`k2_sel <= KA_L;`
440			`reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15`
441			`else`
442			`k1_sel <= KL_R;`
443			`k2_sel <= KL_L;`
444			`reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17`
445			`reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17`
446			`end if;`
447	3	pfulgoni	`end if;`
448	6	pfulgoni	`when SIX3a =>`
449			`if (reg_enc_dec = ENC) then`
450			`if (reg_k_len = KLEN_128) then`
451			`k1_sel <= KL_L;`
452			`reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17`
453			`else`
454			`k1_sel <= KR_L;`
455			`reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15`
456			`end if;`
457			`else -- DEC`
458			`if (reg_k_len = KLEN_128) then`
459			`k1_sel <= KA_R;`
460			`else`
461			`k1_sel <= KA_R;`
462			`end if;`
463			`reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15`
464	3	pfulgoni	`end if;`
465	6	pfulgoni	`when SIX3b =>`
466			`if (reg_enc_dec = ENC) then`
467			`if (reg_k_len = KLEN_128) then`
468			`k1_sel <= KL_R;`
469			`reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17`
470			`else`
471			`k1_sel <= KR_R;`
472			`reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15`
473			`end if;`
474			`else -- DEC`
475			`if (reg_k_len = KLEN_128) then`
476			`k1_sel <= KA_L;`
477			`reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15`
478			`else`
479			`k1_sel <= KA_L;`
480			`end if;`
481	3	pfulgoni	`end if;`
482	6	pfulgoni	`when SIX3c =>`
483			`if (reg_enc_dec = ENC) then`
484			`if (reg_k_len = KLEN_128) then`
485			`k1_sel <= KA_L;`
486			`reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17`
487			`else`
488			`k1_sel <= KB_L;`
489			`reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15`
490			`end if;`
491			`else -- DEC`
492			`if (reg_k_len = KLEN_128) then`
493			`k1_sel <= KL_R;`
494			`else`
495			`k1_sel <= KL_R;`
496			`end if;`
497			`reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15`
498	3	pfulgoni	`end if;`
499	6	pfulgoni	`when SIX3d =>`
500			`if (reg_enc_dec = ENC) then`

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