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[/] [camellia-vhdl/] [trunk/] [pipelining/] [camellia256.vhd] - Blame information for rev 9

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1 2 pfulgoni 
 
2 
--------------------------------------------------------------------------------
3 
-- Designer:      Paolo Fulgoni <pfulgoni@opencores.org>
4 
--
5 
-- Create Date:   09/15/2007
6 8 pfulgoni 
-- Last Update:   06/23/2008
7 2 pfulgoni 
-- Project Name:  camellia-vhdl
8 
-- Description:   Camellia top level module, for 128/192/256-bit keys
9 
--
10 
-- Copyright (C) 2007  Paolo Fulgoni
11 
-- This file is part of camellia-vhdl.
12 
-- camellia-vhdl is free software; you can redistribute it and/or modify
13 
-- it under the terms of the GNU General Public License as published by
14 
-- the Free Software Foundation; either version 3 of the License, or
15 
-- (at your option) any later version.
16 
-- camellia-vhdl is distributed in the hope that it will be useful,
17 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
18 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 
-- GNU General Public License for more details.
20 
-- You should have received a copy of the GNU General Public License
21 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
22 
--
23 
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
24 
-- Mitsubishi Electric researchers.
25 
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
26 
--------------------------------------------------------------------------------
27 
library IEEE;
28 
use IEEE.std_logic_1164.all;
29 
use IEEE.std_logic_unsigned.all;
30 
 
31 
 
32 
entity CAMELLIA256 is
33 
    port(
34 8 pfulgoni 
            reset      : in STD_LOGIC;
35 
            clk        : in STD_LOGIC;
36 
            input      : in STD_LOGIC_VECTOR (0 to 127);  -- input data
37 
            input_en   : in  STD_LOGIC;                   -- input enable
38 
            key        : in STD_LOGIC_VECTOR (0 to 255);  -- key
39 
            key_len    : in STD_LOGIC_VECTOR (0 to 1);    -- key lenght
40 
            enc_dec    : in STD_LOGIC;                    -- dec=0 enc, dec=1 dec
41 
            output     : out STD_LOGIC_VECTOR (0 to 127); -- en/decrypted data
42 
            output_rdy : out STD_LOGIC                    -- output ready
43 2 pfulgoni 
            );
44 
end CAMELLIA256;
45 
 
46 
architecture RTL of CAMELLIA256 is
47 
 
48 
    component KEYSCHED256 is
49 
        port(
50 
                reset  : in STD_LOGIC;
51 
                clk    : in STD_LOGIC;
52 
                kl_in  : in STD_LOGIC_VECTOR (0 to 127);
53 
                kr_in  : in STD_LOGIC_VECTOR (0 to 127);
54 
                kl_out : out STD_LOGIC_VECTOR (0 to 127);
55 
                kr_out : out STD_LOGIC_VECTOR (0 to 127);
56 
                ka_out : out STD_LOGIC_VECTOR (0 to 127);
57 
                kb_out : out STD_LOGIC_VECTOR (0 to 127)
58 
                );
59 
    end component;
60 
 
61 
    component SIXROUND256 is
62 
        generic (
63 
                k1e128_offset  : INTEGER; -- encryption 128bit
64 
                k1e128_shift   : INTEGER;
65 
                k2e128_offset  : INTEGER;
66 
                k2e128_shift   : INTEGER;
67 
                k3e128_offset  : INTEGER;
68 
                k3e128_shift   : INTEGER;
69 
                k4e128_offset  : INTEGER;
70 
                k4e128_shift   : INTEGER;
71 
                k5e128_offset  : INTEGER;
72 
                k5e128_shift   : INTEGER;
73 
                k6e128_offset  : INTEGER;
74 
                k6e128_shift   : INTEGER;
75 
                k1d128_offset  : INTEGER; -- decryption 128bit
76 
                k1d128_shift   : INTEGER;
77 
                k2d128_offset  : INTEGER;
78 
                k2d128_shift   : INTEGER;
79 
                k3d128_offset  : INTEGER;
80 
                k3d128_shift   : INTEGER;
81 
                k4d128_offset  : INTEGER;
82 
                k4d128_shift   : INTEGER;
83 
                k5d128_offset  : INTEGER;
84 
                k5d128_shift   : INTEGER;
85 
                k6d128_offset  : INTEGER;
86 
                k6d128_shift   : INTEGER;
87 
                k1e256_offset  : INTEGER; -- encryption 192/256bit
88 
                k1e256_shift   : INTEGER;
89 
                k2e256_offset  : INTEGER;
90 
                k2e256_shift   : INTEGER;
91 
                k3e256_offset  : INTEGER;
92 
                k3e256_shift   : INTEGER;
93 
                k4e256_offset  : INTEGER;
94 
                k4e256_shift   : INTEGER;
95 
                k5e256_offset  : INTEGER;
96 
                k5e256_shift   : INTEGER;
97 
                k6e256_offset  : INTEGER;
98 
                k6e256_shift   : INTEGER;
99 
                k1d256_offset  : INTEGER; -- decryption 192/256bit
100 
                k1d256_shift   : INTEGER;
101 
                k2d256_offset  : INTEGER;
102 
                k2d256_shift   : INTEGER;
103 
                k3d256_offset  : INTEGER;
104 
                k3d256_shift   : INTEGER;
105 
                k4d256_offset  : INTEGER;
106 
                k4d256_shift   : INTEGER;
107 
                k5d256_offset  : INTEGER;
108 
                k5d256_shift   : INTEGER;
109 
                k6d256_offset  : INTEGER;
110 
                k6d256_shift   : INTEGER
111 
                );
112 
        port(
113 
                reset   : in  STD_LOGIC;
114 
                clk     : in  STD_LOGIC;
115 
                dec1    : in  STD_LOGIC;
116 
                k_len1  : in  STD_LOGIC_VECTOR (0 to 1);
117 
                k1      : in  STD_LOGIC_VECTOR (0 to 511);
118 
                dec2    : in  STD_LOGIC;
119 
                k_len2  : in  STD_LOGIC_VECTOR (0 to 1);
120 
                k2      : in  STD_LOGIC_VECTOR (0 to 511);
121 
                dec3    : in  STD_LOGIC;
122 
                k_len3  : in  STD_LOGIC_VECTOR (0 to 1);
123 
                k3      : in  STD_LOGIC_VECTOR (0 to 511);
124 
                dec4    : in  STD_LOGIC;
125 
                k_len4  : in  STD_LOGIC_VECTOR (0 to 1);
126 
                k4      : in  STD_LOGIC_VECTOR (0 to 511);
127 
                dec5    : in  STD_LOGIC;
128 
                k_len5  : in  STD_LOGIC_VECTOR (0 to 1);
129 
                k5      : in  STD_LOGIC_VECTOR (0 to 511);
130 
                dec6    : in  STD_LOGIC;
131 
                k_len6  : in  STD_LOGIC_VECTOR (0 to 1);
132 
                k6      : in  STD_LOGIC_VECTOR (0 to 511);
133 
                l_in    : in  STD_LOGIC_VECTOR (0 to 63);
134 
                r_in    : in  STD_LOGIC_VECTOR (0 to 63);
135 
                l_out   : out STD_LOGIC_VECTOR (0 to 63);
136 
                r_out   : out STD_LOGIC_VECTOR (0 to 63)
137 
                );
138 
    end component;
139 
 
140 
    component FL256 is
141 
        generic    (
142 
                    fl_ke128_offset  : INTEGER; -- 128bit encryption
143 
                    fl_ke128_shift   : INTEGER;
144 
                    fli_ke128_offset : INTEGER;
145 
                    fli_ke128_shift  : INTEGER;
146 
                    fl_kd128_offset  : INTEGER; -- 128bit decryption
147 
                    fl_kd128_shift   : INTEGER;
148 
                    fli_kd128_offset : INTEGER;
149 
                    fli_kd128_shift  : INTEGER;
150 
                    fl_ke256_offset  : INTEGER; -- 192/256bit encryption
151 
                    fl_ke256_shift   : INTEGER;
152 
                    fli_ke256_offset : INTEGER;
153 
                    fli_ke256_shift  : INTEGER;
154 
                    fl_kd256_offset  : INTEGER; -- 192/256bit decryption
155 
                    fl_kd256_shift   : INTEGER;
156 
                    fli_kd256_offset : INTEGER;
157 
                    fli_kd256_shift  : INTEGER
158 
                    );
159 
        port(
160 
                reset   : in  STD_LOGIC;
161 
                clk     : in  STD_LOGIC;
162 
                fl_in   : in  STD_LOGIC_VECTOR (0 to 63);
163 
                fli_in  : in  STD_LOGIC_VECTOR (0 to 63);
164 
                k       : in  STD_LOGIC_VECTOR (0 to 511);
165 
                k_len   : in  STD_LOGIC_VECTOR (0 to 1);
166 
                dec     : in  STD_LOGIC;
167 
                fl_out  : out STD_LOGIC_VECTOR (0 to 63);
168 
                fli_out : out STD_LOGIC_VECTOR (0 to 63)
169 
                );
170 
    end component;
171 
 
172 
 
173 
    -- input registers
174 
    signal reg_m      : STD_LOGIC_VECTOR (0 to 127);
175 
    signal reg_kl     : STD_LOGIC_VECTOR (0 to 127);
176 
    signal reg_kr_int : STD_LOGIC_VECTOR (0 to 127);
177 
    signal reg_k_len  : STD_LOGIC_VECTOR (0 to 1);
178 
    signal reg_dec    : STD_LOGIC;
179 8 pfulgoni 
    signal reg_rdy : STD_LOGIC;
180 2 pfulgoni 
 
181 
    -- used by pre-whitening
182 
    signal kw1_enc        : STD_LOGIC_VECTOR (0 to 63);
183 
    signal kw2_enc        : STD_LOGIC_VECTOR (0 to 63);
184 
    signal ka_s111_dec128 : STD_LOGIC_VECTOR (0 to 127);
185 
    signal kw1_dec128     : STD_LOGIC_VECTOR (0 to 63);
186 
    signal kw2_dec128     : STD_LOGIC_VECTOR (0 to 63);
187 
    signal ka_s111_dec256 : STD_LOGIC_VECTOR (0 to 127);
188 
    signal kw1_dec256     : STD_LOGIC_VECTOR (0 to 63);
189 
    signal kw2_dec256     : STD_LOGIC_VECTOR (0 to 63);
190 
    signal kw1            : STD_LOGIC_VECTOR (0 to 63);
191 
    signal kw2            : STD_LOGIC_VECTOR (0 to 63);
192 
    signal w1             : STD_LOGIC_VECTOR (0 to 63);
193 
    signal w2             : STD_LOGIC_VECTOR (0 to 63);
194 
 
195 
    -- used by post-whitening
196 
    signal ka_s111_enc128 : STD_LOGIC_VECTOR (0 to 127);
197 
    signal kw3_enc128     : STD_LOGIC_VECTOR (0 to 63);
198 
    signal kw4_enc128     : STD_LOGIC_VECTOR (0 to 63);
199 
    signal ka_s111_enc256 : STD_LOGIC_VECTOR (0 to 127);
200 
    signal kw3_enc256     : STD_LOGIC_VECTOR (0 to 63);
201 
    signal kw4_enc256     : STD_LOGIC_VECTOR (0 to 63);
202 
    signal kw3_dec        : STD_LOGIC_VECTOR (0 to 63);
203 
    signal kw4_dec        : STD_LOGIC_VECTOR (0 to 63);
204 
    signal kw3            : STD_LOGIC_VECTOR (0 to 63);
205 
    signal kw4            : STD_LOGIC_VECTOR (0 to 63);
206 
    signal w3             : STD_LOGIC_VECTOR (0 to 63);
207 
    signal w4             : STD_LOGIC_VECTOR (0 to 63);
208 
 
209 
    -- registers used during key schedule
210 
    signal reg_a1_m    : STD_LOGIC_VECTOR (0 to 127);
211 
    signal reg_a1_dec  : STD_LOGIC;
212 
    signal reg_a1_klen : STD_LOGIC_VECTOR (0 to 1);
213 8 pfulgoni 
    signal reg_a1_rdy  : STD_LOGIC;
214 2 pfulgoni 
    signal reg_a2_m    : STD_LOGIC_VECTOR (0 to 127);
215 
    signal reg_a2_dec  : STD_LOGIC;
216 
    signal reg_a2_klen : STD_LOGIC_VECTOR (0 to 1);
217 8 pfulgoni 
    signal reg_a2_rdy  : STD_LOGIC;
218 2 pfulgoni 
    signal reg_a3_m    : STD_LOGIC_VECTOR (0 to 127);
219 
    signal reg_a3_dec  : STD_LOGIC;
220 
    signal reg_a3_klen : STD_LOGIC_VECTOR (0 to 1);
221 8 pfulgoni 
    signal reg_a3_rdy  : STD_LOGIC;
222 2 pfulgoni 
    signal reg_a4_m    : STD_LOGIC_VECTOR (0 to 127);
223 
    signal reg_a4_dec  : STD_LOGIC;
224 
    signal reg_a4_klen : STD_LOGIC_VECTOR (0 to 1);
225 8 pfulgoni 
    signal reg_a4_rdy  : STD_LOGIC;
226 2 pfulgoni 
    signal reg_a5_m    : STD_LOGIC_VECTOR (0 to 127);
227 
    signal reg_a5_dec  : STD_LOGIC;
228 
    signal reg_a5_klen : STD_LOGIC_VECTOR (0 to 1);
229 8 pfulgoni 
    signal reg_a5_rdy  : STD_LOGIC;
230 2 pfulgoni 
    signal reg_a6_m    : STD_LOGIC_VECTOR (0 to 127);
231 
    signal reg_a6_dec  : STD_LOGIC;
232 
    signal reg_a6_klen : STD_LOGIC_VECTOR (0 to 1);
233 8 pfulgoni 
    signal reg_a6_rdy  : STD_LOGIC;
234 2 pfulgoni 
 
235 
    -- registers used during 6-rounds and fls
236 8 pfulgoni 
    signal reg_b1_dec   : STD_LOGIC;
237 
    signal reg_b1_k     : STD_LOGIC_VECTOR (0 to 511);
238 
    signal reg_b1_klen  : STD_LOGIC_VECTOR (0 to 1);
239 
    signal reg_b1_rdy   : STD_LOGIC;
240 
    signal reg_b2_dec   : STD_LOGIC;
241 
    signal reg_b2_k     : STD_LOGIC_VECTOR (0 to 511);
242 
    signal reg_b2_klen  : STD_LOGIC_VECTOR (0 to 1);
243 
    signal reg_b2_rdy   : STD_LOGIC;
244 
    signal reg_b3_dec   : STD_LOGIC;
245 
    signal reg_b3_k     : STD_LOGIC_VECTOR (0 to 511);
246 
    signal reg_b3_klen  : STD_LOGIC_VECTOR (0 to 1);
247 
    signal reg_b3_rdy   : STD_LOGIC;
248 
    signal reg_b4_dec   : STD_LOGIC;
249 
    signal reg_b4_k     : STD_LOGIC_VECTOR (0 to 511);
250 
    signal reg_b4_klen  : STD_LOGIC_VECTOR (0 to 1);
251 
    signal reg_b4_rdy   : STD_LOGIC;
252 
    signal reg_b5_dec   : STD_LOGIC;
253 
    signal reg_b5_k     : STD_LOGIC_VECTOR (0 to 511);
254 
    signal reg_b5_klen  : STD_LOGIC_VECTOR (0 to 1);
255 
    signal reg_b5_rdy   : STD_LOGIC;
256 
    signal reg_b6_dec   : STD_LOGIC;
257 
    signal reg_b6_k     : STD_LOGIC_VECTOR (0 to 511);
258 
    signal reg_b6_klen  : STD_LOGIC_VECTOR (0 to 1);
259 
    signal reg_b6_rdy   : STD_LOGIC;
260 
    signal reg_b7_dec   : STD_LOGIC;
261 
    signal reg_b7_k     : STD_LOGIC_VECTOR (0 to 511);
262 
    signal reg_b7_klen  : STD_LOGIC_VECTOR (0 to 1);
263 
    signal reg_b7_rdy   : STD_LOGIC;
264 
    signal reg_b8_dec   : STD_LOGIC;
265 
    signal reg_b8_k     : STD_LOGIC_VECTOR (0 to 511);
266 
    signal reg_b8_klen  : STD_LOGIC_VECTOR (0 to 1);
267 
    signal reg_b8_rdy   : STD_LOGIC;
268 
    signal reg_b9_dec   : STD_LOGIC;
269 
    signal reg_b9_k     : STD_LOGIC_VECTOR (0 to 511);
270 
    signal reg_b9_klen  : STD_LOGIC_VECTOR (0 to 1);
271 
    signal reg_b9_rdy   : STD_LOGIC;
272 2 pfulgoni 
    signal reg_b10_dec  : STD_LOGIC;
273 
    signal reg_b10_k    : STD_LOGIC_VECTOR (0 to 511);
274 
    signal reg_b10_klen : STD_LOGIC_VECTOR (0 to 1);
275 8 pfulgoni 
    signal reg_b10_rdy  : STD_LOGIC;
276 2 pfulgoni 
    signal reg_b11_dec  : STD_LOGIC;
277 
    signal reg_b11_k    : STD_LOGIC_VECTOR (0 to 511);
278 
    signal reg_b11_klen : STD_LOGIC_VECTOR (0 to 1);
279 8 pfulgoni 
    signal reg_b11_rdy  : STD_LOGIC;
280 2 pfulgoni 
    signal reg_b12_dec  : STD_LOGIC;
281 
    signal reg_b12_k    : STD_LOGIC_VECTOR (0 to 511);
282 
    signal reg_b12_klen : STD_LOGIC_VECTOR (0 to 1);
283 8 pfulgoni 
    signal reg_b12_rdy  : STD_LOGIC;
284 2 pfulgoni 
    signal reg_b13_dec  : STD_LOGIC;
285 
    signal reg_b13_k    : STD_LOGIC_VECTOR (0 to 511);
286 
    signal reg_b13_klen : STD_LOGIC_VECTOR (0 to 1);
287 8 pfulgoni 
    signal reg_b13_rdy  : STD_LOGIC;
288 2 pfulgoni 
    signal reg_b14_dec  : STD_LOGIC;
289 
    signal reg_b14_k    : STD_LOGIC_VECTOR (0 to 511);
290 
    signal reg_b14_klen : STD_LOGIC_VECTOR (0 to 1);
291 8 pfulgoni 
    signal reg_b14_rdy  : STD_LOGIC;
292 2 pfulgoni 
    signal reg_b15_dec  : STD_LOGIC;
293 
    signal reg_b15_k    : STD_LOGIC_VECTOR (0 to 511);
294 
    signal reg_b15_klen : STD_LOGIC_VECTOR (0 to 1);
295 8 pfulgoni 
    signal reg_b15_rdy  : STD_LOGIC;
296 2 pfulgoni 
    signal reg_b16_dec  : STD_LOGIC;
297 
    signal reg_b16_k    : STD_LOGIC_VECTOR (0 to 511);
298 
    signal reg_b16_klen : STD_LOGIC_VECTOR (0 to 1);
299 8 pfulgoni 
    signal reg_b16_rdy  : STD_LOGIC;
300 2 pfulgoni 
    signal reg_b17_dec  : STD_LOGIC;
301 
    signal reg_b17_k    : STD_LOGIC_VECTOR (0 to 511);
302 
    signal reg_b17_klen : STD_LOGIC_VECTOR (0 to 1);
303 8 pfulgoni 
    signal reg_b17_rdy  : STD_LOGIC;
304 2 pfulgoni 
    signal reg_b18_dec  : STD_LOGIC;
305 
    signal reg_b18_k    : STD_LOGIC_VECTOR (0 to 511);
306 
    signal reg_b18_klen : STD_LOGIC_VECTOR (0 to 1);
307 8 pfulgoni 
    signal reg_b18_rdy  : STD_LOGIC;
308 2 pfulgoni 
    signal reg_b19_dec  : STD_LOGIC;
309 
    signal reg_b19_k    : STD_LOGIC_VECTOR (0 to 511);
310 
    signal reg_b19_klen : STD_LOGIC_VECTOR (0 to 1);
311 8 pfulgoni 
    signal reg_b19_rdy  : STD_LOGIC;
312 2 pfulgoni 
    signal reg_b20_dec  : STD_LOGIC;
313 
    signal reg_b20_k    : STD_LOGIC_VECTOR (0 to 511);
314 
    signal reg_b20_klen : STD_LOGIC_VECTOR (0 to 1);
315 8 pfulgoni 
    signal reg_b20_rdy  : STD_LOGIC;
316 2 pfulgoni 
    signal reg_b21_dec  : STD_LOGIC;
317 
    signal reg_b21_k    : STD_LOGIC_VECTOR (0 to 511);
318 
    signal reg_b21_klen : STD_LOGIC_VECTOR (0 to 1);
319 8 pfulgoni 
    signal reg_b21_rdy  : STD_LOGIC;
320 2 pfulgoni 
    signal reg_b22_dec  : STD_LOGIC;
321 
    signal reg_b22_k    : STD_LOGIC_VECTOR (0 to 511);
322 
    signal reg_b22_klen : STD_LOGIC_VECTOR (0 to 1);
323 8 pfulgoni 
    signal reg_b22_rdy  : STD_LOGIC;
324 2 pfulgoni 
    signal reg_b23_dec  : STD_LOGIC;
325 
    signal reg_b23_k    : STD_LOGIC_VECTOR (0 to 511);
326 
    signal reg_b23_klen : STD_LOGIC_VECTOR (0 to 1);
327 8 pfulgoni 
    signal reg_b23_rdy  : STD_LOGIC;
328 2 pfulgoni 
    signal reg_b24_dec  : STD_LOGIC;
329 
    signal reg_b24_k    : STD_LOGIC_VECTOR (0 to 511);
330 
    signal reg_b24_klen : STD_LOGIC_VECTOR (0 to 1);
331 8 pfulgoni 
    signal reg_b24_rdy  : STD_LOGIC;
332 2 pfulgoni 
    signal reg_b25_dec  : STD_LOGIC;
333 
    signal reg_b25_k    : STD_LOGIC_VECTOR (0 to 511);
334 
    signal reg_b25_klen : STD_LOGIC_VECTOR (0 to 1);
335 8 pfulgoni 
    signal reg_b25_rdy  : STD_LOGIC;
336 2 pfulgoni 
    signal reg_b26_dec  : STD_LOGIC;
337 
    signal reg_b26_k    : STD_LOGIC_VECTOR (0 to 511);
338 
    signal reg_b26_klen : STD_LOGIC_VECTOR (0 to 1);
339 8 pfulgoni 
    signal reg_b26_rdy  : STD_LOGIC;
340 2 pfulgoni 
    signal reg_b27_dec  : STD_LOGIC;
341 
    signal reg_b27_k    : STD_LOGIC_VECTOR (0 to 511);
342 
    signal reg_b27_klen : STD_LOGIC_VECTOR (0 to 1);
343 8 pfulgoni 
    signal reg_b27_rdy  : STD_LOGIC;
344 2 pfulgoni 
 
345 
    -- registers used for 128bit key encryptions
346 
    signal reg_l128_1  : STD_LOGIC_VECTOR (0 to 63);
347 
    signal reg_r128_1  : STD_LOGIC_VECTOR (0 to 63);
348 
    signal reg_l128_2  : STD_LOGIC_VECTOR (0 to 63);
349 
    signal reg_r128_2  : STD_LOGIC_VECTOR (0 to 63);
350 
    signal reg_l128_3  : STD_LOGIC_VECTOR (0 to 63);
351 
    signal reg_r128_3  : STD_LOGIC_VECTOR (0 to 63);
352 
    signal reg_l128_4  : STD_LOGIC_VECTOR (0 to 63);
353 
    signal reg_r128_4  : STD_LOGIC_VECTOR (0 to 63);
354 
    signal reg_l128_5  : STD_LOGIC_VECTOR (0 to 63);
355 
    signal reg_r128_5  : STD_LOGIC_VECTOR (0 to 63);
356 
    signal reg_l128_6  : STD_LOGIC_VECTOR (0 to 63);
357 
    signal reg_r128_6  : STD_LOGIC_VECTOR (0 to 63);
358 
    signal reg_l128_7  : STD_LOGIC_VECTOR (0 to 63);
359 
    signal reg_r128_7  : STD_LOGIC_VECTOR (0 to 63);
360 
 
361 
    -- components outputs
362 
    signal out_ksched : STD_LOGIC_VECTOR (0 to 511); -- key schedule
363 
    signal out_r1l    : STD_LOGIC_VECTOR (0 to 63);  -- first six-round
364 
    signal out_r1r    : STD_LOGIC_VECTOR (0 to 63);
365 
    signal out_r2l    : STD_LOGIC_VECTOR (0 to 63);  -- second six-round
366 
    signal out_r2r    : STD_LOGIC_VECTOR (0 to 63);
367 
    signal out_r3l    : STD_LOGIC_VECTOR (0 to 63);  -- third six-round
368 
    signal out_r3r    : STD_LOGIC_VECTOR (0 to 63);
369 
    signal out_r4l    : STD_LOGIC_VECTOR (0 to 63);  -- fourth six-round
370 
    signal out_r4r    : STD_LOGIC_VECTOR (0 to 63);
371 
    signal out_fl1l   : STD_LOGIC_VECTOR (0 to 63);  -- first fl
372 
    signal out_fl1r   : STD_LOGIC_VECTOR (0 to 63);
373 
    signal out_fl2l   : STD_LOGIC_VECTOR (0 to 63);  -- second fl
374 
    signal out_fl2r   : STD_LOGIC_VECTOR (0 to 63);
375 
    signal out_fl3l   : STD_LOGIC_VECTOR (0 to 63);  -- third fl
376 
    signal out_fl3r   : STD_LOGIC_VECTOR (0 to 63);
377 
 
378 
    -- misc signals
379 
    signal kr_int   : STD_LOGIC_VECTOR (0 to 127);
380 
 
381 
    -- constants
382 
    constant KL_OFFSET : INTEGER := 0;
383 
    constant KR_OFFSET : INTEGER := 128;
384 
    constant KA_OFFSET : INTEGER := 256;
385 
    constant KB_OFFSET : INTEGER := 384;
386 
 
387 
begin
388 
 
389 8 pfulgoni 
    KEY_SCHED: KEYSCHED256
390 2 pfulgoni 
    PORT MAP (
391 
            reset  => reset,
392 
            clk    => clk,
393 
            kl_in  => reg_kl,
394 
            kr_in  => reg_kr_int,
395 
            kl_out => out_ksched(KL_OFFSET to KL_OFFSET+127),
396 
            kr_out => out_ksched(KR_OFFSET to KR_OFFSET+127),
397 
            ka_out => out_ksched(KA_OFFSET to KA_OFFSET+127),
398 
            kb_out => out_ksched(KB_OFFSET to KB_OFFSET+127)
399 
            );
400 
 
401 
    SIX1: SIXROUND256
402 
    GENERIC MAP(
403 
        k1e128_offset => KA_OFFSET,
404 
        k1e128_shift  => 0,
405 
        k2e128_offset => KA_OFFSET,
406 
        k2e128_shift  => 0,
407 
        k3e128_offset => KL_OFFSET,
408 
        k3e128_shift  => 15,
409 
        k4e128_offset => KL_OFFSET,
410 
        k4e128_shift  => 15,
411 
        k5e128_offset => KA_OFFSET,
412 
        k5e128_shift  => 15,
413 
        k6e128_offset => KA_OFFSET,
414 
        k6e128_shift  => 15,
415 
        k1d128_offset => KL_OFFSET,
416 
        k1d128_shift  => 111,
417 
        k2d128_offset => KL_OFFSET,
418 
        k2d128_shift  => 111,
419 
        k3d128_offset => KA_OFFSET,
420 
        k3d128_shift  => 94,
421 
        k4d128_offset => KA_OFFSET,
422 
        k4d128_shift  => 94,
423 
        k5d128_offset => KL_OFFSET,
424 
        k5d128_shift  => 94,
425 
        k6d128_offset => KL_OFFSET,
426 
        k6d128_shift  => 94,
427 
        k1e256_offset => KB_OFFSET,
428 
        k1e256_shift  => 0,
429 
        k2e256_offset => KB_OFFSET,
430 
        k2e256_shift  => 0,
431 
        k3e256_offset => KR_OFFSET,
432 
        k3e256_shift  => 15,
433 
        k4e256_offset => KR_OFFSET,
434 
        k4e256_shift  => 15,
435 
        k5e256_offset => KA_OFFSET,
436 
        k5e256_shift  => 15,
437 
        k6e256_offset => KA_OFFSET,
438 
        k6e256_shift  => 15,
439 
        k1d256_offset => KL_OFFSET,
440 
        k1d256_shift  => 111,
441 
        k2d256_offset => KL_OFFSET,
442 
        k2d256_shift  => 111,
443 
        k3d256_offset => KA_OFFSET,
444 
        k3d256_shift  => 94,
445 
        k4d256_offset => KA_OFFSET,
446 
        k4d256_shift  => 94,
447 
        k5d256_offset => KR_OFFSET,
448 
        k5d256_shift  => 94,
449 
        k6d256_offset => KR_OFFSET,
450 
        k6d256_shift  => 94
451 
    )
452 
    PORT MAP(
453 
        reset   => reset,
454 
        clk     => clk,
455 
        dec1    => reg_a6_dec,
456 
        k_len1  => reg_a6_klen,
457 
        k1      => out_ksched,
458 
        dec2    => reg_b1_dec,
459 
        k_len2  => reg_b1_klen,
460 
        k2      => reg_b1_k,
461 
        dec3    => reg_b2_dec,
462 
        k_len3  => reg_b2_klen,
463 
        k3      => reg_b2_k,
464 
        dec4    => reg_b3_dec,
465 
        k_len4  => reg_b3_klen,
466 
        k4      => reg_b3_k,
467 
        dec5    => reg_b4_dec,
468 
        k_len5  => reg_b4_klen,
469 
        k5      => reg_b4_k,
470 
        dec6    => reg_b5_dec,
471 
        k_len6  => reg_b5_klen,
472 
        k6      => reg_b5_k,
473 
        l_in    => w1,
474 
        r_in    => w2,
475 
        l_out   => out_r1l,
476 
        r_out   => out_r1r
477 
    );
478 
 
479 
    SIX2: SIXROUND256
480 
    GENERIC MAP(
481 
        k1e128_offset => KL_OFFSET,
482 
        k1e128_shift  => 45,
483 
        k2e128_offset => KL_OFFSET,
484 
        k2e128_shift  => 45,
485 
        k3e128_offset => KA_OFFSET,
486 
        k3e128_shift  => 45,
487 
        k4e128_offset => KL_OFFSET,
488 
        k4e128_shift  => 60,
489 
        k5e128_offset => KA_OFFSET,
490 
        k5e128_shift  => 60,
491 
        k6e128_offset => KA_OFFSET,
492 
        k6e128_shift  => 60,
493 
        k1d128_offset => KA_OFFSET,
494 
        k1d128_shift  => 60,
495 
        k2d128_offset => KA_OFFSET,
496 
        k2d128_shift  => 60,
497 
        k3d128_offset => KL_OFFSET,
498 
        k3d128_shift  => 60,
499 
        k4d128_offset => KA_OFFSET,
500 
        k4d128_shift  => 45,
501 
        k5d128_offset => KL_OFFSET,
502 
        k5d128_shift  => 45,
503 
        k6d128_offset => KL_OFFSET,
504 
        k6d128_shift  => 45,
505 
        k1e256_offset => KB_OFFSET,
506 
        k1e256_shift  => 30,
507 
        k2e256_offset => KB_OFFSET,
508 
        k2e256_shift  => 30,
509 
        k3e256_offset => KL_OFFSET,
510 
        k3e256_shift  => 45,
511 
        k4e256_offset => KL_OFFSET,
512 
        k4e256_shift  => 45,
513 
        k5e256_offset => KA_OFFSET,
514 
        k5e256_shift  => 45,
515 
        k6e256_offset => KA_OFFSET,
516 
        k6e256_shift  => 45,
517 
        k1d256_offset => KL_OFFSET,
518 
        k1d256_shift  => 77,
519 
        k2d256_offset => KL_OFFSET,
520 
        k2d256_shift  => 77,
521 
        k3d256_offset => KB_OFFSET,
522 
        k3d256_shift  => 60,
523 
        k4d256_offset => KB_OFFSET,
524 
        k4d256_shift  => 60,
525 
        k5d256_offset => KR_OFFSET,
526 
        k5d256_shift  => 60,
527 
        k6d256_offset => KR_OFFSET,
528 
        k6d256_shift  => 60
529 
    )
530 
    PORT MAP(
531 
        reset   => reset,
532 
        clk     => clk,
533 
        dec1    => reg_b7_dec,
534 
        k_len1  => reg_b7_klen,
535 
        k1      => reg_b7_k,
536 
        dec2    => reg_b8_dec,
537 
        k_len2  => reg_b8_klen,
538 
        k2      => reg_b8_k,
539 
        dec3    => reg_b9_dec,
540 
        k_len3  => reg_b9_klen,
541 
        k3      => reg_b9_k,
542 
        dec4    => reg_b10_dec,
543 
        k_len4  => reg_b10_klen,
544 
        k4      => reg_b10_k,
545 
        dec5    => reg_b11_dec,
546 
        k_len5  => reg_b11_klen,
547 
        k5      => reg_b11_k,
548 
        dec6    => reg_b12_dec,
549 
        k_len6  => reg_b12_klen,
550 
        k6      => reg_b12_k,
551 
        l_in    => out_fl1l,
552 
        r_in    => out_fl1r,
553 
        l_out   => out_r2l,
554 
        r_out   => out_r2r
555 
    );
556 
 
557 
    SIX3: SIXROUND256
558 
    GENERIC MAP(
559 
        k1e128_offset => KL_OFFSET,
560 
        k1e128_shift  => 94,
561 
        k2e128_offset => KL_OFFSET,
562 
        k2e128_shift  => 94,
563 
        k3e128_offset => KA_OFFSET,
564 
        k3e128_shift  => 94,
565 
        k4e128_offset => KA_OFFSET,
566 
        k4e128_shift  => 94,
567 
        k5e128_offset => KL_OFFSET,
568 
        k5e128_shift  => 111,
569 
        k6e128_offset => KL_OFFSET,
570 
        k6e128_shift  => 111,
571 
        k1d128_offset => KA_OFFSET,
572 
        k1d128_shift  => 15,
573 
        k2d128_offset => KA_OFFSET,
574 
        k2d128_shift  => 15,
575 
        k3d128_offset => KL_OFFSET,
576 
        k3d128_shift  => 15,
577 
        k4d128_offset => KL_OFFSET,
578 
        k4d128_shift  => 15,
579 
        k5d128_offset => KA_OFFSET,
580 
        k5d128_shift  => 0,
581 
        k6d128_offset => KA_OFFSET,
582 
        k6d128_shift  => 0,
583 
        k1e256_offset => KR_OFFSET,
584 
        k1e256_shift  => 60,
585 
        k2e256_offset => KR_OFFSET,
586 
        k2e256_shift  => 60,
587 
        k3e256_offset => KB_OFFSET,
588 
        k3e256_shift  => 60,
589 
        k4e256_offset => KB_OFFSET,
590 
        k4e256_shift  => 60,
591 
        k5e256_offset => KL_OFFSET,
592 
        k5e256_shift  => 77,
593 
        k6e256_offset => KL_OFFSET,
594 
        k6e256_shift  => 77,
595 
        k1d256_offset => KA_OFFSET,
596 
        k1d256_shift  => 45,
597 
        k2d256_offset => KA_OFFSET,
598 
        k2d256_shift  => 45,
599 
        k3d256_offset => KL_OFFSET,
600 
        k3d256_shift  => 45,
601 
        k4d256_offset => KL_OFFSET,
602 
        k4d256_shift  => 45,
603 
        k5d256_offset => KB_OFFSET,
604 
        k5d256_shift  => 30,
605 
        k6d256_offset => KB_OFFSET,
606 
        k6d256_shift  => 30
607 
    )
608 
    PORT MAP(
609 
        reset   => reset,
610 
        clk     => clk,
611 
        dec1    => reg_b14_dec,
612 
        k_len1  => reg_b14_klen,
613 
        k1      => reg_b14_k,
614 
        dec2    => reg_b15_dec,
615 
        k_len2  => reg_b15_klen,
616 
        k2      => reg_b15_k,
617 
        dec3    => reg_b16_dec,
618 
        k_len3  => reg_b16_klen,
619 
        k3      => reg_b16_k,
620 
        dec4    => reg_b17_dec,
621 
        k_len4  => reg_b17_klen,
622 
        k4      => reg_b17_k,
623 
        dec5    => reg_b18_dec,
624 
        k_len5  => reg_b18_klen,
625 
        k5      => reg_b18_k,
626 
        dec6    => reg_b19_dec,
627 
        k_len6  => reg_b19_klen,
628 
        k6      => reg_b19_k,
629 
        l_in    => out_fl2l,
630 
        r_in    => out_fl2r,
631 
        l_out   => out_r3l,
632 
        r_out   => out_r3r
633 
    );
634 
 
635 
    SIX4: SIXROUND256
636 
    GENERIC MAP(
637 
        k1e128_offset => 0,
638 
        k1e128_shift  => 0,
639 
        k2e128_offset => 0,
640 
        k2e128_shift  => 0,
641 
        k3e128_offset => 0,
642 
        k3e128_shift  => 0,
643 
        k4e128_offset => 0,
644 
        k4e128_shift  => 0,
645 
        k5e128_offset => 0,
646 
        k5e128_shift  => 0,
647 
        k6e128_offset => 0,
648 
        k6e128_shift  => 0,
649 
        k1d128_offset => 0,
650 
        k1d128_shift  => 0,
651 
        k2d128_offset => 0,
652 
        k2d128_shift  => 0,
653 
        k3d128_offset => 0,
654 
        k3d128_shift  => 0,
655 
        k4d128_offset => 0,
656 
        k4d128_shift  => 0,
657 
        k5d128_offset => 0,
658 
        k5d128_shift  => 0,
659 
        k6d128_offset => 0,
660 
        k6d128_shift  => 0,
661 
        k1e256_offset => KR_OFFSET,
662 
        k1e256_shift  => 94,
663 
        k2e256_offset => KR_OFFSET,
664 
        k2e256_shift  => 94,
665 
        k3e256_offset => KA_OFFSET,
666 
        k3e256_shift  => 94,
667 
        k4e256_offset => KA_OFFSET,
668 
        k4e256_shift  => 94,
669 
        k5e256_offset => KL_OFFSET,
670 
        k5e256_shift  => 111,
671 
        k6e256_offset => KL_OFFSET,
672 
        k6e256_shift  => 111,
673 
        k1d256_offset => KA_OFFSET,
674 
        k1d256_shift  => 15,
675 
        k2d256_offset => KA_OFFSET,
676 
        k2d256_shift  => 15,
677 
        k3d256_offset => KR_OFFSET,
678 
        k3d256_shift  => 15,
679 
        k4d256_offset => KR_OFFSET,
680 
        k4d256_shift  => 15,
681 
        k5d256_offset => KB_OFFSET,
682 
        k5d256_shift  => 0,
683 
        k6d256_offset => KB_OFFSET,
684 
        k6d256_shift  => 0
685 
    )
686 
    PORT MAP(
687 
        reset   => reset,
688 
        clk     => clk,
689 
        dec1    => reg_b21_dec,
690 
        k_len1  => reg_b21_klen,
691 
        k1      => reg_b21_k,
692 
        dec2    => reg_b22_dec,
693 
        k_len2  => reg_b22_klen,
694 
        k2      => reg_b22_k,
695 
        dec3    => reg_b23_dec,
696 
        k_len3  => reg_b23_klen,
697 
        k3      => reg_b23_k,
698 
        dec4    => reg_b24_dec,
699 
        k_len4  => reg_b24_klen,
700 
        k4      => reg_b24_k,
701 
        dec5    => reg_b25_dec,
702 
        k_len5  => reg_b25_klen,
703 
        k5      => reg_b25_k,
704 
        dec6    => reg_b26_dec,
705 
        k_len6  => reg_b26_klen,
706 
        k6      => reg_b26_k,
707 
        l_in    => out_fl3l,
708 
        r_in    => out_fl3r,
709 
        l_out   => out_r4l,
710 
        r_out   => out_r4r
711 
    );
712 
 
713 
    FL1: FL256
714 
    GENERIC MAP (
715 
            fl_ke128_offset  => KA_OFFSET,
716 
            fl_ke128_shift   => 30,
717 
            fli_ke128_offset => KA_OFFSET,
718 
            fli_ke128_shift  => 30,
719 
            fl_kd128_offset  => KL_OFFSET,
720 
            fl_kd128_shift   => 77,
721 
            fli_kd128_offset => KL_OFFSET,
722 
            fli_kd128_shift  => 77,
723 
            fl_ke256_offset  => KR_OFFSET,
724 
            fl_ke256_shift   => 30,
725 
            fli_ke256_offset => KR_OFFSET,
726 
            fli_ke256_shift  => 30,
727 
            fl_kd256_offset  => KA_OFFSET,
728 
            fl_kd256_shift   => 77,
729 
            fli_kd256_offset => KA_OFFSET,
730 
            fli_kd256_shift  => 77
731 
            )
732 
    PORT MAP (
733 
            reset   => reset,
734 
            clk     => clk,
735 
            fl_in   => out_r1l,
736 
            fli_in  => out_r1r,
737 
            k       => reg_b7_k,
738 
            k_len   => reg_b7_klen,
739 
            dec     => reg_b7_dec,
740 
            fl_out  => out_fl1l,
741 
            fli_out => out_fl1r
742 
            );
743 
 
744 
    FL2: FL256
745 
    GENERIC MAP (
746 
            fl_ke128_offset  => KL_OFFSET,
747 
            fl_ke128_shift   => 77,
748 
            fli_ke128_offset => KL_OFFSET,
749 
            fli_ke128_shift  => 77,
750 
            fl_kd128_offset  => KA_OFFSET,
751 
            fl_kd128_shift   => 30,
752 
            fli_kd128_offset => KA_OFFSET,
753 
            fli_kd128_shift  => 30,
754 
            fl_ke256_offset  => KL_OFFSET,
755 
            fl_ke256_shift   => 60,
756 
            fli_ke256_offset => KL_OFFSET,
757 
            fli_ke256_shift  => 60,
758 
            fl_kd256_offset  => KL_OFFSET,
759 
            fl_kd256_shift   => 60,
760 
            fli_kd256_offset => KL_OFFSET,
761 
            fli_kd256_shift  => 60
762 
            )
763 
    PORT MAP (
764 
            reset   => reset,
765 
            clk     => clk,
766 
            fl_in   => out_r2l,
767 
            fli_in  => out_r2r,
768 
            k       => reg_b14_k,
769 
            k_len   => reg_b14_klen,
770 
            dec     => reg_b14_dec,
771 
            fl_out  => out_fl2l,
772 
            fli_out => out_fl2r
773 
            );
774 
 
775 
    FL3: FL256
776 
    GENERIC MAP (
777 
            fl_ke128_offset  => 0,
778 
            fl_ke128_shift   => 0,
779 
            fli_ke128_offset => 0,
780 
            fli_ke128_shift  => 0,
781 
            fl_kd128_offset  => 0,
782 
            fl_kd128_shift   => 0,
783 
            fli_kd128_offset => 0,
784 
            fli_kd128_shift  => 0,
785 
            fl_ke256_offset  => KA_OFFSET,
786 
            fl_ke256_shift   => 77,
787 
            fli_ke256_offset => KA_OFFSET,
788 
            fli_ke256_shift  => 77,
789 
            fl_kd256_offset  => KR_OFFSET,
790 
            fl_kd256_shift   => 30,
791 
            fli_kd256_offset => KR_OFFSET,
792 
            fli_kd256_shift  => 30
793 
            )
794 
    PORT MAP (
795 
            reset   => reset,
796 
            clk     => clk,
797 
            fl_in   => out_r3l,
798 
            fli_in  => out_r3r,
799 
            k       => reg_b21_k,
800 
            k_len   => reg_b21_klen,
801 
            dec     => reg_b21_dec,
802 
            fl_out  => out_fl3l,
803 
            fli_out => out_fl3r
804 
            );
805 
 
806 
 
807 
    process(reset, clk)
808 
    begin
809 
        if(reset = '1') then
810 
            reg_m       <= (others=>'0');
811 
            reg_kl      <= (others=>'0');
812 
            reg_kr_int  <= (others=>'0');
813 
            reg_k_len   <= (others=>'0');
814 8 pfulgoni 
 
815 2 pfulgoni 
            reg_dec     <= '0';
816 8 pfulgoni 
            reg_rdy     <= '0';
817 
            reg_a1_rdy  <= '0';
818 
            reg_a2_rdy  <= '0';
819 
            reg_a3_rdy  <= '0';
820 
            reg_a4_rdy  <= '0';
821 
            reg_a5_rdy  <= '0';
822 
            reg_a6_rdy  <= '0';
823 
            reg_b1_rdy  <= '0';
824 
            reg_b2_rdy  <= '0';
825 
            reg_b3_rdy  <= '0';
826 
            reg_b4_rdy  <= '0';
827 
            reg_b5_rdy  <= '0';
828 
            reg_b6_rdy  <= '0';
829 
            reg_b7_rdy  <= '0';
830 
            reg_b8_rdy  <= '0';
831 
            reg_b9_rdy  <= '0';
832 
            reg_b10_rdy <= '0';
833 
            reg_b11_rdy <= '0';
834 
            reg_b12_rdy <= '0';
835 
            reg_b13_rdy <= '0';
836 
            reg_b14_rdy <= '0';
837 
            reg_b15_rdy <= '0';
838 
            reg_b16_rdy <= '0';
839 
            reg_b17_rdy <= '0';
840 
            reg_b18_rdy <= '0';
841 
            reg_b19_rdy <= '0';
842 
            reg_b20_rdy <= '0';
843 
            reg_b21_rdy <= '0';
844 
            reg_b22_rdy <= '0';
845 
            reg_b23_rdy <= '0';
846 
            reg_b24_rdy <= '0';
847 
            reg_b25_rdy <= '0';
848 
            reg_b26_rdy <= '0';
849 
            reg_b27_rdy <= '0';
850 
            output_rdy  <= '0';
851 
        elsif(rising_edge(clk)) then
852 
            reg_m       <= input;
853 
            reg_kl      <= key(0 to 127);
854 2 pfulgoni 
            reg_kr_int  <= kr_int;
855 8 pfulgoni 
            reg_dec     <= enc_dec;
856 
            reg_k_len   <= key_len;
857 
            reg_rdy     <= input_en;
858 2 pfulgoni 
 
859 
            reg_a1_m    <= reg_m;
860 
            reg_a1_dec  <= reg_dec;
861 
            reg_a1_klen <= reg_k_len;
862 8 pfulgoni 
            reg_a1_rdy  <= reg_rdy;
863 2 pfulgoni 
            reg_a2_m    <= reg_a1_m;
864 
            reg_a2_dec  <= reg_a1_dec;
865 
            reg_a2_klen <= reg_a1_klen;
866 8 pfulgoni 
            reg_a2_rdy  <= reg_a1_rdy;
867 2 pfulgoni 
            reg_a3_m    <= reg_a2_m;
868 
            reg_a3_dec  <= reg_a2_dec;
869 
            reg_a3_klen <= reg_a2_klen;
870 8 pfulgoni 
            reg_a3_rdy  <= reg_a2_rdy;
871 2 pfulgoni 
            reg_a4_m    <= reg_a3_m;
872 
            reg_a4_dec  <= reg_a3_dec;
873 
            reg_a4_klen <= reg_a3_klen;
874 8 pfulgoni 
            reg_a4_rdy  <= reg_a3_rdy;
875 2 pfulgoni 
            reg_a5_m    <= reg_a4_m;
876 
            reg_a5_dec  <= reg_a4_dec;
877 
            reg_a5_klen <= reg_a4_klen;
878 8 pfulgoni 
            reg_a5_rdy  <= reg_a4_rdy;
879 2 pfulgoni 
            reg_a6_m    <= reg_a5_m;
880 
            reg_a6_dec  <= reg_a5_dec;
881 
            reg_a6_klen <= reg_a5_klen;
882 8 pfulgoni 
            reg_a6_rdy  <= reg_a5_rdy;
883 2 pfulgoni 
 
884 
            reg_b1_dec  <= reg_a6_dec;
885 
            reg_b1_k    <= out_ksched;
886 
            reg_b1_klen <= reg_a6_klen;
887 8 pfulgoni 
            reg_b1_rdy  <= reg_a6_rdy;
888 2 pfulgoni 
            reg_b2_dec  <= reg_b1_dec;
889 
            reg_b2_k    <= reg_b1_k;
890 
            reg_b2_klen <= reg_b1_klen;
891 8 pfulgoni 
            reg_b2_rdy  <= reg_b1_rdy;
892 2 pfulgoni 
            reg_b3_dec  <= reg_b2_dec;
893 
            reg_b3_k    <= reg_b2_k;
894 
            reg_b3_klen <= reg_b2_klen;
895 8 pfulgoni 
            reg_b3_rdy  <= reg_b2_rdy;
896 2 pfulgoni 
            reg_b4_dec  <= reg_b3_dec;
897 
            reg_b4_k    <= reg_b3_k;
898 
            reg_b4_klen <= reg_b3_klen;
899 8 pfulgoni 
            reg_b4_rdy  <= reg_b3_rdy;
900 2 pfulgoni 
            reg_b5_dec  <= reg_b4_dec;
901 
            reg_b5_k    <= reg_b4_k;
902 
            reg_b5_klen <= reg_b4_klen;
903 8 pfulgoni 
            reg_b5_rdy  <= reg_b4_rdy;
904 2 pfulgoni 
            reg_b6_dec  <= reg_b5_dec;
905 
            reg_b6_k    <= reg_b5_k;
906 
            reg_b6_klen <= reg_b5_klen;
907 8 pfulgoni 
            reg_b6_rdy  <= reg_b5_rdy;
908 2 pfulgoni 
            reg_b7_dec  <= reg_b6_dec;
909 
            reg_b7_k    <= reg_b6_k;
910 
            reg_b7_klen <= reg_b6_klen;
911 8 pfulgoni 
            reg_b7_rdy  <= reg_b6_rdy;
912 2 pfulgoni 
            reg_b8_dec  <= reg_b7_dec;
913 
            reg_b8_k    <= reg_b7_k;
914 
            reg_b8_klen <= reg_b7_klen;
915 8 pfulgoni 
            reg_b8_rdy  <= reg_b7_rdy;
916 2 pfulgoni 
            reg_b9_dec  <= reg_b8_dec;
917 
            reg_b9_k    <= reg_b8_k;
918 
            reg_b9_klen <= reg_b8_klen;
919 8 pfulgoni 
            reg_b9_rdy  <= reg_b8_rdy;
920 2 pfulgoni 
            reg_b10_dec  <= reg_b9_dec;
921 
            reg_b10_k    <= reg_b9_k;
922 
            reg_b10_klen <= reg_b9_klen;
923 8 pfulgoni 
            reg_b10_rdy  <= reg_b9_rdy;
924 2 pfulgoni 
            reg_b11_dec  <= reg_b10_dec;
925 
            reg_b11_k    <= reg_b10_k;
926 
            reg_b11_klen <= reg_b10_klen;
927 8 pfulgoni 
            reg_b11_rdy  <= reg_b10_rdy;
928 2 pfulgoni 
            reg_b12_dec  <= reg_b11_dec;
929 
            reg_b12_k    <= reg_b11_k;
930 
            reg_b12_klen <= reg_b11_klen;
931 8 pfulgoni 
            reg_b12_rdy  <= reg_b11_rdy;
932 2 pfulgoni 
            reg_b13_dec  <= reg_b12_dec;
933 
            reg_b13_k    <= reg_b12_k;
934 
            reg_b13_klen <= reg_b12_klen;
935 8 pfulgoni 
            reg_b13_rdy  <= reg_b12_rdy;
936 2 pfulgoni 
            reg_b14_dec  <= reg_b13_dec;
937 
            reg_b14_k    <= reg_b13_k;
938 
            reg_b14_klen <= reg_b13_klen;
939 8 pfulgoni 
            reg_b14_rdy  <= reg_b13_rdy;
940 2 pfulgoni 
            reg_b15_dec  <= reg_b14_dec;
941 
            reg_b15_k    <= reg_b14_k;
942 
            reg_b15_klen <= reg_b14_klen;
943 8 pfulgoni 
            reg_b15_rdy  <= reg_b14_rdy;
944 2 pfulgoni 
            reg_b16_dec  <= reg_b15_dec;
945 
            reg_b16_k    <= reg_b15_k;
946 
            reg_b16_klen <= reg_b15_klen;
947 8 pfulgoni 
            reg_b16_rdy  <= reg_b15_rdy;
948 2 pfulgoni 
            reg_b17_dec  <= reg_b16_dec;
949 
            reg_b17_k    <= reg_b16_k;
950 
            reg_b17_klen <= reg_b16_klen;
951 8 pfulgoni 
            reg_b17_rdy  <= reg_b16_rdy;
952 2 pfulgoni 
            reg_b18_dec  <= reg_b17_dec;
953 
            reg_b18_k    <= reg_b17_k;
954 
            reg_b18_klen <= reg_b17_klen;
955 8 pfulgoni 
            reg_b18_rdy  <= reg_b17_rdy;
956 2 pfulgoni 
            reg_b19_dec  <= reg_b18_dec;
957 
            reg_b19_k    <= reg_b18_k;
958 
            reg_b19_klen <= reg_b18_klen;
959 8 pfulgoni 
            reg_b19_rdy  <= reg_b18_rdy;
960 2 pfulgoni 
            reg_b20_dec  <= reg_b19_dec;
961 
            reg_b20_k    <= reg_b19_k;
962 
            reg_b20_klen <= reg_b19_klen;
963 8 pfulgoni 
            reg_b20_rdy  <= reg_b19_rdy;
964 2 pfulgoni 
            reg_b21_dec  <= reg_b20_dec;
965 
            reg_b21_k    <= reg_b20_k;
966 
            reg_b21_klen <= reg_b20_klen;
967 8 pfulgoni 
            reg_b21_rdy  <= reg_b20_rdy;
968 2 pfulgoni 
            reg_b22_dec  <= reg_b21_dec;
969 
            reg_b22_k    <= reg_b21_k;
970 
            reg_b22_klen <= reg_b21_klen;
971 8 pfulgoni 
            reg_b22_rdy  <= reg_b21_rdy;
972 2 pfulgoni 
            reg_b23_dec  <= reg_b22_dec;
973 
            reg_b23_k    <= reg_b22_k;
974 
            reg_b23_klen <= reg_b22_klen;
975 8 pfulgoni 
            reg_b23_rdy  <= reg_b22_rdy;
976 2 pfulgoni 
            reg_b24_dec  <= reg_b23_dec;
977 
            reg_b24_k    <= reg_b23_k;
978 
            reg_b24_klen <= reg_b23_klen;
979 8 pfulgoni 
            reg_b24_rdy  <= reg_b23_rdy;
980 2 pfulgoni 
            reg_b25_dec  <= reg_b24_dec;
981 
            reg_b25_k    <= reg_b24_k;
982 
            reg_b25_klen <= reg_b24_klen;
983 8 pfulgoni 
            reg_b25_rdy  <= reg_b24_rdy;
984 2 pfulgoni 
            reg_b26_dec  <= reg_b25_dec;
985 
            reg_b26_k    <= reg_b25_k;
986 
            reg_b26_klen <= reg_b25_klen;
987 8 pfulgoni 
            reg_b26_rdy  <= reg_b25_rdy;
988 2 pfulgoni 
            reg_b27_dec  <= reg_b26_dec;
989 
            reg_b27_k    <= reg_b26_k;
990 
            reg_b27_klen <= reg_b26_klen;
991 8 pfulgoni 
            reg_b27_rdy  <= reg_b26_rdy;
992 2 pfulgoni 
 
993 
            reg_l128_1  <= out_r3l;
994 
            reg_r128_1  <= out_r3r;
995 
            reg_l128_2  <= reg_l128_1;
996 
            reg_r128_2  <= reg_r128_1;
997 
            reg_l128_3  <= reg_l128_2;
998 
            reg_r128_3  <= reg_r128_2;
999 
            reg_l128_4  <= reg_l128_3;
1000 
            reg_r128_4  <= reg_r128_3;
1001 
            reg_l128_5  <= reg_l128_4;
1002 
            reg_r128_5  <= reg_r128_4;
1003 
            reg_l128_6  <= reg_l128_5;
1004 
            reg_r128_6  <= reg_r128_5;
1005 
            reg_l128_7  <= reg_l128_6;
1006 
            reg_r128_7  <= reg_r128_6;
1007 
 
1008 
            -- output
1009 8 pfulgoni 
            output <= w3 & w4;
1010 
                        output_rdy <= reg_b27_rdy;
1011 2 pfulgoni 
 
1012 
        end if;
1013 
    end process;
1014 
 
1015 
    --kr depends on key lenght
1016 8 pfulgoni 
    kr_int <= (others=>'0') when key_len(0)='0' else
1017 
              key(128 to 191) & not key(128 to 191) when key_len="10" else
1018 
              key(128 to 255);
1019 2 pfulgoni 
 
1020 
    -- pre-whitening
1021 
    kw1_enc <= out_ksched(KL_OFFSET to KL_OFFSET+63);
1022 
    kw2_enc <= out_ksched(KL_OFFSET+64 to KL_OFFSET+127);
1023 
 
1024 
    ka_s111_dec128 <= out_ksched(KA_OFFSET+111 to KA_OFFSET+127) &
1025 
                      out_ksched(KA_OFFSET to KA_OFFSET+110);
1026 
    kw1_dec128 <= ka_s111_dec128(0 to 63);
1027 
    kw2_dec128 <= ka_s111_dec128(64 to 127);
1028 
 
1029 
    ka_s111_dec256 <= out_ksched(KB_OFFSET+111 to KB_OFFSET+127) &
1030 
                      out_ksched(KB_OFFSET to KB_OFFSET+110);
1031 
    kw1_dec256 <= ka_s111_dec256(0 to 63);
1032 
    kw2_dec256 <= ka_s111_dec256(64 to 127);
1033 
 
1034 
    kw1 <= kw1_dec128 when reg_a6_dec='1' and reg_a6_klen(0)='0' else
1035 
           kw1_dec256 when reg_a6_dec='1' and reg_a6_klen(0)='1' else
1036 
           kw1_enc;
1037 
    kw2 <= kw2_dec128 when reg_a6_dec='1' and reg_a6_klen(0)='0' else
1038 
           kw2_dec256 when reg_a6_dec='1' and reg_a6_klen(0)='1' else
1039 
           kw2_enc;
1040 
 
1041 
    w1 <= reg_a6_m(0 to 63) xor kw1;
1042 
    w2 <= reg_a6_m(64 to 127) xor kw2;
1043 
 
1044 
    -- post-whitening
1045 
    ka_s111_enc128 <= reg_b27_k(KA_OFFSET+111 to KA_OFFSET+127) &
1046 
                      reg_b27_k(KA_OFFSET to KA_OFFSET+110);
1047 
    kw3_enc128 <= ka_s111_enc128(0 to 63);
1048 
    kw4_enc128 <= ka_s111_enc128(64 to 127);
1049 
 
1050 
    ka_s111_enc256 <= reg_b27_k(KB_OFFSET+111 to KB_OFFSET+127) &
1051 
                      reg_b27_k(KB_OFFSET to KB_OFFSET+110);
1052 
    kw3_enc256 <= ka_s111_enc256(0 to 63);
1053 
    kw4_enc256 <= ka_s111_enc256(64 to 127);
1054 
 
1055 
    kw3_dec <= reg_b27_k(KL_OFFSET to KL_OFFSET+63);
1056 
    kw4_dec <= reg_b27_k(KL_OFFSET+64 to KL_OFFSET+127);
1057 
 
1058 
    kw3 <= kw3_enc128 when reg_b27_dec='0' and reg_b27_klen(0)='0' else
1059 
           kw3_enc256 when reg_b27_dec='0' and reg_b27_klen(0)='1' else
1060 
           kw3_dec;
1061 
    kw4 <= kw4_enc128 when reg_b27_dec='0' and reg_b27_klen(0)='0' else
1062 
           kw4_enc256 when reg_b27_dec='0' and reg_b27_klen(0)='1' else
1063 
           kw4_dec;
1064 
 
1065 
 
1066 
    w3 <= reg_r128_7 xor kw3 when reg_b27_klen(0)='0' else
1067 
          out_r4r xor kw3;
1068 
    w4 <= reg_l128_7 xor kw4 when reg_b27_klen(0)='0' else
1069 
          out_r4l xor kw4;
1070 
 
1071 
end RTL;

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