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pfulgoni |
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--------------------------------------------------------------------------------
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-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
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--
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-- Create Date: 09/14/2007
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pfulgoni |
-- Last Update: 04/09/2008
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pfulgoni |
-- Project Name: camellia-vhdl
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-- Description: Key schedule only for 128-bit keys
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--
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-- Copyright (C) 2007 Paolo Fulgoni
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-- This file is part of camellia-vhdl.
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-- camellia-vhdl is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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-- camellia-vhdl is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
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-- Mitsubishi Electric researchers.
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-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity KEYSCHED128 is
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port (
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reset : in STD_LOGIC;
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clk : in STD_LOGIC;
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kl_in : in STD_LOGIC_VECTOR (0 to 127);
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kl_out : out STD_LOGIC_VECTOR (0 to 127);
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ka_out : out STD_LOGIC_VECTOR (0 to 127)
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);
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end KEYSCHED128;
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architecture RTL of KEYSCHED128 is
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component F is
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port (
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reset : in STD_LOGIC;
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clk : in STD_LOGIC;
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x : in STD_LOGIC_VECTOR (0 to 63);
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k : in STD_LOGIC_VECTOR (0 to 63);
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z : out STD_LOGIC_VECTOR (0 to 63)
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);
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end component;
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-- f inputs
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signal f1_in : STD_LOGIC_VECTOR (0 to 63);
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signal f2_in : STD_LOGIC_VECTOR (0 to 63);
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signal f3_in : STD_LOGIC_VECTOR (0 to 63);
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signal f4_in : STD_LOGIC_VECTOR (0 to 63);
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-- f outputs
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signal f1_out : STD_LOGIC_VECTOR (0 to 63);
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signal f2_out : STD_LOGIC_VECTOR (0 to 63);
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signal f3_out : STD_LOGIC_VECTOR (0 to 63);
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signal f4_out : STD_LOGIC_VECTOR (0 to 63);
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-- intermediate registers
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signal reg1_l : STD_LOGIC_VECTOR (0 to 63);
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signal reg1_r : STD_LOGIC_VECTOR (0 to 63);
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signal reg1_kl : STD_LOGIC_VECTOR (0 to 127);
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signal reg2_l : STD_LOGIC_VECTOR (0 to 63);
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signal reg2_r : STD_LOGIC_VECTOR (0 to 63);
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signal reg2_kl : STD_LOGIC_VECTOR (0 to 127);
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signal reg3_l : STD_LOGIC_VECTOR (0 to 63);
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signal reg3_r : STD_LOGIC_VECTOR (0 to 63);
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signal reg3_kl : STD_LOGIC_VECTOR (0 to 127);
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signal reg4_l : STD_LOGIC_VECTOR (0 to 63);
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signal reg4_r : STD_LOGIC_VECTOR (0 to 63);
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signal reg4_kl : STD_LOGIC_VECTOR (0 to 127);
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-- constant keys
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constant k1 : STD_LOGIC_VECTOR (0 to 63) := X"A09E667F3BCC908B";
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constant k2 : STD_LOGIC_VECTOR (0 to 63) := X"B67AE8584CAA73B2";
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constant k3 : STD_LOGIC_VECTOR (0 to 63) := X"C6EF372FE94F82BE";
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constant k4 : STD_LOGIC_VECTOR (0 to 63) := X"54FF53A5F1D36F1C";
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-- intermediate signal
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signal inter : STD_LOGIC_VECTOR (0 to 127);
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begin
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F1 : F
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port map(reset, clk, f1_in, k1, f1_out);
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F2 : F
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port map(reset, clk, f2_in, k2, f2_out);
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F3 : F
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port map(reset, clk, f3_in, k3, f3_out);
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F4 : F
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port map(reset, clk, f4_in, k4, f4_out);
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REG : process(reset, clk)
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begin
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if (reset = '1') then
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reg1_l <= (others=>'0');
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reg1_r <= (others=>'0');
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reg1_kl <= (others=>'0');
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reg2_l <= (others=>'0');
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reg2_r <= (others=>'0');
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reg2_kl <= (others=>'0');
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reg3_l <= (others=>'0');
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reg3_r <= (others=>'0');
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reg3_kl <= (others=>'0');
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reg4_l <= (others=>'0');
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reg4_r <= (others=>'0');
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reg4_kl <= (others=>'0');
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else
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if (rising_edge(clk)) then -- rising clock edge
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reg1_l <= f1_in;
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reg1_r <= kl_in(64 to 127);
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reg1_kl <= kl_in;
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reg2_l <= f2_in;
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reg2_r <= reg1_l;
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reg2_kl <= reg1_kl;
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reg3_l <= f3_in;
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reg3_r <= inter(64 to 127);
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reg3_kl <= reg2_kl;
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reg4_l <= f4_in;
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reg4_r <= reg3_l;
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reg4_kl <= reg3_kl;
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end if;
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end if;
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end process;
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inter <= ((f2_out xor reg2_r) & reg2_l) xor reg2_kl;
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-- f inputs
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f1_in <= kl_in(0 to 63);
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f2_in <= f1_out xor reg1_r;
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f3_in <= inter(0 to 63);
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f4_in <= f3_out xor reg3_r;
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-- output
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kl_out <= reg4_kl;
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ka_out <= (f4_out xor reg4_r) & reg4_l;
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end RTL;
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