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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.11  2003/02/09 18:40:29  mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.10  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.9  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.8  2003/01/10 17:51:34  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.6  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.5  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Mode register */
  reset_mode,
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  clk_en,
  sample_point,
  sampled_bit,
  sampled_bit_q,
  tx_point,
  hard_sync,
  go_seg1,
 
  /* Output from can_bsp module */
  rx_idle,
  transmitting,
  overjump_sync_seg,
  last_bit_of_inter
 
 
 
 
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
  /* Mode register */
input         reset_mode;
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output from can_bsp module */
input         rx_idle;
input         transmitting;
input         overjump_sync_seg;
input         last_bit_of_inter;
 
/* Output signals from this module */
output        clk_en;
output        sample_point;
output        sampled_bit;
output        sampled_bit_q;
output        tx_point;
output        hard_sync;
output        go_seg1;
 
 
 
reg     [8:0] clk_cnt;
reg           clk_en;
reg           sync_blocked;
reg           resync_blocked;
reg           sampled_bit;
reg           sampled_bit_q;
reg     [7:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_point;
reg     [1:0] sample;
 
wire          go_sync;
wire          go_seg1;
wire          go_seg2;
wire [8:0]    preset_cnt;
wire          sync_window;
wire          resync;
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   (rx_idle | last_bit_of_inter)  & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting);  // Hard synchronization
assign resync     =  (~rx_idle)                      & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting);  // Re-synchronization
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_cnt <= 0;
  else if (clk_cnt == (preset_cnt-1))
    clk_cnt <=#Tp 0;
  else
    clk_cnt <=#Tp clk_cnt + 1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en  <= 1'b0;
  else if (clk_cnt == (preset_cnt-1))
    clk_en  <=#Tp 1'b1;
  else
    clk_en  <=#Tp 1'b0;
end
 
 
 
/* Changing states */
 assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));
 assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
 assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
 
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 0;
  else if (go_sync)
    sync <=#Tp 1'b1;
  else if (go_seg1)
    sync <=#Tp 1'b0;
end
 
 
assign tx_point = go_sync;
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 1;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 0;
  else if (go_sync | go_seg1 & (~overjump_sync_seg) | go_seg2)
    quant_cnt <=#Tp 0;
  else if (go_seg1 & overjump_sync_seg)
    quant_cnt <=#Tp 1;
  else if (clk_en)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 0;
  else if (clk_en & resync & seg1)
    delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);
  else if (go_sync | go_seg1)
    delay <=#Tp 0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sampled_bit_q <= 1;
      sample_point <= 0;
    end
  else if (clk_en & (~hard_sync))
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_point <=#Tp 1;
          sampled_bit_q <=#Tp sampled_bit;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_point <=#Tp 0;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b0;
  else if (clk_en)
    begin
      if (hard_sync | resync)
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & quant_cnt == time_segment2)
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
/* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for
   end-of-frame and interframe. No resynchronization is needed meanwhile). */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_blocked <=#Tp 1'b1;
  else if (reset_mode)
    resync_blocked <=#Tp 1'b1;
  else if (hard_sync)
    resync_blocked <=#Tp 1'b0;
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	2	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	75	mohor	`// Revision 1.12 2003/02/14 20:17:01 mohor`
54			`// Several registers added. Not finished, yet.`
55			`//`
56	35	mohor	`// Revision 1.11 2003/02/09 18:40:29 mohor`
57			`// Overload fixed. Hard synchronization also enabled at the last bit of`
58			`// interframe.`
59			`//`
60	29	mohor	`// Revision 1.10 2003/02/09 02:24:33 mohor`
61			`// Bosch license warning added. Error counters finished. Overload frames`
62			`// still need to be fixed.`
63			`//`
64	28	mohor	`// Revision 1.9 2003/01/31 01:13:38 mohor`
65			`// backup.`
66			`//`
67	24	mohor	`// Revision 1.8 2003/01/10 17:51:34 mohor`
68			`// Temporary version (backup).`
69			`//`
70	15	mohor	`// Revision 1.7 2003/01/08 02:10:53 mohor`
71			`// Acceptance filter added.`
72			`//`
73	11	mohor	`// Revision 1.6 2002/12/28 04:13:23 mohor`
74			`// Backup version.`
75			`//`
76	10	mohor	`// Revision 1.5 2002/12/27 00:12:52 mohor`
77			`// Header changed, testbench improved to send a frame (crc still missing).`
78			`//`
79	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
80			`// Tripple sampling supported.`
81			`//`
82	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
83			`// Commented lines removed.`
84			`//`
85	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
86			`// Synchronization working.`
87			`//`
88	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
89			`// Initial`
90	2	mohor	`//`
91			`//`
92	5	mohor	`//`
93	2	mohor
94			`// synopsys translate_off`
95			`include "timescale.v"
96			`// synopsys translate_on`
97			`include "can_defines.v"
98
99			`module can_btl`
100			`(`
101			`clk,`
102			`rst,`
103			`rx,`
104
105			`/* Mode register */`
106	10	mohor	`reset_mode,`
107	2	mohor
108			`/* Bus Timing 0 register */`
109			`baud_r_presc,`
110			`sync_jump_width,`
111
112			`/* Bus Timing 1 register */`
113			`time_segment1,`
114			`time_segment2,`
115			`triple_sampling,`
116
117			`/* Output signals from this module */`
118			`clk_en,`
119	10	mohor	`sample_point,`
120			`sampled_bit,`
121			`sampled_bit_q,`
122	24	mohor	`tx_point,`
123	11	mohor	`hard_sync,`
124	75	mohor	`go_seg1,`
125	2	mohor
126	10	mohor	`/* Output from can_bsp module */`
127	24	mohor	`rx_idle,`
128	29	mohor	`transmitting,`
129	75	mohor	`overjump_sync_seg,`
130	29	mohor	`last_bit_of_inter`
131	2	mohor
132	10	mohor
133	11	mohor
134	2	mohor
135
136			`);`
137
138			`parameter Tp = 1;`
139
140			`input clk;`
141			`input rst;`
142			`input rx;`
143
144	10	mohor	`/* Mode register */`
145	2	mohor	`input reset_mode;`
146
147			`/* Bus Timing 0 register */`
148			`input [5:0] baud_r_presc;`
149			`input [1:0] sync_jump_width;`
150
151			`/* Bus Timing 1 register */`
152			`input [3:0] time_segment1;`
153			`input [2:0] time_segment2;`
154			`input triple_sampling;`
155
156	10	mohor	`/* Output from can_bsp module */`
157			`input rx_idle;`
158	24	mohor	`input transmitting;`
159	75	mohor	`input overjump_sync_seg;`
160	29	mohor	`input last_bit_of_inter;`
161	10	mohor
162	2	mohor	`/* Output signals from this module */`
163			`output clk_en;`
164	10	mohor	`output sample_point;`
165			`output sampled_bit;`
166			`output sampled_bit_q;`
167	24	mohor	`output tx_point;`
168	11	mohor	`output hard_sync;`
169	75	mohor	`output go_seg1;`
170	2	mohor
171
172
173			`reg [8:0] clk_cnt;`
174			`reg clk_en;`
175	5	mohor	`reg sync_blocked;`
176	24	mohor	`reg resync_blocked;`
177	2	mohor	`reg sampled_bit;`
178	10	mohor	`reg sampled_bit_q;`
179	2	mohor	`reg [7:0] quant_cnt;`
180	6	mohor	`reg [3:0] delay;`
181			`reg sync;`
182			`reg seg1;`
183			`reg seg2;`
184			`reg resync_latched;`
185	10	mohor	`reg sample_point;`
186	7	mohor	`reg [1:0] sample;`
187	2	mohor
188	6	mohor	`wire go_sync;`
189			`wire go_seg1;`
190			`wire go_seg2;`
191			`wire [8:0] preset_cnt;`
192			`wire sync_window;`
193	75	mohor	`wire resync;`
194	2	mohor
195	5	mohor
196	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
197	29	mohor	`assign hard_sync = (rx_idle \| last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Hard synchronization`
198			`assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting); // Re-synchronization`
199	5	mohor
200
201	6	mohor	`/* Generating general enable signal that defines baud rate. */`
202	2	mohor	`always @ (posedge clk or posedge rst)`
203			`begin`
204			`if (rst)`
205	10	mohor	`clk_cnt <= 0;`
206	35	mohor	`else if (clk_cnt == (preset_cnt-1))`
207	10	mohor	`clk_cnt <=#Tp 0;`
208			`else`
209			`clk_cnt <=#Tp clk_cnt + 1;`
210			`end`
211
212
213			`always @ (posedge clk or posedge rst)`
214			`begin`
215			`if (rst)`
216			`clk_en <= 1'b0;`
217	2	mohor	`else if (clk_cnt == (preset_cnt-1))`
218	10	mohor	`clk_en <=#Tp 1'b1;`
219	2	mohor	`else`
220	10	mohor	`clk_en <=#Tp 1'b0;`
221	2	mohor	`end`
222
223
224	5	mohor
225	6	mohor	`/* Changing states */`
226	10	mohor	`assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));`
227			`assign go_seg1 = clk_en & (sync \| hard_sync \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
228			`assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));`
229	5	mohor
230
231	10	mohor
232	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
233			`SJW is reached */`
234	2	mohor	`always @ (posedge clk or posedge rst)`
235			`begin`
236			`if (rst)`
237	5	mohor	`resync_latched <= 1'b0;`
238	6	mohor	`else if (resync & seg2 & (~sync_window))`
239	5	mohor	`resync_latched <=#Tp 1'b1;`
240			`else if (go_seg1)`
241			`resync_latched <= 1'b0;`
242			`end`
243
244
245
246	6	mohor	`/* Synchronization stage/segment */`
247	5	mohor	`always @ (posedge clk or posedge rst)`
248			`begin`
249			`if (rst)`
250	10	mohor	`sync <= 0;`
251	5	mohor	`else if (go_sync)`
252			`sync <=#Tp 1'b1;`
253			`else if (go_seg1)`
254			`sync <=#Tp 1'b0;`
255			`end`
256
257
258	24	mohor	`assign tx_point = go_sync;`
259
260	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
261	5	mohor	`always @ (posedge clk or posedge rst)`
262			`begin`
263			`if (rst)`
264	10	mohor	`seg1 <= 1;`
265	5	mohor	`else if (go_seg1)`
266			`seg1 <=#Tp 1'b1;`
267			`else if (go_seg2)`
268			`seg1 <=#Tp 1'b0;`
269			`end`
270
271
272	6	mohor	`/* Seg2 stage/segment */`
273	5	mohor	`always @ (posedge clk or posedge rst)`
274			`begin`
275			`if (rst)`
276			`seg2 <= 0;`
277			`else if (go_seg2)`
278			`seg2 <=#Tp 1'b1;`
279			`else if (go_sync \| go_seg1)`
280			`seg2 <=#Tp 1'b0;`
281			`end`
282
283
284	6	mohor	`/* Quant counter */`
285	5	mohor	`always @ (posedge clk or posedge rst)`
286			`begin`
287			`if (rst)`
288			`quant_cnt <= 0;`
289	75	mohor	`else if (go_sync \| go_seg1 & (~overjump_sync_seg) \| go_seg2)`
290	5	mohor	`quant_cnt <=#Tp 0;`
291	75	mohor	`else if (go_seg1 & overjump_sync_seg)`
292			`quant_cnt <=#Tp 1;`
293	5	mohor	`else if (clk_en)`
294			`quant_cnt <=#Tp quant_cnt + 1'b1;`
295			`end`
296
297
298	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
299	5	mohor	`always @ (posedge clk or posedge rst)`
300			`begin`
301			`if (rst)`
302	6	mohor	`delay <= 0;`
303	5	mohor	`else if (clk_en & resync & seg1)`
304	6	mohor	`delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);`
305	5	mohor	`else if (go_sync \| go_seg1)`
306	6	mohor	`delay <=#Tp 0;`
307	5	mohor	`end`
308
309
310	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
311			`assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));`
312	5	mohor
313
314	7	mohor	`// Sampling data (memorizing two samples all the time).`
315	5	mohor	`always @ (posedge clk or posedge rst)`
316			`begin`
317			`if (rst)`
318	7	mohor	`sample <= 2'b11;`
319			`else if (clk_en)`
320			`sample <= {sample[0], rx};`
321			`end`
322
323
324			`// When enabled, tripple sampling is done here.`
325			`always @ (posedge clk or posedge rst)`
326			`begin`
327			`if (rst)`
328	2	mohor	`begin`
329			`sampled_bit <= 1;`
330	10	mohor	`sampled_bit_q <= 1;`
331			`sample_point <= 0;`
332	2	mohor	`end`
333	15	mohor	`else if (clk_en & (~hard_sync))`
334	2	mohor	`begin`
335	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
336			`begin`
337	10	mohor	`sample_point <=#Tp 1;`
338			`sampled_bit_q <=#Tp sampled_bit;`
339	7	mohor	`if (triple_sampling)`
340			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
341			`else`
342			`sampled_bit <=#Tp rx;`
343			`end`
344	2	mohor	`end`
345	5	mohor	`else`
346	10	mohor	`sample_point <=#Tp 0;`
347	2	mohor	`end`
348
349
350
351	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
352	35	mohor
353	5	mohor	`always @ (posedge clk or posedge rst)`
354			`begin`
355			`if (rst)`
356			`sync_blocked <=#Tp 1'b0;`
357			`else if (clk_en)`
358			`begin`
359	35	mohor	`if (hard_sync \| resync)`
360	5	mohor	`sync_blocked <=#Tp 1'b1;`
361			`else if (seg2 & quant_cnt == time_segment2)`
362			`sync_blocked <=#Tp 1'b0;`
363			`end`
364			`end`
365	2	mohor
366
367	24	mohor	`/* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for`
368			`end-of-frame and interframe. No resynchronization is needed meanwhile). */`
369			`always @ (posedge clk or posedge rst)`
370			`begin`
371			`if (rst)`
372			`resync_blocked <=#Tp 1'b1;`
373			`else if (reset_mode)`
374			`resync_blocked <=#Tp 1'b1;`
375			`else if (hard_sync)`
376			`resync_blocked <=#Tp 1'b0;`
377			`end`
378	2	mohor
379
380	5	mohor
381	24	mohor
382
383	2	mohor	`endmodule`

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