1 |
66 |
mohor |
//////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// can_registers.v ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// ////
|
6 |
|
|
//// This file is part of the CAN Protocol Controller ////
|
7 |
|
|
//// http://www.opencores.org/projects/can/ ////
|
8 |
|
|
//// ////
|
9 |
|
|
//// ////
|
10 |
|
|
//// Author(s): ////
|
11 |
|
|
//// Igor Mohor ////
|
12 |
|
|
//// igorm@opencores.org ////
|
13 |
|
|
//// ////
|
14 |
|
|
//// ////
|
15 |
|
|
//// All additional information is available in the README.txt ////
|
16 |
|
|
//// file. ////
|
17 |
|
|
//// ////
|
18 |
|
|
//////////////////////////////////////////////////////////////////////
|
19 |
|
|
//// ////
|
20 |
|
|
//// Copyright (C) 2002, 2003 Authors ////
|
21 |
|
|
//// ////
|
22 |
|
|
//// This source file may be used and distributed without ////
|
23 |
|
|
//// restriction provided that this copyright statement is not ////
|
24 |
|
|
//// removed from the file and that any derivative work contains ////
|
25 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
26 |
|
|
//// ////
|
27 |
|
|
//// This source file is free software; you can redistribute it ////
|
28 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
29 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
30 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
31 |
|
|
//// later version. ////
|
32 |
|
|
//// ////
|
33 |
|
|
//// This source is distributed in the hope that it will be ////
|
34 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
35 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
36 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
37 |
|
|
//// details. ////
|
38 |
|
|
//// ////
|
39 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
40 |
|
|
//// Public License along with this source; if not, download it ////
|
41 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
42 |
|
|
//// ////
|
43 |
|
|
//// The CAN protocol is developed by Robert Bosch GmbH and ////
|
44 |
|
|
//// protected by patents. Anybody who wants to implement this ////
|
45 |
|
|
//// CAN IP core on silicon has to obtain a CAN protocol license ////
|
46 |
|
|
//// from Bosch. ////
|
47 |
|
|
//// ////
|
48 |
|
|
//////////////////////////////////////////////////////////////////////
|
49 |
|
|
//
|
50 |
|
|
// CVS Revision History
|
51 |
|
|
//
|
52 |
|
|
// $Log: not supported by cvs2svn $
|
53 |
111 |
mohor |
// Revision 1.29 2003/07/10 01:59:04 tadejm
|
54 |
|
|
// Synchronization fixed. In some strange cases it didn't work according to
|
55 |
|
|
// the VHDL reference model.
|
56 |
|
|
//
|
57 |
104 |
tadejm |
// Revision 1.28 2003/07/07 11:21:37 mohor
|
58 |
|
|
// Little fixes (to fix warnings).
|
59 |
|
|
//
|
60 |
102 |
mohor |
// Revision 1.27 2003/06/22 09:43:03 mohor
|
61 |
|
|
// synthesi full_case parallel_case fixed.
|
62 |
|
|
//
|
63 |
93 |
mohor |
// Revision 1.26 2003/06/22 01:33:14 mohor
|
64 |
|
|
// clkout is clk/2 after the reset.
|
65 |
|
|
//
|
66 |
92 |
mohor |
// Revision 1.25 2003/06/21 12:16:30 mohor
|
67 |
|
|
// paralel_case and full_case compiler directives added to case statements.
|
68 |
|
|
//
|
69 |
90 |
mohor |
// Revision 1.24 2003/06/09 11:22:54 mohor
|
70 |
|
|
// data_out is already registered in the can_top.v file.
|
71 |
|
|
//
|
72 |
70 |
mohor |
// Revision 1.23 2003/04/15 15:31:24 mohor
|
73 |
|
|
// Some features are supported in extended mode only (listen_only_mode...).
|
74 |
|
|
//
|
75 |
69 |
mohor |
// Revision 1.22 2003/03/20 16:58:50 mohor
|
76 |
|
|
// unix.
|
77 |
|
|
//
|
78 |
66 |
mohor |
// Revision 1.20 2003/03/11 16:31:05 mohor
|
79 |
|
|
// Mux used for clkout to avoid "gated clocks warning".
|
80 |
|
|
//
|
81 |
|
|
// Revision 1.19 2003/03/10 17:34:25 mohor
|
82 |
|
|
// Doubled declarations removed.
|
83 |
|
|
//
|
84 |
|
|
// Revision 1.18 2003/03/01 22:52:11 mohor
|
85 |
|
|
// Data is latched on read.
|
86 |
|
|
//
|
87 |
|
|
// Revision 1.17 2003/02/19 15:09:02 mohor
|
88 |
|
|
// Incomplete sensitivity list fixed.
|
89 |
|
|
//
|
90 |
|
|
// Revision 1.16 2003/02/19 14:44:03 mohor
|
91 |
|
|
// CAN core finished. Host interface added. Registers finished.
|
92 |
|
|
// Synchronization to the wishbone finished.
|
93 |
|
|
//
|
94 |
|
|
// Revision 1.15 2003/02/18 00:10:15 mohor
|
95 |
|
|
// Most of the registers added. Registers "arbitration lost capture", "error code
|
96 |
|
|
// capture" + few more still need to be added.
|
97 |
|
|
//
|
98 |
|
|
// Revision 1.14 2003/02/14 20:17:01 mohor
|
99 |
|
|
// Several registers added. Not finished, yet.
|
100 |
|
|
//
|
101 |
|
|
// Revision 1.13 2003/02/12 14:25:30 mohor
|
102 |
|
|
// abort_tx added.
|
103 |
|
|
//
|
104 |
|
|
// Revision 1.12 2003/02/11 00:56:06 mohor
|
105 |
|
|
// Wishbone interface added.
|
106 |
|
|
//
|
107 |
|
|
// Revision 1.11 2003/02/09 02:24:33 mohor
|
108 |
|
|
// Bosch license warning added. Error counters finished. Overload frames
|
109 |
|
|
// still need to be fixed.
|
110 |
|
|
//
|
111 |
|
|
// Revision 1.10 2003/01/31 01:13:38 mohor
|
112 |
|
|
// backup.
|
113 |
|
|
//
|
114 |
|
|
// Revision 1.9 2003/01/15 13:16:48 mohor
|
115 |
|
|
// When a frame with "remote request" is received, no data is stored
|
116 |
|
|
// to fifo, just the frame information (identifier, ...). Data length
|
117 |
|
|
// that is stored is the received data length and not the actual data
|
118 |
|
|
// length that is stored to fifo.
|
119 |
|
|
//
|
120 |
|
|
// Revision 1.8 2003/01/14 17:25:09 mohor
|
121 |
|
|
// Addresses corrected to decimal values (previously hex).
|
122 |
|
|
//
|
123 |
|
|
// Revision 1.7 2003/01/14 12:19:35 mohor
|
124 |
|
|
// rx_fifo is now working.
|
125 |
|
|
//
|
126 |
|
|
// Revision 1.6 2003/01/10 17:51:34 mohor
|
127 |
|
|
// Temporary version (backup).
|
128 |
|
|
//
|
129 |
|
|
// Revision 1.5 2003/01/09 14:46:58 mohor
|
130 |
|
|
// Temporary files (backup).
|
131 |
|
|
//
|
132 |
|
|
// Revision 1.4 2003/01/08 02:10:55 mohor
|
133 |
|
|
// Acceptance filter added.
|
134 |
|
|
//
|
135 |
|
|
// Revision 1.3 2002/12/27 00:12:52 mohor
|
136 |
|
|
// Header changed, testbench improved to send a frame (crc still missing).
|
137 |
|
|
//
|
138 |
|
|
// Revision 1.2 2002/12/26 16:00:34 mohor
|
139 |
|
|
// Testbench define file added. Clock divider register added.
|
140 |
|
|
//
|
141 |
|
|
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
|
142 |
|
|
// Initial
|
143 |
|
|
//
|
144 |
|
|
//
|
145 |
|
|
//
|
146 |
|
|
|
147 |
|
|
// synopsys translate_off
|
148 |
|
|
`include "timescale.v"
|
149 |
|
|
// synopsys translate_on
|
150 |
|
|
`include "can_defines.v"
|
151 |
|
|
|
152 |
|
|
module can_registers
|
153 |
|
|
(
|
154 |
|
|
clk,
|
155 |
|
|
rst,
|
156 |
|
|
cs,
|
157 |
|
|
we,
|
158 |
|
|
addr,
|
159 |
|
|
data_in,
|
160 |
|
|
data_out,
|
161 |
|
|
irq,
|
162 |
|
|
|
163 |
|
|
sample_point,
|
164 |
|
|
transmitting,
|
165 |
|
|
set_reset_mode,
|
166 |
|
|
node_bus_off,
|
167 |
|
|
error_status,
|
168 |
|
|
rx_err_cnt,
|
169 |
|
|
tx_err_cnt,
|
170 |
|
|
transmit_status,
|
171 |
|
|
receive_status,
|
172 |
|
|
tx_successful,
|
173 |
|
|
need_to_tx,
|
174 |
|
|
overrun,
|
175 |
|
|
info_empty,
|
176 |
|
|
set_bus_error_irq,
|
177 |
|
|
set_arbitration_lost_irq,
|
178 |
|
|
arbitration_lost_capture,
|
179 |
|
|
node_error_passive,
|
180 |
|
|
node_error_active,
|
181 |
|
|
rx_message_counter,
|
182 |
|
|
|
183 |
|
|
|
184 |
|
|
/* Mode register */
|
185 |
|
|
reset_mode,
|
186 |
|
|
listen_only_mode,
|
187 |
|
|
acceptance_filter_mode,
|
188 |
|
|
self_test_mode,
|
189 |
|
|
|
190 |
|
|
|
191 |
|
|
/* Command register */
|
192 |
|
|
clear_data_overrun,
|
193 |
|
|
release_buffer,
|
194 |
|
|
abort_tx,
|
195 |
|
|
tx_request,
|
196 |
|
|
self_rx_request,
|
197 |
|
|
single_shot_transmission,
|
198 |
104 |
tadejm |
tx_state,
|
199 |
|
|
tx_state_q,
|
200 |
66 |
mohor |
|
201 |
|
|
/* Arbitration Lost Capture Register */
|
202 |
|
|
read_arbitration_lost_capture_reg,
|
203 |
|
|
|
204 |
|
|
/* Error Code Capture Register */
|
205 |
|
|
read_error_code_capture_reg,
|
206 |
|
|
error_capture_code,
|
207 |
|
|
|
208 |
|
|
/* Bus Timing 0 register */
|
209 |
|
|
baud_r_presc,
|
210 |
|
|
sync_jump_width,
|
211 |
|
|
|
212 |
|
|
/* Bus Timing 1 register */
|
213 |
|
|
time_segment1,
|
214 |
|
|
time_segment2,
|
215 |
|
|
triple_sampling,
|
216 |
|
|
|
217 |
|
|
/* Error Warning Limit register */
|
218 |
|
|
error_warning_limit,
|
219 |
|
|
|
220 |
|
|
/* Rx Error Counter register */
|
221 |
|
|
we_rx_err_cnt,
|
222 |
|
|
|
223 |
|
|
/* Tx Error Counter register */
|
224 |
|
|
we_tx_err_cnt,
|
225 |
|
|
|
226 |
|
|
/* Clock Divider register */
|
227 |
|
|
extended_mode,
|
228 |
|
|
clkout,
|
229 |
|
|
|
230 |
|
|
|
231 |
|
|
/* This section is for BASIC and EXTENDED mode */
|
232 |
|
|
/* Acceptance code register */
|
233 |
|
|
acceptance_code_0,
|
234 |
|
|
|
235 |
|
|
/* Acceptance mask register */
|
236 |
|
|
acceptance_mask_0,
|
237 |
|
|
/* End: This section is for BASIC and EXTENDED mode */
|
238 |
|
|
|
239 |
|
|
/* This section is for EXTENDED mode */
|
240 |
|
|
/* Acceptance code register */
|
241 |
|
|
acceptance_code_1,
|
242 |
|
|
acceptance_code_2,
|
243 |
|
|
acceptance_code_3,
|
244 |
|
|
|
245 |
|
|
/* Acceptance mask register */
|
246 |
|
|
acceptance_mask_1,
|
247 |
|
|
acceptance_mask_2,
|
248 |
|
|
acceptance_mask_3,
|
249 |
|
|
/* End: This section is for EXTENDED mode */
|
250 |
|
|
|
251 |
|
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
252 |
|
|
tx_data_0,
|
253 |
|
|
tx_data_1,
|
254 |
|
|
tx_data_2,
|
255 |
|
|
tx_data_3,
|
256 |
|
|
tx_data_4,
|
257 |
|
|
tx_data_5,
|
258 |
|
|
tx_data_6,
|
259 |
|
|
tx_data_7,
|
260 |
|
|
tx_data_8,
|
261 |
|
|
tx_data_9,
|
262 |
|
|
tx_data_10,
|
263 |
|
|
tx_data_11,
|
264 |
|
|
tx_data_12
|
265 |
|
|
/* End: Tx data registers */
|
266 |
|
|
|
267 |
|
|
|
268 |
|
|
|
269 |
|
|
|
270 |
|
|
);
|
271 |
|
|
|
272 |
|
|
parameter Tp = 1;
|
273 |
|
|
|
274 |
|
|
input clk;
|
275 |
|
|
input rst;
|
276 |
|
|
input cs;
|
277 |
|
|
input we;
|
278 |
|
|
input [7:0] addr;
|
279 |
|
|
input [7:0] data_in;
|
280 |
|
|
|
281 |
|
|
output [7:0] data_out;
|
282 |
|
|
reg [7:0] data_out;
|
283 |
|
|
|
284 |
|
|
output irq;
|
285 |
|
|
|
286 |
|
|
input sample_point;
|
287 |
|
|
input transmitting;
|
288 |
|
|
input set_reset_mode;
|
289 |
|
|
input node_bus_off;
|
290 |
|
|
input error_status;
|
291 |
|
|
input [7:0] rx_err_cnt;
|
292 |
|
|
input [7:0] tx_err_cnt;
|
293 |
|
|
input transmit_status;
|
294 |
|
|
input receive_status;
|
295 |
|
|
input tx_successful;
|
296 |
|
|
input need_to_tx;
|
297 |
|
|
input overrun;
|
298 |
|
|
input info_empty;
|
299 |
|
|
input set_bus_error_irq;
|
300 |
|
|
input set_arbitration_lost_irq;
|
301 |
|
|
input [4:0] arbitration_lost_capture;
|
302 |
|
|
input node_error_passive;
|
303 |
|
|
input node_error_active;
|
304 |
|
|
input [6:0] rx_message_counter;
|
305 |
|
|
|
306 |
|
|
|
307 |
|
|
|
308 |
|
|
/* Mode register */
|
309 |
|
|
output reset_mode;
|
310 |
|
|
output listen_only_mode;
|
311 |
|
|
output acceptance_filter_mode;
|
312 |
|
|
output self_test_mode;
|
313 |
|
|
|
314 |
|
|
/* Command register */
|
315 |
|
|
output clear_data_overrun;
|
316 |
|
|
output release_buffer;
|
317 |
|
|
output abort_tx;
|
318 |
|
|
output tx_request;
|
319 |
|
|
output self_rx_request;
|
320 |
|
|
output single_shot_transmission;
|
321 |
104 |
tadejm |
input tx_state;
|
322 |
|
|
input tx_state_q;
|
323 |
66 |
mohor |
|
324 |
|
|
/* Arbitration Lost Capture Register */
|
325 |
|
|
output read_arbitration_lost_capture_reg;
|
326 |
|
|
|
327 |
|
|
/* Error Code Capture Register */
|
328 |
|
|
output read_error_code_capture_reg;
|
329 |
|
|
input [7:0] error_capture_code;
|
330 |
|
|
|
331 |
|
|
/* Bus Timing 0 register */
|
332 |
|
|
output [5:0] baud_r_presc;
|
333 |
|
|
output [1:0] sync_jump_width;
|
334 |
|
|
|
335 |
|
|
|
336 |
|
|
/* Bus Timing 1 register */
|
337 |
|
|
output [3:0] time_segment1;
|
338 |
|
|
output [2:0] time_segment2;
|
339 |
|
|
output triple_sampling;
|
340 |
|
|
|
341 |
|
|
/* Error Warning Limit register */
|
342 |
|
|
output [7:0] error_warning_limit;
|
343 |
|
|
|
344 |
|
|
/* Rx Error Counter register */
|
345 |
|
|
output we_rx_err_cnt;
|
346 |
|
|
|
347 |
|
|
/* Tx Error Counter register */
|
348 |
|
|
output we_tx_err_cnt;
|
349 |
|
|
|
350 |
|
|
/* Clock Divider register */
|
351 |
|
|
output extended_mode;
|
352 |
|
|
output clkout;
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
/* This section is for BASIC and EXTENDED mode */
|
356 |
|
|
/* Acceptance code register */
|
357 |
|
|
output [7:0] acceptance_code_0;
|
358 |
|
|
|
359 |
|
|
/* Acceptance mask register */
|
360 |
|
|
output [7:0] acceptance_mask_0;
|
361 |
|
|
|
362 |
|
|
/* End: This section is for BASIC and EXTENDED mode */
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
/* This section is for EXTENDED mode */
|
366 |
|
|
/* Acceptance code register */
|
367 |
|
|
output [7:0] acceptance_code_1;
|
368 |
|
|
output [7:0] acceptance_code_2;
|
369 |
|
|
output [7:0] acceptance_code_3;
|
370 |
|
|
|
371 |
|
|
/* Acceptance mask register */
|
372 |
|
|
output [7:0] acceptance_mask_1;
|
373 |
|
|
output [7:0] acceptance_mask_2;
|
374 |
|
|
output [7:0] acceptance_mask_3;
|
375 |
|
|
|
376 |
|
|
/* End: This section is for EXTENDED mode */
|
377 |
|
|
|
378 |
|
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
379 |
|
|
output [7:0] tx_data_0;
|
380 |
|
|
output [7:0] tx_data_1;
|
381 |
|
|
output [7:0] tx_data_2;
|
382 |
|
|
output [7:0] tx_data_3;
|
383 |
|
|
output [7:0] tx_data_4;
|
384 |
|
|
output [7:0] tx_data_5;
|
385 |
|
|
output [7:0] tx_data_6;
|
386 |
|
|
output [7:0] tx_data_7;
|
387 |
|
|
output [7:0] tx_data_8;
|
388 |
|
|
output [7:0] tx_data_9;
|
389 |
|
|
output [7:0] tx_data_10;
|
390 |
|
|
output [7:0] tx_data_11;
|
391 |
|
|
output [7:0] tx_data_12;
|
392 |
|
|
/* End: Tx data registers */
|
393 |
|
|
|
394 |
|
|
|
395 |
|
|
reg tx_successful_q;
|
396 |
|
|
reg overrun_q;
|
397 |
|
|
reg overrun_status;
|
398 |
|
|
reg transmission_complete;
|
399 |
|
|
reg transmit_buffer_status_q;
|
400 |
|
|
reg receive_buffer_status;
|
401 |
|
|
reg error_status_q;
|
402 |
|
|
reg node_bus_off_q;
|
403 |
|
|
reg node_error_passive_q;
|
404 |
|
|
reg transmit_buffer_status;
|
405 |
|
|
reg single_shot_transmission;
|
406 |
104 |
tadejm |
reg self_rx_request;
|
407 |
66 |
mohor |
|
408 |
|
|
|
409 |
|
|
// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
|
410 |
|
|
wire data_overrun_irq_en;
|
411 |
|
|
wire error_warning_irq_en;
|
412 |
|
|
wire transmit_irq_en;
|
413 |
|
|
wire receive_irq_en;
|
414 |
|
|
|
415 |
|
|
wire [7:0] irq_reg;
|
416 |
|
|
|
417 |
|
|
wire we_mode = cs & we & (addr == 8'd0);
|
418 |
|
|
wire we_command = cs & we & (addr == 8'd1);
|
419 |
|
|
wire we_bus_timing_0 = cs & we & (addr == 8'd6) & reset_mode;
|
420 |
|
|
wire we_bus_timing_1 = cs & we & (addr == 8'd7) & reset_mode;
|
421 |
|
|
wire we_clock_divider_low = cs & we & (addr == 8'd31);
|
422 |
|
|
wire we_clock_divider_hi = we_clock_divider_low & reset_mode;
|
423 |
|
|
|
424 |
|
|
wire read = cs & (~we);
|
425 |
|
|
wire read_irq_reg = read & (addr == 8'd3);
|
426 |
|
|
assign read_arbitration_lost_capture_reg = read & extended_mode & (addr == 8'd11);
|
427 |
|
|
assign read_error_code_capture_reg = read & extended_mode & (addr == 8'd12);
|
428 |
|
|
|
429 |
|
|
/* This section is for BASIC and EXTENDED mode */
|
430 |
|
|
wire we_acceptance_code_0 = cs & we & reset_mode & ((~extended_mode) & (addr == 8'd4) | extended_mode & (addr == 8'd16));
|
431 |
|
|
wire we_acceptance_mask_0 = cs & we & reset_mode & ((~extended_mode) & (addr == 8'd5) | extended_mode & (addr == 8'd20));
|
432 |
|
|
wire we_tx_data_0 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd10) | extended_mode & (addr == 8'd16)) & transmit_buffer_status;
|
433 |
|
|
wire we_tx_data_1 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd11) | extended_mode & (addr == 8'd17)) & transmit_buffer_status;
|
434 |
|
|
wire we_tx_data_2 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd12) | extended_mode & (addr == 8'd18)) & transmit_buffer_status;
|
435 |
|
|
wire we_tx_data_3 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd13) | extended_mode & (addr == 8'd19)) & transmit_buffer_status;
|
436 |
|
|
wire we_tx_data_4 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd14) | extended_mode & (addr == 8'd20)) & transmit_buffer_status;
|
437 |
|
|
wire we_tx_data_5 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd15) | extended_mode & (addr == 8'd21)) & transmit_buffer_status;
|
438 |
|
|
wire we_tx_data_6 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd16) | extended_mode & (addr == 8'd22)) & transmit_buffer_status;
|
439 |
|
|
wire we_tx_data_7 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd17) | extended_mode & (addr == 8'd23)) & transmit_buffer_status;
|
440 |
|
|
wire we_tx_data_8 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd18) | extended_mode & (addr == 8'd24)) & transmit_buffer_status;
|
441 |
|
|
wire we_tx_data_9 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd19) | extended_mode & (addr == 8'd25)) & transmit_buffer_status;
|
442 |
|
|
wire we_tx_data_10 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd26)) & transmit_buffer_status;
|
443 |
|
|
wire we_tx_data_11 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd27)) & transmit_buffer_status;
|
444 |
|
|
wire we_tx_data_12 = cs & we & (~reset_mode) & ( extended_mode & (addr == 8'd28)) & transmit_buffer_status;
|
445 |
|
|
/* End: This section is for BASIC and EXTENDED mode */
|
446 |
|
|
|
447 |
|
|
|
448 |
|
|
/* This section is for EXTENDED mode */
|
449 |
|
|
wire we_interrupt_enable = cs & we & (addr == 8'd4) & extended_mode;
|
450 |
|
|
wire we_error_warning_limit = cs & we & (addr == 8'd13) & reset_mode & extended_mode;
|
451 |
|
|
assign we_rx_err_cnt = cs & we & (addr == 8'd14) & reset_mode & extended_mode;
|
452 |
|
|
assign we_tx_err_cnt = cs & we & (addr == 8'd15) & reset_mode & extended_mode;
|
453 |
|
|
wire we_acceptance_code_1 = cs & we & (addr == 8'd17) & reset_mode & extended_mode;
|
454 |
|
|
wire we_acceptance_code_2 = cs & we & (addr == 8'd18) & reset_mode & extended_mode;
|
455 |
|
|
wire we_acceptance_code_3 = cs & we & (addr == 8'd19) & reset_mode & extended_mode;
|
456 |
|
|
wire we_acceptance_mask_1 = cs & we & (addr == 8'd21) & reset_mode & extended_mode;
|
457 |
|
|
wire we_acceptance_mask_2 = cs & we & (addr == 8'd22) & reset_mode & extended_mode;
|
458 |
|
|
wire we_acceptance_mask_3 = cs & we & (addr == 8'd23) & reset_mode & extended_mode;
|
459 |
|
|
/* End: This section is for EXTENDED mode */
|
460 |
|
|
|
461 |
|
|
|
462 |
|
|
|
463 |
|
|
always @ (posedge clk)
|
464 |
|
|
begin
|
465 |
|
|
tx_successful_q <=#Tp tx_successful;
|
466 |
|
|
overrun_q <=#Tp overrun;
|
467 |
|
|
transmit_buffer_status_q <=#Tp transmit_buffer_status;
|
468 |
|
|
error_status_q <=#Tp error_status;
|
469 |
|
|
node_bus_off_q <=#Tp node_bus_off;
|
470 |
|
|
node_error_passive_q <=#Tp node_error_passive;
|
471 |
|
|
end
|
472 |
|
|
|
473 |
|
|
|
474 |
|
|
|
475 |
|
|
/* Mode register */
|
476 |
|
|
wire [0:0] mode;
|
477 |
|
|
wire [4:1] mode_basic;
|
478 |
|
|
wire [3:1] mode_ext;
|
479 |
|
|
wire receive_irq_en_basic;
|
480 |
|
|
wire transmit_irq_en_basic;
|
481 |
|
|
wire error_irq_en_basic;
|
482 |
|
|
wire overrun_irq_en_basic;
|
483 |
|
|
|
484 |
|
|
can_register_asyn_syn #(1, 1'h1) MODE_REG0
|
485 |
|
|
( .data_in(data_in[0]),
|
486 |
|
|
.data_out(mode[0]),
|
487 |
|
|
.we(we_mode),
|
488 |
|
|
.clk(clk),
|
489 |
|
|
.rst(rst),
|
490 |
|
|
.rst_sync(set_reset_mode)
|
491 |
|
|
);
|
492 |
|
|
|
493 |
|
|
can_register_asyn #(4, 0) MODE_REG_BASIC
|
494 |
|
|
( .data_in(data_in[4:1]),
|
495 |
|
|
.data_out(mode_basic[4:1]),
|
496 |
|
|
.we(we_mode),
|
497 |
|
|
.clk(clk),
|
498 |
|
|
.rst(rst)
|
499 |
|
|
);
|
500 |
|
|
|
501 |
|
|
can_register_asyn #(3, 0) MODE_REG_EXT
|
502 |
|
|
( .data_in(data_in[3:1]),
|
503 |
|
|
.data_out(mode_ext[3:1]),
|
504 |
|
|
.we(we_mode & reset_mode),
|
505 |
|
|
.clk(clk),
|
506 |
|
|
.rst(rst)
|
507 |
|
|
);
|
508 |
|
|
|
509 |
|
|
assign reset_mode = mode[0];
|
510 |
69 |
mohor |
assign listen_only_mode = extended_mode & mode_ext[1];
|
511 |
|
|
assign self_test_mode = extended_mode & mode_ext[2];
|
512 |
|
|
assign acceptance_filter_mode = extended_mode & mode_ext[3];
|
513 |
66 |
mohor |
|
514 |
|
|
assign receive_irq_en_basic = mode_basic[1];
|
515 |
|
|
assign transmit_irq_en_basic = mode_basic[2];
|
516 |
|
|
assign error_irq_en_basic = mode_basic[3];
|
517 |
|
|
assign overrun_irq_en_basic = mode_basic[4];
|
518 |
|
|
/* End Mode register */
|
519 |
|
|
|
520 |
|
|
|
521 |
|
|
/* Command register */
|
522 |
|
|
wire [4:0] command;
|
523 |
|
|
can_register_asyn_syn #(1, 1'h0) COMMAND_REG0
|
524 |
|
|
( .data_in(data_in[0]),
|
525 |
|
|
.data_out(command[0]),
|
526 |
|
|
.we(we_command),
|
527 |
|
|
.clk(clk),
|
528 |
|
|
.rst(rst),
|
529 |
104 |
tadejm |
.rst_sync(command[0] & sample_point)
|
530 |
66 |
mohor |
);
|
531 |
|
|
|
532 |
|
|
can_register_asyn_syn #(1, 1'h0) COMMAND_REG1
|
533 |
|
|
( .data_in(data_in[1]),
|
534 |
|
|
.data_out(command[1]),
|
535 |
|
|
.we(we_command),
|
536 |
|
|
.clk(clk),
|
537 |
|
|
.rst(rst),
|
538 |
104 |
tadejm |
.rst_sync(sample_point & (tx_request | (abort_tx & ~transmitting)))
|
539 |
66 |
mohor |
);
|
540 |
|
|
|
541 |
|
|
can_register_asyn_syn #(2, 2'h0) COMMAND_REG
|
542 |
|
|
( .data_in(data_in[3:2]),
|
543 |
|
|
.data_out(command[3:2]),
|
544 |
|
|
.we(we_command),
|
545 |
|
|
.clk(clk),
|
546 |
|
|
.rst(rst),
|
547 |
|
|
.rst_sync(|command[3:2])
|
548 |
|
|
);
|
549 |
|
|
|
550 |
|
|
can_register_asyn_syn #(1, 1'h0) COMMAND_REG4
|
551 |
|
|
( .data_in(data_in[4]),
|
552 |
|
|
.data_out(command[4]),
|
553 |
|
|
.we(we_command),
|
554 |
|
|
.clk(clk),
|
555 |
|
|
.rst(rst),
|
556 |
104 |
tadejm |
.rst_sync(command[4] & sample_point)
|
557 |
66 |
mohor |
);
|
558 |
|
|
|
559 |
104 |
tadejm |
|
560 |
|
|
always @ (posedge clk or posedge rst)
|
561 |
|
|
begin
|
562 |
|
|
if (rst)
|
563 |
|
|
self_rx_request <= 1'b0;
|
564 |
|
|
else if (command[4] & (~command[0]))
|
565 |
|
|
self_rx_request <=#Tp 1'b1;
|
566 |
|
|
else if ((~tx_state) & tx_state_q)
|
567 |
|
|
self_rx_request <=#Tp 1'b0;
|
568 |
|
|
end
|
569 |
|
|
|
570 |
|
|
|
571 |
66 |
mohor |
assign clear_data_overrun = command[3];
|
572 |
|
|
assign release_buffer = command[2];
|
573 |
|
|
assign tx_request = command[0] | command[4];
|
574 |
104 |
tadejm |
assign abort_tx = command[1] & (~tx_request);
|
575 |
66 |
mohor |
|
576 |
|
|
|
577 |
|
|
always @ (posedge clk or posedge rst)
|
578 |
|
|
begin
|
579 |
|
|
if (rst)
|
580 |
|
|
single_shot_transmission <= 1'b0;
|
581 |
104 |
tadejm |
else if (tx_request & command[1] & sample_point)
|
582 |
66 |
mohor |
single_shot_transmission <=#Tp 1'b1;
|
583 |
104 |
tadejm |
else if ((~tx_state) & tx_state_q)
|
584 |
66 |
mohor |
single_shot_transmission <=#Tp 1'b0;
|
585 |
|
|
end
|
586 |
|
|
|
587 |
|
|
|
588 |
|
|
|
589 |
|
|
/* End Command register */
|
590 |
|
|
|
591 |
|
|
|
592 |
|
|
/* Status register */
|
593 |
|
|
|
594 |
|
|
wire [7:0] status;
|
595 |
|
|
|
596 |
|
|
assign status[7] = node_bus_off;
|
597 |
|
|
assign status[6] = error_status;
|
598 |
|
|
assign status[5] = transmit_status;
|
599 |
|
|
assign status[4] = receive_status;
|
600 |
|
|
assign status[3] = transmission_complete;
|
601 |
|
|
assign status[2] = transmit_buffer_status;
|
602 |
|
|
assign status[1] = overrun_status;
|
603 |
|
|
assign status[0] = receive_buffer_status;
|
604 |
|
|
|
605 |
|
|
|
606 |
|
|
|
607 |
|
|
always @ (posedge clk or posedge rst)
|
608 |
|
|
begin
|
609 |
|
|
if (rst)
|
610 |
|
|
transmission_complete <= 1'b1;
|
611 |
|
|
else if (tx_successful & (~tx_successful_q) | abort_tx)
|
612 |
|
|
transmission_complete <=#Tp 1'b1;
|
613 |
|
|
else if (tx_request)
|
614 |
|
|
transmission_complete <=#Tp 1'b0;
|
615 |
|
|
end
|
616 |
|
|
|
617 |
|
|
|
618 |
|
|
always @ (posedge clk or posedge rst)
|
619 |
|
|
begin
|
620 |
|
|
if (rst)
|
621 |
|
|
transmit_buffer_status <= 1'b1;
|
622 |
|
|
else if (tx_request)
|
623 |
|
|
transmit_buffer_status <=#Tp 1'b0;
|
624 |
|
|
else if (~need_to_tx)
|
625 |
|
|
transmit_buffer_status <=#Tp 1'b1;
|
626 |
|
|
end
|
627 |
|
|
|
628 |
|
|
|
629 |
|
|
always @ (posedge clk or posedge rst)
|
630 |
|
|
begin
|
631 |
|
|
if (rst)
|
632 |
|
|
overrun_status <= 1'b0;
|
633 |
|
|
else if (overrun & (~overrun_q))
|
634 |
|
|
overrun_status <=#Tp 1'b1;
|
635 |
|
|
else if (clear_data_overrun)
|
636 |
|
|
overrun_status <=#Tp 1'b0;
|
637 |
|
|
end
|
638 |
|
|
|
639 |
|
|
|
640 |
|
|
always @ (posedge clk or posedge rst)
|
641 |
|
|
begin
|
642 |
|
|
if (rst)
|
643 |
|
|
receive_buffer_status <= 1'b0;
|
644 |
|
|
else if (release_buffer)
|
645 |
|
|
receive_buffer_status <=#Tp 1'b0;
|
646 |
|
|
else if (~info_empty)
|
647 |
|
|
receive_buffer_status <=#Tp 1'b1;
|
648 |
|
|
end
|
649 |
|
|
|
650 |
|
|
/* End Status register */
|
651 |
|
|
|
652 |
|
|
|
653 |
|
|
/* Interrupt Enable register (extended mode) */
|
654 |
|
|
wire [7:0] irq_en_ext;
|
655 |
|
|
wire bus_error_irq_en;
|
656 |
|
|
wire arbitration_lost_irq_en;
|
657 |
|
|
wire error_passive_irq_en;
|
658 |
|
|
wire data_overrun_irq_en_ext;
|
659 |
|
|
wire error_warning_irq_en_ext;
|
660 |
|
|
wire transmit_irq_en_ext;
|
661 |
|
|
wire receive_irq_en_ext;
|
662 |
|
|
|
663 |
|
|
can_register #(8) IRQ_EN_REG
|
664 |
|
|
( .data_in(data_in),
|
665 |
|
|
.data_out(irq_en_ext),
|
666 |
|
|
.we(we_interrupt_enable),
|
667 |
|
|
.clk(clk)
|
668 |
|
|
);
|
669 |
|
|
|
670 |
|
|
|
671 |
|
|
assign bus_error_irq_en = irq_en_ext[7];
|
672 |
|
|
assign arbitration_lost_irq_en = irq_en_ext[6];
|
673 |
|
|
assign error_passive_irq_en = irq_en_ext[5];
|
674 |
|
|
assign data_overrun_irq_en_ext = irq_en_ext[3];
|
675 |
|
|
assign error_warning_irq_en_ext = irq_en_ext[2];
|
676 |
|
|
assign transmit_irq_en_ext = irq_en_ext[1];
|
677 |
|
|
assign receive_irq_en_ext = irq_en_ext[0];
|
678 |
|
|
/* End Bus Timing 0 register */
|
679 |
|
|
|
680 |
|
|
|
681 |
|
|
/* Bus Timing 0 register */
|
682 |
|
|
wire [7:0] bus_timing_0;
|
683 |
|
|
can_register #(8) BUS_TIMING_0_REG
|
684 |
|
|
( .data_in(data_in),
|
685 |
|
|
.data_out(bus_timing_0),
|
686 |
|
|
.we(we_bus_timing_0),
|
687 |
|
|
.clk(clk)
|
688 |
|
|
);
|
689 |
|
|
|
690 |
|
|
assign baud_r_presc = bus_timing_0[5:0];
|
691 |
|
|
assign sync_jump_width = bus_timing_0[7:6];
|
692 |
|
|
/* End Bus Timing 0 register */
|
693 |
|
|
|
694 |
|
|
|
695 |
|
|
/* Bus Timing 1 register */
|
696 |
|
|
wire [7:0] bus_timing_1;
|
697 |
|
|
can_register #(8) BUS_TIMING_1_REG
|
698 |
|
|
( .data_in(data_in),
|
699 |
|
|
.data_out(bus_timing_1),
|
700 |
|
|
.we(we_bus_timing_1),
|
701 |
|
|
.clk(clk)
|
702 |
|
|
);
|
703 |
|
|
|
704 |
|
|
assign time_segment1 = bus_timing_1[3:0];
|
705 |
|
|
assign time_segment2 = bus_timing_1[6:4];
|
706 |
|
|
assign triple_sampling = bus_timing_1[7];
|
707 |
|
|
/* End Bus Timing 1 register */
|
708 |
|
|
|
709 |
|
|
|
710 |
|
|
/* Error Warning Limit register */
|
711 |
|
|
can_register_asyn #(8, 96) ERROR_WARNING_REG
|
712 |
|
|
( .data_in(data_in),
|
713 |
|
|
.data_out(error_warning_limit),
|
714 |
|
|
.we(we_error_warning_limit),
|
715 |
|
|
.clk(clk),
|
716 |
|
|
.rst(rst)
|
717 |
|
|
);
|
718 |
|
|
/* End Error Warning Limit register */
|
719 |
|
|
|
720 |
|
|
|
721 |
|
|
|
722 |
|
|
/* Clock Divider register */
|
723 |
|
|
wire [7:0] clock_divider;
|
724 |
|
|
wire clock_off;
|
725 |
|
|
wire [2:0] cd;
|
726 |
|
|
reg [2:0] clkout_div;
|
727 |
|
|
reg [2:0] clkout_cnt;
|
728 |
|
|
reg clkout_tmp;
|
729 |
|
|
//reg clkout;
|
730 |
|
|
|
731 |
92 |
mohor |
can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_7
|
732 |
66 |
mohor |
( .data_in(data_in[7]),
|
733 |
|
|
.data_out(clock_divider[7]),
|
734 |
|
|
.we(we_clock_divider_hi),
|
735 |
92 |
mohor |
.clk(clk),
|
736 |
|
|
.rst(rst)
|
737 |
66 |
mohor |
);
|
738 |
|
|
|
739 |
|
|
assign clock_divider[6:4] = 3'h0;
|
740 |
|
|
|
741 |
92 |
mohor |
can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_3
|
742 |
66 |
mohor |
( .data_in(data_in[3]),
|
743 |
|
|
.data_out(clock_divider[3]),
|
744 |
|
|
.we(we_clock_divider_hi),
|
745 |
92 |
mohor |
.clk(clk),
|
746 |
|
|
.rst(rst)
|
747 |
66 |
mohor |
);
|
748 |
|
|
|
749 |
92 |
mohor |
can_register_asyn #(3, 0) CLOCK_DIVIDER_REG_LOW
|
750 |
66 |
mohor |
( .data_in(data_in[2:0]),
|
751 |
|
|
.data_out(clock_divider[2:0]),
|
752 |
|
|
.we(we_clock_divider_low),
|
753 |
92 |
mohor |
.clk(clk),
|
754 |
|
|
.rst(rst)
|
755 |
66 |
mohor |
);
|
756 |
|
|
|
757 |
|
|
assign extended_mode = clock_divider[7];
|
758 |
|
|
assign clock_off = clock_divider[3];
|
759 |
|
|
assign cd[2:0] = clock_divider[2:0];
|
760 |
|
|
|
761 |
|
|
|
762 |
|
|
|
763 |
|
|
always @ (cd)
|
764 |
|
|
begin
|
765 |
93 |
mohor |
case (cd) /* synthesis full_case parallel_case */
|
766 |
111 |
mohor |
3'b000 : clkout_div = 3'd0;
|
767 |
|
|
3'b001 : clkout_div = 3'd1;
|
768 |
|
|
3'b010 : clkout_div = 3'd2;
|
769 |
|
|
3'b011 : clkout_div = 3'd3;
|
770 |
|
|
3'b100 : clkout_div = 3'd4;
|
771 |
|
|
3'b101 : clkout_div = 3'd5;
|
772 |
|
|
3'b110 : clkout_div = 3'd6;
|
773 |
|
|
3'b111 : clkout_div = 3'd0;
|
774 |
66 |
mohor |
endcase
|
775 |
|
|
end
|
776 |
|
|
|
777 |
|
|
|
778 |
|
|
|
779 |
|
|
always @ (posedge clk or posedge rst)
|
780 |
|
|
begin
|
781 |
|
|
if (rst)
|
782 |
|
|
clkout_cnt <= 3'h0;
|
783 |
|
|
else if (clkout_cnt == clkout_div)
|
784 |
|
|
clkout_cnt <=#Tp 3'h0;
|
785 |
|
|
else
|
786 |
|
|
clkout_cnt <= clkout_cnt + 1'b1;
|
787 |
|
|
end
|
788 |
|
|
|
789 |
|
|
|
790 |
|
|
|
791 |
|
|
always @ (posedge clk or posedge rst)
|
792 |
|
|
begin
|
793 |
|
|
if (rst)
|
794 |
|
|
clkout_tmp <= 1'b0;
|
795 |
|
|
else if (clkout_cnt == clkout_div)
|
796 |
|
|
clkout_tmp <=#Tp ~clkout_tmp;
|
797 |
|
|
end
|
798 |
|
|
|
799 |
|
|
|
800 |
|
|
/*
|
801 |
|
|
//always @ (cd or clk or clkout_tmp or clock_off)
|
802 |
|
|
always @ (cd or clkout_tmp or clock_off)
|
803 |
|
|
begin
|
804 |
|
|
if (clock_off)
|
805 |
|
|
clkout <=#Tp 1'b1;
|
806 |
|
|
// else if (&cd)
|
807 |
|
|
// clkout <=#Tp clk;
|
808 |
|
|
else
|
809 |
|
|
clkout <=#Tp clkout_tmp;
|
810 |
|
|
end
|
811 |
|
|
*/
|
812 |
|
|
assign clkout = clock_off ? 1'b1 : ((&cd)? clk : clkout_tmp);
|
813 |
|
|
|
814 |
|
|
|
815 |
|
|
|
816 |
|
|
/* End Clock Divider register */
|
817 |
|
|
|
818 |
|
|
|
819 |
|
|
|
820 |
|
|
|
821 |
|
|
/* This section is for BASIC and EXTENDED mode */
|
822 |
|
|
|
823 |
|
|
/* Acceptance code register */
|
824 |
|
|
can_register #(8) ACCEPTANCE_CODE_REG0
|
825 |
|
|
( .data_in(data_in),
|
826 |
|
|
.data_out(acceptance_code_0),
|
827 |
|
|
.we(we_acceptance_code_0),
|
828 |
|
|
.clk(clk)
|
829 |
|
|
);
|
830 |
|
|
/* End: Acceptance code register */
|
831 |
|
|
|
832 |
|
|
|
833 |
|
|
/* Acceptance mask register */
|
834 |
|
|
can_register #(8) ACCEPTANCE_MASK_REG0
|
835 |
|
|
( .data_in(data_in),
|
836 |
|
|
.data_out(acceptance_mask_0),
|
837 |
|
|
.we(we_acceptance_mask_0),
|
838 |
|
|
.clk(clk)
|
839 |
|
|
);
|
840 |
|
|
/* End: Acceptance mask register */
|
841 |
|
|
/* End: This section is for BASIC and EXTENDED mode */
|
842 |
|
|
|
843 |
|
|
|
844 |
|
|
/* Tx data 0 register. */
|
845 |
|
|
can_register #(8) TX_DATA_REG0
|
846 |
|
|
( .data_in(data_in),
|
847 |
|
|
.data_out(tx_data_0),
|
848 |
|
|
.we(we_tx_data_0),
|
849 |
|
|
.clk(clk)
|
850 |
|
|
);
|
851 |
|
|
/* End: Tx data 0 register. */
|
852 |
|
|
|
853 |
|
|
|
854 |
|
|
/* Tx data 1 register. */
|
855 |
|
|
can_register #(8) TX_DATA_REG1
|
856 |
|
|
( .data_in(data_in),
|
857 |
|
|
.data_out(tx_data_1),
|
858 |
|
|
.we(we_tx_data_1),
|
859 |
|
|
.clk(clk)
|
860 |
|
|
);
|
861 |
|
|
/* End: Tx data 1 register. */
|
862 |
|
|
|
863 |
|
|
|
864 |
|
|
/* Tx data 2 register. */
|
865 |
|
|
can_register #(8) TX_DATA_REG2
|
866 |
|
|
( .data_in(data_in),
|
867 |
|
|
.data_out(tx_data_2),
|
868 |
|
|
.we(we_tx_data_2),
|
869 |
|
|
.clk(clk)
|
870 |
|
|
);
|
871 |
|
|
/* End: Tx data 2 register. */
|
872 |
|
|
|
873 |
|
|
|
874 |
|
|
/* Tx data 3 register. */
|
875 |
|
|
can_register #(8) TX_DATA_REG3
|
876 |
|
|
( .data_in(data_in),
|
877 |
|
|
.data_out(tx_data_3),
|
878 |
|
|
.we(we_tx_data_3),
|
879 |
|
|
.clk(clk)
|
880 |
|
|
);
|
881 |
|
|
/* End: Tx data 3 register. */
|
882 |
|
|
|
883 |
|
|
|
884 |
|
|
/* Tx data 4 register. */
|
885 |
|
|
can_register #(8) TX_DATA_REG4
|
886 |
|
|
( .data_in(data_in),
|
887 |
|
|
.data_out(tx_data_4),
|
888 |
|
|
.we(we_tx_data_4),
|
889 |
|
|
.clk(clk)
|
890 |
|
|
);
|
891 |
|
|
/* End: Tx data 4 register. */
|
892 |
|
|
|
893 |
|
|
|
894 |
|
|
/* Tx data 5 register. */
|
895 |
|
|
can_register #(8) TX_DATA_REG5
|
896 |
|
|
( .data_in(data_in),
|
897 |
|
|
.data_out(tx_data_5),
|
898 |
|
|
.we(we_tx_data_5),
|
899 |
|
|
.clk(clk)
|
900 |
|
|
);
|
901 |
|
|
/* End: Tx data 5 register. */
|
902 |
|
|
|
903 |
|
|
|
904 |
|
|
/* Tx data 6 register. */
|
905 |
|
|
can_register #(8) TX_DATA_REG6
|
906 |
|
|
( .data_in(data_in),
|
907 |
|
|
.data_out(tx_data_6),
|
908 |
|
|
.we(we_tx_data_6),
|
909 |
|
|
.clk(clk)
|
910 |
|
|
);
|
911 |
|
|
/* End: Tx data 6 register. */
|
912 |
|
|
|
913 |
|
|
|
914 |
|
|
/* Tx data 7 register. */
|
915 |
|
|
can_register #(8) TX_DATA_REG7
|
916 |
|
|
( .data_in(data_in),
|
917 |
|
|
.data_out(tx_data_7),
|
918 |
|
|
.we(we_tx_data_7),
|
919 |
|
|
.clk(clk)
|
920 |
|
|
);
|
921 |
|
|
/* End: Tx data 7 register. */
|
922 |
|
|
|
923 |
|
|
|
924 |
|
|
/* Tx data 8 register. */
|
925 |
|
|
can_register #(8) TX_DATA_REG8
|
926 |
|
|
( .data_in(data_in),
|
927 |
|
|
.data_out(tx_data_8),
|
928 |
|
|
.we(we_tx_data_8),
|
929 |
|
|
.clk(clk)
|
930 |
|
|
);
|
931 |
|
|
/* End: Tx data 8 register. */
|
932 |
|
|
|
933 |
|
|
|
934 |
|
|
/* Tx data 9 register. */
|
935 |
|
|
can_register #(8) TX_DATA_REG9
|
936 |
|
|
( .data_in(data_in),
|
937 |
|
|
.data_out(tx_data_9),
|
938 |
|
|
.we(we_tx_data_9),
|
939 |
|
|
.clk(clk)
|
940 |
|
|
);
|
941 |
|
|
/* End: Tx data 9 register. */
|
942 |
|
|
|
943 |
|
|
|
944 |
|
|
/* Tx data 10 register. */
|
945 |
|
|
can_register #(8) TX_DATA_REG10
|
946 |
|
|
( .data_in(data_in),
|
947 |
|
|
.data_out(tx_data_10),
|
948 |
|
|
.we(we_tx_data_10),
|
949 |
|
|
.clk(clk)
|
950 |
|
|
);
|
951 |
|
|
/* End: Tx data 10 register. */
|
952 |
|
|
|
953 |
|
|
|
954 |
|
|
/* Tx data 11 register. */
|
955 |
|
|
can_register #(8) TX_DATA_REG11
|
956 |
|
|
( .data_in(data_in),
|
957 |
|
|
.data_out(tx_data_11),
|
958 |
|
|
.we(we_tx_data_11),
|
959 |
|
|
.clk(clk)
|
960 |
|
|
);
|
961 |
|
|
/* End: Tx data 11 register. */
|
962 |
|
|
|
963 |
|
|
|
964 |
|
|
/* Tx data 12 register. */
|
965 |
|
|
can_register #(8) TX_DATA_REG12
|
966 |
|
|
( .data_in(data_in),
|
967 |
|
|
.data_out(tx_data_12),
|
968 |
|
|
.we(we_tx_data_12),
|
969 |
|
|
.clk(clk)
|
970 |
|
|
);
|
971 |
|
|
/* End: Tx data 12 register. */
|
972 |
|
|
|
973 |
|
|
|
974 |
|
|
|
975 |
|
|
|
976 |
|
|
|
977 |
|
|
/* This section is for EXTENDED mode */
|
978 |
|
|
|
979 |
|
|
/* Acceptance code register 1 */
|
980 |
|
|
can_register #(8) ACCEPTANCE_CODE_REG1
|
981 |
|
|
( .data_in(data_in),
|
982 |
|
|
.data_out(acceptance_code_1),
|
983 |
|
|
.we(we_acceptance_code_1),
|
984 |
|
|
.clk(clk)
|
985 |
|
|
);
|
986 |
|
|
/* End: Acceptance code register */
|
987 |
|
|
|
988 |
|
|
|
989 |
|
|
/* Acceptance code register 2 */
|
990 |
|
|
can_register #(8) ACCEPTANCE_CODE_REG2
|
991 |
|
|
( .data_in(data_in),
|
992 |
|
|
.data_out(acceptance_code_2),
|
993 |
|
|
.we(we_acceptance_code_2),
|
994 |
|
|
.clk(clk)
|
995 |
|
|
);
|
996 |
|
|
/* End: Acceptance code register */
|
997 |
|
|
|
998 |
|
|
|
999 |
|
|
/* Acceptance code register 3 */
|
1000 |
|
|
can_register #(8) ACCEPTANCE_CODE_REG3
|
1001 |
|
|
( .data_in(data_in),
|
1002 |
|
|
.data_out(acceptance_code_3),
|
1003 |
|
|
.we(we_acceptance_code_3),
|
1004 |
|
|
.clk(clk)
|
1005 |
|
|
);
|
1006 |
|
|
/* End: Acceptance code register */
|
1007 |
|
|
|
1008 |
|
|
|
1009 |
|
|
/* Acceptance mask register 1 */
|
1010 |
|
|
can_register #(8) ACCEPTANCE_MASK_REG1
|
1011 |
|
|
( .data_in(data_in),
|
1012 |
|
|
.data_out(acceptance_mask_1),
|
1013 |
|
|
.we(we_acceptance_mask_1),
|
1014 |
|
|
.clk(clk)
|
1015 |
|
|
);
|
1016 |
|
|
/* End: Acceptance code register */
|
1017 |
|
|
|
1018 |
|
|
|
1019 |
|
|
/* Acceptance mask register 2 */
|
1020 |
|
|
can_register #(8) ACCEPTANCE_MASK_REG2
|
1021 |
|
|
( .data_in(data_in),
|
1022 |
|
|
.data_out(acceptance_mask_2),
|
1023 |
|
|
.we(we_acceptance_mask_2),
|
1024 |
|
|
.clk(clk)
|
1025 |
|
|
);
|
1026 |
|
|
/* End: Acceptance code register */
|
1027 |
|
|
|
1028 |
|
|
|
1029 |
|
|
/* Acceptance mask register 3 */
|
1030 |
|
|
can_register #(8) ACCEPTANCE_MASK_REG3
|
1031 |
|
|
( .data_in(data_in),
|
1032 |
|
|
.data_out(acceptance_mask_3),
|
1033 |
|
|
.we(we_acceptance_mask_3),
|
1034 |
|
|
.clk(clk)
|
1035 |
|
|
);
|
1036 |
|
|
/* End: Acceptance code register */
|
1037 |
|
|
|
1038 |
|
|
|
1039 |
|
|
/* End: This section is for EXTENDED mode */
|
1040 |
|
|
|
1041 |
|
|
|
1042 |
|
|
|
1043 |
|
|
|
1044 |
|
|
// Reading data from registers
|
1045 |
111 |
mohor |
always @ ( addr or extended_mode or mode or bus_timing_0 or bus_timing_1 or clock_divider or
|
1046 |
66 |
mohor |
acceptance_code_0 or acceptance_code_1 or acceptance_code_2 or acceptance_code_3 or
|
1047 |
|
|
acceptance_mask_0 or acceptance_mask_1 or acceptance_mask_2 or acceptance_mask_3 or
|
1048 |
|
|
reset_mode or tx_data_0 or tx_data_1 or tx_data_2 or tx_data_3 or tx_data_4 or
|
1049 |
|
|
tx_data_5 or tx_data_6 or tx_data_7 or tx_data_8 or tx_data_9 or status or
|
1050 |
|
|
error_warning_limit or rx_err_cnt or tx_err_cnt or irq_en_ext or irq_reg or mode_ext or
|
1051 |
|
|
arbitration_lost_capture or rx_message_counter or mode_basic or error_capture_code
|
1052 |
|
|
)
|
1053 |
|
|
begin
|
1054 |
111 |
mohor |
case({extended_mode, addr[4:0]}) /* synthesis parallel_case */
|
1055 |
|
|
{1'h1, 5'd00} : data_out = {4'b0000, mode_ext[3:1], mode[0]}; // extended mode
|
1056 |
|
|
{1'h1, 5'd01} : data_out = 8'h0; // extended mode
|
1057 |
|
|
{1'h1, 5'd02} : data_out = status; // extended mode
|
1058 |
|
|
{1'h1, 5'd03} : data_out = irq_reg; // extended mode
|
1059 |
|
|
{1'h1, 5'd04} : data_out = irq_en_ext; // extended mode
|
1060 |
|
|
{1'h1, 5'd06} : data_out = bus_timing_0; // extended mode
|
1061 |
|
|
{1'h1, 5'd07} : data_out = bus_timing_1; // extended mode
|
1062 |
|
|
{1'h1, 5'd11} : data_out = {3'h0, arbitration_lost_capture[4:0]}; // extended mode
|
1063 |
|
|
{1'h1, 5'd12} : data_out = error_capture_code; // extended mode
|
1064 |
|
|
{1'h1, 5'd13} : data_out = error_warning_limit; // extended mode
|
1065 |
|
|
{1'h1, 5'd14} : data_out = rx_err_cnt; // extended mode
|
1066 |
|
|
{1'h1, 5'd15} : data_out = tx_err_cnt; // extended mode
|
1067 |
|
|
{1'h1, 5'd16} : data_out = acceptance_code_0; // extended mode
|
1068 |
|
|
{1'h1, 5'd17} : data_out = acceptance_code_1; // extended mode
|
1069 |
|
|
{1'h1, 5'd18} : data_out = acceptance_code_2; // extended mode
|
1070 |
|
|
{1'h1, 5'd19} : data_out = acceptance_code_3; // extended mode
|
1071 |
|
|
{1'h1, 5'd20} : data_out = acceptance_mask_0; // extended mode
|
1072 |
|
|
{1'h1, 5'd21} : data_out = acceptance_mask_1; // extended mode
|
1073 |
|
|
{1'h1, 5'd22} : data_out = acceptance_mask_2; // extended mode
|
1074 |
|
|
{1'h1, 5'd23} : data_out = acceptance_mask_3; // extended mode
|
1075 |
|
|
{1'h1, 5'd24} : data_out = 8'h0; // extended mode
|
1076 |
|
|
{1'h1, 5'd25} : data_out = 8'h0; // extended mode
|
1077 |
|
|
{1'h1, 5'd26} : data_out = 8'h0; // extended mode
|
1078 |
|
|
{1'h1, 5'd27} : data_out = 8'h0; // extended mode
|
1079 |
|
|
{1'h1, 5'd28} : data_out = 8'h0; // extended mode
|
1080 |
|
|
{1'h1, 5'd29} : data_out = {1'b0, rx_message_counter}; // extended mode
|
1081 |
|
|
{1'h1, 5'd31} : data_out = clock_divider; // extended mode
|
1082 |
|
|
{1'h0, 5'd00} : data_out = {3'b001, mode_basic[4:1], mode[0]}; // basic mode
|
1083 |
|
|
{1'h0, 5'd01} : data_out = 8'hff; // basic mode
|
1084 |
|
|
{1'h0, 5'd02} : data_out = status; // basic mode
|
1085 |
|
|
{1'h0, 5'd03} : data_out = {4'hf, irq_reg[3:0]}; // basic mode
|
1086 |
|
|
{1'h0, 5'd04} : data_out = reset_mode? acceptance_code_0 : 8'hff; // basic mode
|
1087 |
|
|
{1'h0, 5'd05} : data_out = reset_mode? acceptance_mask_0 : 8'hff; // basic mode
|
1088 |
|
|
{1'h0, 5'd06} : data_out = reset_mode? bus_timing_0 : 8'hff; // basic mode
|
1089 |
|
|
{1'h0, 5'd07} : data_out = reset_mode? bus_timing_1 : 8'hff; // basic mode
|
1090 |
|
|
{1'h0, 5'd10} : data_out = reset_mode? 8'hff : tx_data_0; // basic mode
|
1091 |
|
|
{1'h0, 5'd11} : data_out = reset_mode? 8'hff : tx_data_1; // basic mode
|
1092 |
|
|
{1'h0, 5'd12} : data_out = reset_mode? 8'hff : tx_data_2; // basic mode
|
1093 |
|
|
{1'h0, 5'd13} : data_out = reset_mode? 8'hff : tx_data_3; // basic mode
|
1094 |
|
|
{1'h0, 5'd14} : data_out = reset_mode? 8'hff : tx_data_4; // basic mode
|
1095 |
|
|
{1'h0, 5'd15} : data_out = reset_mode? 8'hff : tx_data_5; // basic mode
|
1096 |
|
|
{1'h0, 5'd16} : data_out = reset_mode? 8'hff : tx_data_6; // basic mode
|
1097 |
|
|
{1'h0, 5'd17} : data_out = reset_mode? 8'hff : tx_data_7; // basic mode
|
1098 |
|
|
{1'h0, 5'd18} : data_out = reset_mode? 8'hff : tx_data_8; // basic mode
|
1099 |
|
|
{1'h0, 5'd19} : data_out = reset_mode? 8'hff : tx_data_9; // basic mode
|
1100 |
|
|
{1'h0, 5'd31} : data_out = clock_divider; // basic mode
|
1101 |
|
|
default : data_out = 8'h0; // the rest is read as 0
|
1102 |
|
|
endcase
|
1103 |
66 |
mohor |
end
|
1104 |
|
|
|
1105 |
|
|
|
1106 |
|
|
// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
|
1107 |
|
|
assign data_overrun_irq_en = extended_mode ? data_overrun_irq_en_ext : overrun_irq_en_basic;
|
1108 |
|
|
assign error_warning_irq_en = extended_mode ? error_warning_irq_en_ext : error_irq_en_basic;
|
1109 |
|
|
assign transmit_irq_en = extended_mode ? transmit_irq_en_ext : transmit_irq_en_basic;
|
1110 |
|
|
assign receive_irq_en = extended_mode ? receive_irq_en_ext : receive_irq_en_basic;
|
1111 |
|
|
|
1112 |
|
|
|
1113 |
|
|
reg data_overrun_irq;
|
1114 |
|
|
always @ (posedge clk or posedge rst)
|
1115 |
|
|
begin
|
1116 |
|
|
if (rst)
|
1117 |
|
|
data_overrun_irq <= 1'b0;
|
1118 |
|
|
else if (overrun & (~overrun_q) & data_overrun_irq_en)
|
1119 |
|
|
data_overrun_irq <=#Tp 1'b1;
|
1120 |
|
|
else if (read_irq_reg)
|
1121 |
|
|
data_overrun_irq <=#Tp 1'b0;
|
1122 |
|
|
end
|
1123 |
|
|
|
1124 |
|
|
|
1125 |
|
|
reg transmit_irq;
|
1126 |
|
|
always @ (posedge clk or posedge rst)
|
1127 |
|
|
begin
|
1128 |
|
|
if (rst)
|
1129 |
|
|
transmit_irq <= 1'b0;
|
1130 |
|
|
else if (transmit_buffer_status & (~transmit_buffer_status_q) & transmit_irq_en)
|
1131 |
|
|
transmit_irq <=#Tp 1'b1;
|
1132 |
|
|
else if (read_irq_reg)
|
1133 |
|
|
transmit_irq <=#Tp 1'b0;
|
1134 |
|
|
end
|
1135 |
|
|
|
1136 |
|
|
|
1137 |
|
|
reg receive_irq;
|
1138 |
|
|
always @ (posedge clk or posedge rst)
|
1139 |
|
|
begin
|
1140 |
|
|
if (rst)
|
1141 |
|
|
receive_irq <= 1'b0;
|
1142 |
|
|
else if (release_buffer)
|
1143 |
|
|
receive_irq <=#Tp 1'b0;
|
1144 |
|
|
else if ((~info_empty) & (~receive_irq) & receive_irq_en)
|
1145 |
|
|
receive_irq <=#Tp 1'b1;
|
1146 |
|
|
end
|
1147 |
|
|
|
1148 |
|
|
|
1149 |
|
|
reg error_irq;
|
1150 |
|
|
always @ (posedge clk or posedge rst)
|
1151 |
|
|
begin
|
1152 |
|
|
if (rst)
|
1153 |
|
|
error_irq <= 1'b0;
|
1154 |
|
|
else if (((error_status ^ error_status_q) | (node_bus_off ^ node_bus_off_q)) & error_warning_irq_en)
|
1155 |
|
|
error_irq <=#Tp 1'b1;
|
1156 |
|
|
else if (read_irq_reg)
|
1157 |
|
|
error_irq <=#Tp 1'b0;
|
1158 |
|
|
end
|
1159 |
|
|
|
1160 |
|
|
|
1161 |
|
|
reg bus_error_irq;
|
1162 |
|
|
always @ (posedge clk or posedge rst)
|
1163 |
|
|
begin
|
1164 |
|
|
if (rst)
|
1165 |
|
|
bus_error_irq <= 1'b0;
|
1166 |
|
|
else if (set_bus_error_irq & bus_error_irq_en)
|
1167 |
|
|
bus_error_irq <=#Tp 1'b1;
|
1168 |
|
|
else if (read_irq_reg)
|
1169 |
|
|
bus_error_irq <=#Tp 1'b0;
|
1170 |
|
|
end
|
1171 |
|
|
|
1172 |
|
|
|
1173 |
|
|
reg arbitration_lost_irq;
|
1174 |
|
|
always @ (posedge clk or posedge rst)
|
1175 |
|
|
begin
|
1176 |
|
|
if (rst)
|
1177 |
|
|
arbitration_lost_irq <= 1'b0;
|
1178 |
|
|
else if (set_arbitration_lost_irq & arbitration_lost_irq_en)
|
1179 |
|
|
arbitration_lost_irq <=#Tp 1'b1;
|
1180 |
|
|
else if (read_irq_reg)
|
1181 |
|
|
arbitration_lost_irq <=#Tp 1'b0;
|
1182 |
|
|
end
|
1183 |
|
|
|
1184 |
|
|
|
1185 |
|
|
|
1186 |
|
|
reg error_passive_irq;
|
1187 |
|
|
always @ (posedge clk or posedge rst)
|
1188 |
|
|
begin
|
1189 |
|
|
if (rst)
|
1190 |
|
|
error_passive_irq <= 1'b0;
|
1191 |
|
|
else if ((node_error_passive & (~node_error_passive_q) | (~node_error_passive) & node_error_passive_q & node_error_active) & error_passive_irq_en)
|
1192 |
|
|
error_passive_irq <=#Tp 1'b1;
|
1193 |
|
|
else if (read_irq_reg)
|
1194 |
|
|
error_passive_irq <=#Tp 1'b0;
|
1195 |
|
|
end
|
1196 |
|
|
|
1197 |
|
|
|
1198 |
|
|
|
1199 |
|
|
assign irq_reg = {bus_error_irq, arbitration_lost_irq, error_passive_irq, 1'b0, data_overrun_irq, error_irq, transmit_irq, receive_irq};
|
1200 |
|
|
|
1201 |
|
|
assign irq = data_overrun_irq | transmit_irq | receive_irq | error_irq | bus_error_irq | arbitration_lost_irq | error_passive_irq;
|
1202 |
|
|
|
1203 |
|
|
|
1204 |
|
|
|
1205 |
|
|
|
1206 |
|
|
|
1207 |
|
|
endmodule
|