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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.23  2003/09/05 12:46:41  mohor
// ALTERA_RAM supported.
//
// Revision 1.22  2003/08/20 09:59:16  mohor
// Artisan RAM fixed (when not using BIST).
//
// Revision 1.21  2003/08/14 16:04:52  simons
// Artisan ram instances added.
//
// Revision 1.20  2003/07/16 14:00:45  mohor
// Fixed according to the linter.
//
// Revision 1.19  2003/07/03 09:30:44  mohor
// PCI_BIST replaced with CAN_BIST.
//
// Revision 1.18  2003/06/27 22:14:23  simons
// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
//
// Revision 1.17  2003/06/27 20:56:15  simons
// Virtual silicon ram instances added.
//
// Revision 1.16  2003/06/18 23:03:44  mohor
// Typo fixed.
//
// Revision 1.15  2003/06/11 09:37:05  mohor
// overrun and length_info fifos are initialized at the end of reset.
//
// Revision 1.14  2003/03/05 15:02:30  mohor
// Xilinx RAM added.
//
// Revision 1.13  2003/03/01 22:53:33  mohor
// Actel APA ram supported.
//
// Revision 1.12  2003/02/19 14:44:03  mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.11  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10  2003/02/11 00:56:06  mohor
// Wishbone interface added.
//
// Revision 1.9  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.8  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.7  2003/01/17 17:44:31  mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
  fifo_selected,
 
  reset_mode,
  release_buffer,
  extended_mode,
  overrun,
  info_empty,
  info_cnt
 
`ifdef CAN_BIST
  ,
  mbist_si_i,
  mbist_so_o,
  mbist_ctrl_i
`endif
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [5:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
input         fifo_selected;
 
output  [7:0] data_out;
output        overrun;
output        info_empty;
output  [6:0] info_cnt;
 
`ifdef CAN_BIST
input         mbist_si_i;
output        mbist_so_o;
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
wire          mbist_s_0;
`endif
 
`ifdef ALTERA_RAM
`else
`ifdef ACTEL_APA_RAM
`else
`ifdef XILINX_RAM
`else
`ifdef ARTISAN_RAM
  reg           overrun_info[0:63];
`else
`ifdef VIRTUALSILICON_RAM
  reg           overrun_info[0:63];
`else
  reg     [7:0] fifo [0:63];
  reg     [3:0] length_fifo[0:63];
  reg           overrun_info[0:63];
`endif
`endif
`endif
`endif
`endif
 
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg     [6:0] info_cnt;
reg           latch_overrun;
reg           initialize_memories;
 
wire    [3:0] length_info;
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
wire          info_full;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <=#Tp 1'b0;
  else if (reset_mode)
    wr_q <=#Tp 1'b0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 4'h0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 4'h0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 6'h0;
  else if (write_length_info & (~info_full) | initialize_memories)
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
  else if (reset_mode)
    wr_info_pointer <=#Tp 6'h0;
end
 
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 6'h0;
  else if (reset_mode)
    rd_info_pointer <=#Tp 6'h0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 5'h0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
  else if (reset_mode)
    rd_pointer <=#Tp 5'h0;
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 5'h0;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
  else if (reset_mode)
    wr_pointer <=#Tp 5'h0;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 1'b0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 1'b0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 7'h0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
  else if (reset_mode)
    fifo_cnt <=#Tp 7'h0;
end
 
assign fifo_full = fifo_cnt == 7'd64;
assign fifo_empty = fifo_cnt == 7'd0;
 
 
// Counting data in length_fifo and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    info_cnt <=#Tp 7'h0;
  else if (reset_mode)
    info_cnt <=#Tp 7'h0;
  else if (write_length_info ^ release_buffer)
    begin
      if (release_buffer & (~info_empty))
        info_cnt <=#Tp info_cnt - 1'b1;
      else if (write_length_info & (~info_full))
        info_cnt <=#Tp info_cnt + 1'b1;
    end
end
 
assign info_full = info_cnt == 7'd64;
assign info_empty = info_cnt == 7'd0;
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    read_address = rd_pointer + (addr - 6'd16);
  else                    // normal mode
    read_address = rd_pointer + (addr - 6'd20);
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    initialize_memories <= 1'b1;
  else if (&wr_info_pointer)
    initialize_memories <=#Tp 1'b0;
end
 
 
`ifdef ALTERA_RAM
//  altera_ram_64x8_sync fifo
  lpm_ram_dp fifo
  (
    .q         (data_out),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      (data_in),
    .wren      (~(wr & (~fifo_full))),
    .rden      (~fifo_selected),
    .wraddress (wr_pointer),
    .rdaddress (read_address)
  );
  defparam fifo.lpm_width = 8;
  defparam fifo.lpm_widthad = 6;
 
 
//  altera_ram_64x4_sync info_fifo
  lpm_ram_dp info_fifo
  (
    .q         (length_info),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      (len_cnt & {4{~initialize_memories}}),
    .wren      (~(write_length_info & (~info_full) | initialize_memories)),
    .rden      (1'b0),                   // always enabled
    .wraddress (wr_info_pointer),
    .rdaddress (rd_info_pointer)
  );
  defparam info_fifo.lpm_width = 4;
  defparam info_fifo.lpm_widthad = 6;
 
 
//  altera_ram_64x1_sync overrun_fifo
  lpm_ram_dp overrun_fifo
  (
    .q         (overrun),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .wren      (~(write_length_info & (~info_full) | initialize_memories)),
    .rden      (1'b0),                   // always enabled
    .wraddress (wr_info_pointer),
    .rdaddress (rd_info_pointer)
  );
  defparam overrun_fifo.lpm_width = 1;
  defparam overrun_fifo.lpm_widthad = 6;
 
`else
`ifdef ACTEL_APA_RAM
  actel_ram_64x8_sync fifo
  (
    .DO      (data_out),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (data_in),
    .PO      (),                       // parity not used
    .WRB     (~(wr & (~fifo_full))),
    .RDB     (~fifo_selected),
    .WADDR   (wr_pointer),
    .RADDR   (read_address)
  );
 
 
  actel_ram_64x4_sync info_fifo
  (
    .DO      (length_info),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (len_cnt & {4{~initialize_memories}}),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
 
 
  actel_ram_64x1_sync overrun_fifo
  (
    .DO      (overrun),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
`else
`ifdef XILINX_RAM
 
/*
  ram_64x8_sync fifo
  (
    .addra(wr_pointer),
    .addrb(read_address),
    .clka(clk),
    .clkb(clk),
    .dina(data_in),
    .doutb(data_out),
    .wea(wr & (~fifo_full))
  );
*/
 
  RAMB4_S8_S8 fifo
  (
    .DOA(),
    .DOB(data_out),
    .ADDRA({3'h0, wr_pointer}),
    .CLKA(clk),
    .DIA(data_in),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(wr & (~fifo_full)),
    .ADDRB({3'h0, read_address}),
    .CLKB(clk),
    .DIB(8'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
 
/*
  ram_64x4_sync info_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(len_cnt),
    .doutb(length_info),
    .wea(write_length_info & (~info_full))
  );
*/
  RAMB4_S4_S4 info_fifo
  (
    .DOA(),
    .DOB(length_info),
    .ADDRA({4'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA(len_cnt & {4{~initialize_memories}}),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({4'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(4'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
/*
  ram_64x1_sync overrun_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(latch_overrun | (wr & fifo_full)),
    .doutb(overrun),
    .wea(write_length_info & (~info_full))
  );
*/
 
 
  RAMB4_S1_S1 overrun_fifo
  (
    .DOA(),
    .DOB(overrun),
    .ADDRA({6'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({6'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(1'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
`else
`ifdef VIRTUALSILICON_RAM
 
`ifdef CAN_BIST
    vs_hdtp_64x8_bist fifo
`else
    vs_hdtp_64x8 fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (read_address),
        .WADR       (wr_pointer),
        .DI         (data_in),
        .DOUT       (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full)))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .mbist_si_i   (mbist_si_i),
        .mbist_so_o   (mbist_s_0),
        .mbist_ctrl_i   (mbist_ctrl_i)
    `endif
    );
 
`ifdef CAN_BIST
    vs_hdtp_64x4_bist info_fifo
`else
    vs_hdtp_64x4 info_fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (rd_info_pointer),
        .WADR       (wr_info_pointer),
        .DI         (len_cnt & {4{~initialize_memories}}),
        .DOUT       (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .mbist_si_i   (mbist_s_0),
        .mbist_so_o   (mbist_so_o),
        .mbist_ctrl_i   (mbist_ctrl_i)
    `endif
    );
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
`ifdef ARTISAN_RAM
 
`ifdef CAN_BIST
    art_hstp_64x8_bist fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (read_address),
        .AW         (wr_pointer),
        .D          (data_in),
        .Q          (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full))),
        .mbist_si_i   (mbist_si_i),
        .mbist_so_o   (mbist_s_0),
        .mbist_ctrl_i   (mbist_ctrl_i)
    );
    art_hstp_64x4_bist info_fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (rd_info_pointer),
        .AW         (wr_info_pointer),
        .D          (len_cnt & {4{~initialize_memories}}),
        .Q          (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories)),
        .mbist_si_i   (mbist_s_0),
        .mbist_so_o   (mbist_so_o),
        .mbist_ctrl_i   (mbist_ctrl_i)
    );
`else
    art_hsdp_64x8 fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (read_address),
        .AB         (wr_pointer),
        .DA         (8'h00),
        .DB         (data_in),
        .QA         (data_out),
        .QB         (),
        .OENA       (~fifo_selected),
        .OENB       (1'b1),
        .WENA       (1'b1),
        .WENB       (~(wr & (~fifo_full)))
    );
    art_hsdp_64x4 info_fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (rd_info_pointer),
        .AB         (wr_info_pointer),
        .DA         (4'h0),
        .DB         (len_cnt & {4{~initialize_memories}}),
        .QA         (length_info),
        .QB         (),
        .OENA       (1'b0),
        .OENB       (1'b1),
        .WENA       (1'b1),
        .WENB       (~(write_length_info & (~info_full) | initialize_memories))
    );
`endif
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
  // writing data to fifo
  always @ (posedge clk)
  begin
    if (wr & (~fifo_full))
      fifo[wr_pointer] <=#Tp data_in;
  end
 
  // reading from fifo
  assign data_out = fifo[read_address];
 
 
  // writing length_fifo
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
  end
 
 
  // reading length_fifo
  assign length_info = length_fifo[rd_info_pointer];
 
  // overrun_info
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
  end
 
 
  // reading overrun
  assign overrun = overrun_info[rd_info_pointer];
 
 
`endif
`endif
`endif
`endif
`endif
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002, 2003 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	11	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	130	markom	`// Revision 1.23 2003/09/05 12:46:41 mohor`
54			`// ALTERA_RAM supported.`
55			`//`
56	124	mohor	`// Revision 1.22 2003/08/20 09:59:16 mohor`
57			`// Artisan RAM fixed (when not using BIST).`
58			`//`
59	118	mohor	`// Revision 1.21 2003/08/14 16:04:52 simons`
60			`// Artisan ram instances added.`
61			`//`
62	115	simons	`// Revision 1.20 2003/07/16 14:00:45 mohor`
63			`// Fixed according to the linter.`
64			`//`
65	109	mohor	`// Revision 1.19 2003/07/03 09:30:44 mohor`
66			`// PCI_BIST replaced with CAN_BIST.`
67			`//`
68	99	mohor	`// Revision 1.18 2003/06/27 22:14:23 simons`
69			`// Overrun fifo implemented with FFs, because it is not possible to create such a memory.`
70			`//`
71	97	simons	`// Revision 1.17 2003/06/27 20:56:15 simons`
72			`// Virtual silicon ram instances added.`
73			`//`
74	95	simons	`// Revision 1.16 2003/06/18 23:03:44 mohor`
75			`// Typo fixed.`
76			`//`
77	85	mohor	`// Revision 1.15 2003/06/11 09:37:05 mohor`
78			`// overrun and length_info fifos are initialized at the end of reset.`
79			`//`
80	73	mohor	`// Revision 1.14 2003/03/05 15:02:30 mohor`
81			`// Xilinx RAM added.`
82			`//`
83	51	mohor	`// Revision 1.13 2003/03/01 22:53:33 mohor`
84			`// Actel APA ram supported.`
85			`//`
86	48	mohor	`// Revision 1.12 2003/02/19 14:44:03 mohor`
87			`// CAN core finished. Host interface added. Registers finished.`
88			`// Synchronization to the wishbone finished.`
89			`//`
90	39	mohor	`// Revision 1.11 2003/02/14 20:17:01 mohor`
91			`// Several registers added. Not finished, yet.`
92			`//`
93	35	mohor	`// Revision 1.10 2003/02/11 00:56:06 mohor`
94			`// Wishbone interface added.`
95			`//`
96	31	mohor	`// Revision 1.9 2003/02/09 02:24:33 mohor`
97			`// Bosch license warning added. Error counters finished. Overload frames`
98			`// still need to be fixed.`
99			`//`
100	28	mohor	`// Revision 1.8 2003/01/31 01:13:38 mohor`
101			`// backup.`
102			`//`
103	24	mohor	`// Revision 1.7 2003/01/17 17:44:31 mohor`
104			`// Fifo corrected to be synthesizable.`
105			`//`
106	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
107	31	mohor	`// When a frame with "remote request" is received, no data is stored`
108			`// to fifo, just the frame information (identifier, ...). Data length`
109			`// that is stored is the received data length and not the actual data`
110			`// length that is stored to fifo.`
111	23	mohor	`//`
112	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
113			`// Addresses corrected to decimal values (previously hex).`
114			`//`
115	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
116			`// rx_fifo is now working.`
117			`//`
118	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
119			`// rx fifo added. Not 100 % verified, yet.`
120			`//`
121	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
122			`// Temporary files (backup).`
123			`//`
124	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
125			`// Acceptance filter added.`
126	11	mohor	`//`
127			`//`
128			`//`
129	13	mohor	`//`
130	11	mohor
131			`// synopsys translate_off`
132			`include "timescale.v"
133			`// synopsys translate_on`
134			`include "can_defines.v"
135
136			`module can_fifo`
137			`(`
138			`clk,`
139			`rst,`
140
141			`wr,`
142
143			`data_in,`
144	14	mohor	`addr,`
145	11	mohor	`data_out,`
146	48	mohor	`fifo_selected,`
147	11	mohor
148			`reset_mode,`
149	14	mohor	`release_buffer,`
150	35	mohor	`extended_mode,`
151			`overrun,`
152	39	mohor	`info_empty,`
153			`info_cnt`
154	13	mohor
155	95	simons	`ifdef CAN_BIST
156			`,`
157	130	markom	`mbist_si_i,`
158			`mbist_so_o,`
159			`mbist_ctrl_i`
160	95	simons	`endif
161	11	mohor	`);`
162
163			`parameter Tp = 1;`
164
165			`input clk;`
166			`input rst;`
167			`input wr;`
168			`input [7:0] data_in;`
169	109	mohor	`input [5:0] addr;`
170	11	mohor	`input reset_mode;`
171			`input release_buffer;`
172	14	mohor	`input extended_mode;`
173	48	mohor	`input fifo_selected;`
174	11	mohor
175	13	mohor	`output [7:0] data_out;`
176	35	mohor	`output overrun;`
177			`output info_empty;`
178	39	mohor	`output [6:0] info_cnt;`
179	11	mohor
180	95	simons	`ifdef CAN_BIST
181	130	markom	`input mbist_si_i;`
182			`output mbist_so_o;`
183			input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
184			`wire mbist_s_0;`
185	95	simons	`endif
186
187	124	mohor	`ifdef ALTERA_RAM
188			`else
189	48	mohor	`ifdef ACTEL_APA_RAM
190			`else
191	51	mohor	`ifdef XILINX_RAM
192			`else
193	115	simons	`ifdef ARTISAN_RAM
194			`reg overrun_info[0:63];`
195			`else
196	95	simons	`ifdef VIRTUALSILICON_RAM
197	97	simons	`reg overrun_info[0:63];`
198	95	simons	`else
199	48	mohor	`reg [7:0] fifo [0:63];`
200			`reg [3:0] length_fifo[0:63];`
201			`reg overrun_info[0:63];`
202			`endif
203	51	mohor	`endif
204	95	simons	`endif
205	115	simons	`endif
206	124	mohor	`endif
207	11	mohor
208			`reg [5:0] rd_pointer;`
209			`reg [5:0] wr_pointer;`
210	14	mohor	`reg [5:0] read_address;`
211	16	mohor	`reg [5:0] wr_info_pointer;`
212			`reg [5:0] rd_info_pointer;`
213	13	mohor	`reg wr_q;`
214			`reg [3:0] len_cnt;`
215	16	mohor	`reg [6:0] fifo_cnt;`
216	24	mohor	`reg [6:0] info_cnt;`
217	16	mohor	`reg latch_overrun;`
218	73	mohor	`reg initialize_memories;`
219	11	mohor
220	48	mohor	`wire [3:0] length_info;`
221	13	mohor	`wire write_length_info;`
222	16	mohor	`wire fifo_empty;`
223			`wire fifo_full;`
224	24	mohor	`wire info_full;`
225	11	mohor
226	13	mohor	`assign write_length_info = (~wr) & wr_q;`
227
228			`// Delayed write signal`
229			`always @ (posedge clk or posedge rst)`
230			`begin`
231			`if (rst)`
232	109	mohor	`wr_q <=#Tp 1'b0;`
233	13	mohor	`else if (reset_mode)`
234	109	mohor	`wr_q <=#Tp 1'b0;`
235	13	mohor	`else`
236			`wr_q <=#Tp wr;`
237			`end`
238
239
240			`// length counter`
241			`always @ (posedge clk or posedge rst)`
242			`begin`
243			`if (rst)`
244	109	mohor	`len_cnt <= 4'h0;`
245	13	mohor	`else if (reset_mode \| write_length_info)`
246	109	mohor	`len_cnt <=#Tp 4'h0;`
247	16	mohor	`else if (wr & (~fifo_full))`
248	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
249			`end`
250
251
252			`// wr_info_pointer`
253			`always @ (posedge clk or posedge rst)`
254			`begin`
255			`if (rst)`
256	109	mohor	`wr_info_pointer <= 6'h0;`
257	73	mohor	`else if (write_length_info & (~info_full) \| initialize_memories)`
258			`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
259	13	mohor	`else if (reset_mode)`
260	109	mohor	`wr_info_pointer <=#Tp 6'h0;`
261	13	mohor	`end`
262
263
264
265			`// rd_info_pointer`
266	11	mohor	`always @ (posedge clk or posedge rst)`
267			`begin`
268			`if (rst)`
269	109	mohor	`rd_info_pointer <= 6'h0;`
270	11	mohor	`else if (reset_mode)`
271	109	mohor	`rd_info_pointer <=#Tp 6'h0;`
272	16	mohor	`else if (release_buffer & (~fifo_empty))`
273	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
274	11	mohor	`end`
275
276
277			`// rd_pointer`
278			`always @ (posedge clk or posedge rst)`
279			`begin`
280			`if (rst)`
281	109	mohor	`rd_pointer <= 5'h0;`
282	16	mohor	`else if (release_buffer & (~fifo_empty))`
283	109	mohor	`rd_pointer <=#Tp rd_pointer + {2'h0, length_info};`
284	11	mohor	`else if (reset_mode)`
285	109	mohor	`rd_pointer <=#Tp 5'h0;`
286	11	mohor	`end`
287
288
289			`// wr_pointer`
290			`always @ (posedge clk or posedge rst)`
291			`begin`
292			`if (rst)`
293	109	mohor	`wr_pointer <= 5'h0;`
294	16	mohor	`else if (wr & (~fifo_full))`
295	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
296	11	mohor	`else if (reset_mode)`
297	109	mohor	`wr_pointer <=#Tp 5'h0;`
298	11	mohor	`end`
299
300
301	16	mohor	`// latch_overrun`
302			`always @ (posedge clk or posedge rst)`
303			`begin`
304			`if (rst)`
305	109	mohor	`latch_overrun <= 1'b0;`
306	16	mohor	`else if (reset_mode \| write_length_info)`
307	109	mohor	`latch_overrun <=#Tp 1'b0;`
308	16	mohor	`else if (wr & fifo_full)`
309			`latch_overrun <=#Tp 1'b1;`
310			`end`
311
312
313			`// Counting data in fifo`
314			`always @ (posedge clk or posedge rst)`
315			`begin`
316			`if (rst)`
317	109	mohor	`fifo_cnt <= 7'h0;`
318	16	mohor	`else if (wr & (~release_buffer) & (~fifo_full))`
319			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
320			`else if ((~wr) & release_buffer & (~fifo_empty))`
321	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};`
322	16	mohor	`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
323	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;`
324	16	mohor	`else if (reset_mode)`
325	109	mohor	`fifo_cnt <=#Tp 7'h0;`
326	16	mohor	`end`
327
328	109	mohor	`assign fifo_full = fifo_cnt == 7'd64;`
329			`assign fifo_empty = fifo_cnt == 7'd0;`
330	16	mohor
331
332	48	mohor	`// Counting data in length_fifo and overrun_info fifo`
333	24	mohor	`always @ (posedge clk or posedge rst)`
334			`begin`
335			`if (rst)`
336	109	mohor	`info_cnt <=#Tp 7'h0;`
337			`else if (reset_mode)`
338			`info_cnt <=#Tp 7'h0;`
339	24	mohor	`else if (write_length_info ^ release_buffer)`
340			`begin`
341			`if (release_buffer & (~info_empty))`
342			`info_cnt <=#Tp info_cnt - 1'b1;`
343			`else if (write_length_info & (~info_full))`
344			`info_cnt <=#Tp info_cnt + 1'b1;`
345			`end`
346			`end`
347
348	109	mohor	`assign info_full = info_cnt == 7'd64;`
349			`assign info_empty = info_cnt == 7'd0;`
350	16	mohor
351	24	mohor
352	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
353			`always @ (extended_mode or rd_pointer or addr)`
354			`begin`
355			`if (extended_mode) // extended mode`
356	109	mohor	`read_address = rd_pointer + (addr - 6'd16);`
357	14	mohor	`else // normal mode`
358	109	mohor	`read_address = rd_pointer + (addr - 6'd20);`
359	14	mohor	`end`
360	11	mohor
361
362	73	mohor	`always @ (posedge clk or posedge rst)`
363			`begin`
364			`if (rst)`
365	109	mohor	`initialize_memories <= 1'b1;`
366	73	mohor	`else if (&wr_info_pointer)`
367			`initialize_memories <=#Tp 1'b0;`
368			`end`
369	14	mohor
370	73	mohor
371	124	mohor	`ifdef ALTERA_RAM
372			`// altera_ram_64x8_sync fifo`
373			`lpm_ram_dp fifo`
374			`(`
375			`.q (data_out),`
376			`.rdclock (clk),`
377			`.wrclock (clk),`
378			`.data (data_in),`
379			`.wren (~(wr & (~fifo_full))),`
380			`.rden (~fifo_selected),`
381			`.wraddress (wr_pointer),`
382			`.rdaddress (read_address)`
383			`);`
384			`defparam fifo.lpm_width = 8;`
385			`defparam fifo.lpm_widthad = 6;`
386
387
388			`// altera_ram_64x4_sync info_fifo`
389			`lpm_ram_dp info_fifo`
390			`(`
391			`.q (length_info),`
392			`.rdclock (clk),`
393			`.wrclock (clk),`
394			`.data (len_cnt & {4{~initialize_memories}}),`
395			`.wren (~(write_length_info & (~info_full) \| initialize_memories)),`
396			`.rden (1'b0), // always enabled`
397			`.wraddress (wr_info_pointer),`
398			`.rdaddress (rd_info_pointer)`
399			`);`
400			`defparam info_fifo.lpm_width = 4;`
401			`defparam info_fifo.lpm_widthad = 6;`
402
403
404			`// altera_ram_64x1_sync overrun_fifo`
405			`lpm_ram_dp overrun_fifo`
406			`(`
407			`.q (overrun),`
408			`.rdclock (clk),`
409			`.wrclock (clk),`
410			`.data ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
411			`.wren (~(write_length_info & (~info_full) \| initialize_memories)),`
412			`.rden (1'b0), // always enabled`
413			`.wraddress (wr_info_pointer),`
414			`.rdaddress (rd_info_pointer)`
415			`);`
416			`defparam overrun_fifo.lpm_width = 1;`
417			`defparam overrun_fifo.lpm_widthad = 6;`
418
419			`else
420	48	mohor	`ifdef ACTEL_APA_RAM
421			`actel_ram_64x8_sync fifo`
422			`(`
423			`.DO (data_out),`
424			`.RCLOCK (clk),`
425			`.WCLOCK (clk),`
426			`.DI (data_in),`
427			`.PO (), // parity not used`
428			`.WRB (~(wr & (~fifo_full))),`
429			`.RDB (~fifo_selected),`
430			`.WADDR (wr_pointer),`
431			`.RADDR (read_address)`
432			`);`
433	14	mohor
434
435	48	mohor	`actel_ram_64x4_sync info_fifo`
436			`(`
437			`.DO (length_info),`
438			`.RCLOCK (clk),`
439			`.WCLOCK (clk),`
440	73	mohor	`.DI (len_cnt & {4{~initialize_memories}}),`
441	48	mohor	`.PO (), // parity not used`
442	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
443	48	mohor	`.RDB (1'b0), // always enabled`
444			`.WADDR (wr_info_pointer),`
445			`.RADDR (rd_info_pointer)`
446			`);`
447	14	mohor
448
449	48	mohor	`actel_ram_64x1_sync overrun_fifo`
450			`(`
451			`.DO (overrun),`
452			`.RCLOCK (clk),`
453			`.WCLOCK (clk),`
454	73	mohor	`.DI ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
455	48	mohor	`.PO (), // parity not used`
456	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
457	48	mohor	`.RDB (1'b0), // always enabled`
458			`.WADDR (wr_info_pointer),`
459			`.RADDR (rd_info_pointer)`
460			`);`
461			`else
462	51	mohor	`ifdef XILINX_RAM
463
464			`/*`
465			`ram_64x8_sync fifo`
466			`(`
467			`.addra(wr_pointer),`
468			`.addrb(read_address),`
469			`.clka(clk),`
470			`.clkb(clk),`
471			`.dina(data_in),`
472			`.doutb(data_out),`
473			`.wea(wr & (~fifo_full))`
474			`);`
475			`*/`
476
477			`RAMB4_S8_S8 fifo`
478			`(`
479			`.DOA(),`
480			`.DOB(data_out),`
481			`.ADDRA({3'h0, wr_pointer}),`
482			`.CLKA(clk),`
483			`.DIA(data_in),`
484			`.ENA(1'b1),`
485			`.RSTA(1'b0),`
486			`.WEA(wr & (~fifo_full)),`
487			`.ADDRB({3'h0, read_address}),`
488			`.CLKB(clk),`
489			`.DIB(8'h0),`
490			`.ENB(1'b1),`
491			`.RSTB(1'b0),`
492			`.WEB(1'b0)`
493			`);`
494
495
496
497			`/*`
498			`ram_64x4_sync info_fifo`
499			`(`
500			`.addra(wr_info_pointer),`

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